JPH06292152A - Video signal converter - Google Patents

Abstract

PURPOSE:To make the capacity of a memory for a segmentation display function and a line memory for a flicker elimination filter small. CONSTITUTION:A non-interlace video signal from a computer 1 is segmented in the horizontal direction by a horizontal segmentation circuit 10 provided with a line memory by one NTSC line. Furthermore, after the signal is subject to line flicker elimination in a filter 11, the result is segmented in the vertical direction by a vertical segmentation circuit 12 provided with two field memories by one NTSC field and the time axis is expanded and the resulting signal is converted into an interlace NTSC signal with 240 lines per field forming part of a computer pattern.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal converter for converting a video signal from a computer such as a personal computer into an NTSC video signal.

[0002]

2. Description of the Related Art Conventionally, N video signals from a computer have been used.
A video signal conversion device for displaying on a TSC monitor is described in, for example, Japanese Patent Application Laid-Open No. 63-82180.

In this type of video signal conversion apparatus, there is a cutout display function of setting an area of an arbitrary size on the screen of a computer, cutting out an image of this area and displaying it on an NTSC monitor.

FIG. 8 shows a conventional video signal converter having the cutout display function. The non-interlaced video signal from the computer 1 is AD-converted by the AD converter 2.

A line flicker due to interlace is removed from the AD conversion output by a filter 3 formed of a vertical low pass filter.

Next, the output of the filter 3 is written in the frame memory 4 composed of two field memories.
This frame memory has, for example, a capacity corresponding to pixels 1280 (H) × 1024 (V) for one screen of the computer, and writing is controlled by the write control circuit 5 based on the synchronization signal from the computer 1.

The reading from the frame memory 4 is performed by the interlace by the read control circuit 6 based on the external synchronizing signal for NTSC.

Here, when it is desired to cut out and display a part of the computer screen, a cutout area designating signal is supplied to the read control circuit to read only the data corresponding to the cutout area from the frame memory 4.

The data read from the frame memory 4 is converted into an analog signal by the DA converter 7.

The video signal from the computer 1 is RG.
It is a B parallel signal, and although only one system is shown from the AD converter to the DA converter in the drawing, it is actually provided with three systems.

Then, the RGB signal from the DA converter 7 is applied to the matrix circuit 8 for the luminance signal Y and the color difference signals RY and B-.
After Y is created, it is encoded by an encoder into an NTSC signal. This encoded NTSC signal is NT
It is supplied directly to the SC monitor or recorded on a VTR or the like for use.

[0012]

By the way, since the number of pixels for one screen of a computer is usually larger than that for one screen of NTSC, the frame memory 4 in the above apparatus needs to have a larger capacity than that for NTSC.

Further, the line memory forming the filter 3 needs to have a large capacity for one line of the computer screen.

According to the present invention, the frame memory used for the cutout display function can be made smaller in capacity than one computer screen, and the line memory used for the flicker removing filter can also be made small in capacity. A signal converter is provided.

[0015]

SUMMARY OF THE INVENTION The present invention is a video signal converter for converting a first video signal of the first standard into a second video signal of the second standard, which has less one screen of data than the first standard. In the apparatus, it corresponds to an image memory that stores data for one screen of the second video signal and a size for one screen of the second video signal at an arbitrary position within one screen of the first video signal. An area designating means for designating an area, a writing means for writing data corresponding to the area designated by the area designating means into the image memory, and a reading means for reading data from the image memory according to the second standard. This is a video signal conversion device.

[0016]

According to the present invention, the writing means writes only the data of the area designated by the area designating means in the image memory, and the reading means reads the data in accordance with the second standard.
A part of the video signal is cut out and converted into a second video signal.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a schematic view of the cutout display function in this embodiment. That is, a partial area P2 of the computer screen P1 of 1280 × 1024 pixels is cut out and
Display on C monitor. This area P2 has the number of pixels corresponding to one screen of NTSC1 of 640 × 480 pixels, and the cut out data is displayed on the NTSC monitor without performing enlargement (interpolation) or reduction (thinning-out) processing. Also,
The size of the region P2 is constant for the size of one NTSC screen, but the cutout position can be set arbitrarily.

FIG. 2 shows a schematic block diagram of the apparatus of this embodiment. The same parts as those in FIG.

The video signal of the computer after AD conversion is
First, it is supplied to the horizontal cutting circuit 10. As will be described later, the horizontal cutout circuit 10 includes a line memory for one NTSC line, so that the NTSC equivalent of one line of data in the cutout area is high speed (96 MHz).
And write at low speed (48 MHz). By this processing, the processing in the vertical cutout circuit described later can be performed at low speed.

The output of the horizontal cutting circuit 10 is NT.
It is supplied to the vertical cutout circuit 12 through a flicker removal filter 11 having a line memory for SC1 lines.

This vertical cutout circuit 12 is an NTSC 1
Of the data from the computer which has a memory for frames and which is cut out in the horizontal direction by the horizontal cutout circuit 10, the data cut out in 480 lines in the vertical direction is selected and written at a speed of 48 MHz and non-interlaced. , 12 MHz and interlaced.

The horizontal cutout circuit 10 is provided separately from the vertical cutout circuit 12 because the vertical cutout circuit 12 performs the processing at a low speed as described above, and the vertical cutout circuit 12 can perform the processing at a high speed. Then, it is possible to omit the horizontal cutout circuit 10 and simultaneously perform the horizontal and vertical cutout processing by the vertical cutout circuit.

A cut-out position setting circuit 15 sets the cut-out position by controlling the write timing to the line memory in the horizontal cut-out circuit 10 and the memory in the vertical cut-out circuit 12.

Next, details of the horizontal cutting circuit 10 which is a feature of this embodiment will be described with reference to FIG.

The horizontal cutout circuit 10 is a line memory LM.
1. A write address counter 100 for controlling writing in the line memory, a read address counter 101 for controlling reading, a delay circuit 102 for delaying a line memory address reset signal which will be described later, and a 96 MHz write clock divided by two. And a frequency dividing circuit 103 for generating a read clock of 48 MHz.

The write control circuit 13 is a sync separation circuit 130 for separating the horizontal sync signal and the vertical sync signal from the composite sync signal from the computer 1, and is reset by the horizontal sync signal. When the write clock is counted by a predetermined number, a line memory address reset signal is output. Is reset by the first counter 131 for generating
A second counter 1 that generates a frame memory address reset signal when a predetermined number of counter output pulses are counted.
32 and 32.

The filter 11 is a line memory LM.
2, the coefficient multipliers 110 and 111, and the adder 112 form a vertical low-pass filter.

The horizontal synchronizing signal of the computer is NTS.
The frequency is about 4 times that of C, 60 kHz, and the vertical synchronizing signal is 60 Hz, which is the same as NTSC.

Next, the operation of the above circuit will be described with reference to FIG.

First, the first counter 131 is reset by the horizontal synchronizing signal and starts counting the write clock. The count number of this first counter is set by the horizontal cut-out position data from the cut-out position setting circuit 15. When the set number is counted, a line memory address reset signal is generated. The write address counter 100 is reset by the line memory address reset signal, and the write address is supplied to the line memory LM1 according to the write clock.

Therefore, the line memory LM1 starts writing the input data sequentially from the address 1. When the write address counter 100 counts 640, the counting operation is stopped and the writing is stopped. That is, data for one NTSC line is written in the line memory LM1 during one horizontal scanning period of a computer signal.

On the other hand, the line memory address reset signal is delayed by the delay circuit 102 by at least one read clock. The read signal counter 101 is reset by this delay signal and supplies the read address to the line memory LM1.

Then, the data written in the line memory LM1 is sequentially read from the address 1 by the read clock of 48 MHZ. Read address counter 10
When 1 counts 640, the counting operation is stopped and the reading is stopped. That is, NTSC1 line worth of data is read from the line memory LM1 in a time twice as long as writing, and the time axis is doubled.

Therefore, the horizontal cutout circuit 10 cuts out and outputs a screen having a width of NTSC in the horizontal direction of the computer screen.

The output of the horizontal cutout circuit 10 is supplied to the vertical cutout circuit 12 after the line flicker is removed by the filter 11.

Further, the second counter 132 is set with a count number based on the vertical cut-out position data from the cut-out position setting circuit 15, and when a predetermined number is counted, a frame memory address reset signal is generated. Then, this signal is supplied to the vertical clipping circuit 12.

Further, the output of the delay circuit 102 is supplied to the vertical cutout circuit 12 as an H reset signal.

Next, details of the vertical cutout circuit 12 will be described with reference to FIG.

The vertical cutout circuit 12 sets the input data to 1 by the H reset signal from the horizontal cutout circuit 10.
The first selector 120, which selects and outputs each line, NT
A first field memory FM1 having a capacity of SC1 field and in which only odd lines are written, a second field memory FM2 in which only even lines are written, first
And the second write address counters 121, 123, the first
And the second read address counters 122 and 124, and the second selector 126 that selects the field memory output for each field and outputs it as an interlaced signal.

Next, the operation of the above circuit will be described with reference to FIG.

The input data is selected by the first selector 120 line by line, and the selected field data is stored in the first field memory FM.
It is supplied to the first and second field memories FM2.

First, the first write address counter 121
The vertical and horizontal addresses are reset by the frame address reset signal and the H reset signal to count the addresses. This frame address reset signal indicates the timing of the start of cutting in the vertical direction, and the first field memory FM1 starts the NTS from the line after the count starts.
Data of 240 lines for the odd field of C is written. That is, when the cut-out start line is set to 1 by the first write enable signal from the first write address counter 121, data of 240 odd-numbered lines 1 to 3 to 479 is written and then the write operation is stopped. .

On the other hand, data of 240 even-numbered lines from 2, 4 to 480 is similarly written in the second field memory FM2.

The reading from the first and second field memories is performed asynchronously with the writing. That is,
The first and second read address counters 122 and 124 have read control circuits 14 based on the NTSC external synchronization signal.
The vertical reset signal, the horizontal reset signal, and the read clock created in step 3 are supplied, and the vertical reset signal starts reading asynchronously with writing. The frequency of the read clock is 1/4 of the write clock.
Is 12 MHz, and the time axis of the read data is 4
It has been stretched twice. First and second field memory F
The data of the odd line and the even line are simultaneously read from M1 and FM2, but the second selector 126 selects the output of the first field memory FM1 for the odd field and the output of the second field memory FM2 for the even field. Output.

Therefore, an interlaced NTSC signal is obtained at the output of the second selector.

In this embodiment, the AD converter 2 to the DA converter 7 are shown as one system, but actually three RGB systems are required, and each line memory and field memory also has three systems.
System is required.

Further, as shown in FIG. 7, the line memory of the filter can be omitted by arranging the flicker removing filter 11 at the subsequent stage of the vertical cutting circuit 12. That is, the vertical selector circuit 12 has the second selector 1
26 is provided in parallel with the third selector 127, and two signals separated by one field can be obtained at the same time by operating both selectors in a complementary manner. Therefore, if these two signals are used, a vertical filter equivalent to that shown in FIG. 3 is constructed. can do.

FIG. 8 shows a block diagram of a video signal converting apparatus according to the second embodiment of the present invention. The difference from the first embodiment is that the matrix circuit 8 is arranged in front of the AD converter 2. The point is that after the luminance signal and the two color difference signals are formed from the RGB signal, the clipping process and the flicker removal are performed.

Therefore, although the capacity of the memory required for the cut-out processing is the same, the flicker can be removed only for the luminance signal, so the filter 11 can be used only for the luminance signal. Furthermore, when the band of the color signal is reduced in the encoder 9, the capacity of the field memory for the color difference signal of the vertical cutout circuit 12 can be slightly reduced.

[0051]

As described above, according to the present invention, the field memory used for the cutout display function can be made smaller in capacity than one computer screen, and the line memory used for the flicker removal filter is also small. It can be a capacity, and the circuit scale can be significantly reduced.

[Brief description of drawings]

FIG. 1 is a schematic diagram of a cutout display function in the present invention.

FIG. 2 is a schematic block diagram of a video signal converter according to an embodiment of the present invention.

FIG. 3 is a circuit diagram of a horizontal cutout circuit.

FIG. 4 is a time chart of FIG.

FIG. 5 is a circuit diagram of a vertical cutout circuit.

FIG. 6 is a time chart of FIG.

FIG. 7 is a diagram showing another embodiment of the vertical cutout circuit and the filter.

FIG. 8 is a schematic block diagram of a video signal converter according to another embodiment of the present invention.

FIG. 9 is a schematic block diagram of a conventional video signal conversion device.

[Explanation of reference numerals] 1 computer 10 horizontal cutout circuit LM1 line memory LM2 line memory 11 filter 12 vertical cutout circuit FM1 first field memory FM2 first field memory 13 write control circuit 14 read control circuit 15 cutout position setting circuit

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Isao Tsukano 2-18, Keihan Hondori, Moriguchi City, Osaka Sanyo Electric Co., Ltd.

Claims (6)

[Claims] 1. A video signal conversion device for converting a first video signal of a first standard into a second video signal of a second standard in which one screen has less data than the first standard. An image memory for storing data for one screen, and an area designating unit for designating an area corresponding to the size of one screen of the second video signal at an arbitrary position in one screen of the first video signal. A video signal conversion device comprising: a writing unit that writes data corresponding to the area designated by the area designating unit into the image memory; and a reading unit that reads data from the image memory according to the second standard. 2. The video signal conversion device according to claim 1, wherein a line memory is provided in the preceding stage of the image memory, in which data for one line of the second video signal is written at high speed and read at low speed. 3. The video signal conversion apparatus according to claim 1, wherein a vertical filter for removing line flicker is provided in a front stage or a rear stage of the image memory. 4. The vertical filter is provided for the second video signal 1
4. The video signal conversion device according to claim 3, further comprising at least one line memory for storing data for lines. 5. The non-interlaced writing to the image memory and the interlaced reading of the image memory.
The described video signal conversion device. 6. The video signal conversion device according to claim 3, wherein only the luminance signal is supplied to the vertical filter.