JPH06208452A - Common circuit for companding buffer - Google Patents

Abstract

PURPOSE:To share a companding buffer for multiplying/separating plural system data in respect to a common circuit for a data companding buffer. CONSTITUTION:In the common circuit provided with a compressing buffer 2 for executing equivalent data compression for data sent from plural system transmission lines and an expanding buffer 5 for executing equivalent data expansion for the data, a multiplying part 1 for multiplying data from the plural systems on the input side of the buffer 2, a separating part 3 for separating the data of the plural systems on the output side of the buffer 2, a multiplying part 4 for multiplying the data of the plural systems on the input side of the buffer 5 and a separating part 6 for separating the data on the output side of the buffer 5 are provided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus having frame conversion for continuous data and burst data, and more particularly to a common circuit for data compression and decompression buffers.

At present, in a device for transmitting and receiving data, it is essential to perform data compression and data decompression in order to improve the efficiency of a transmission line. In addition, it is also indispensable to reduce the scale of the circuit that performs data compression and data decompression.

[0003]

2. Description of the Related Art A compression buffer and a decompression buffer are required to compress and decompress data, respectively. Less than,
The circuits of the compression buffer and decompression buffer will be described with reference to FIG.

FIG. 9 is a diagram showing a circuit of a conventional embodiment, which handles, for example, data compression and data decompression.
This is a case where there are two system transmission paths. In the figure, 31 is the first
A compression buffer, 32 is a second compression buffer. Also 33
Is a first decompression buffer, and 34 is a second decompression buffer.

In the example of FIG. 9, when data is compressed / decompressed when there are two transmission lines of two systems, the first compression buffer 31, the second compression buffer 32, and the first expansion buffer are provided for each of the two systems. 33 and the second decompression buffer 34 are required.

In the circuit shown in FIG. 9, in the case of transmitting 2-system data which is continuous data, for one first transmission input data (TxIN1) among the transmission data of 2 systems, a transmission write clock (TxWCK). Write the TxIN1 to the first compression buffer 31 using
IN1 is read from the first compression buffer 31 as the first transmission output data (TxOUT1) which is burst data using the transmission read clock (TxRCK).

Regarding the other second transmission input data (TxIN2) which is continuous data, the TxWCK is used to write the TxIN2 to the second compression buffer 32, and the TxIN2 is used to the second compression buffer using the TxRCK.
The second transmission output data (Tx that is burst data from 32
It is read out as OUT2).

Similarly, when two-system data is received,
One of the two-system reception data that is burst data
For the reception input data (RxIN1), the first write buffer 33 is used by using the reception write clock (RxWCK).
The first read output data (RxOUT1), which is continuous data, is read from the first expansion buffer 33 using the receive read clock (RxRCK).

Further, another second received input data (RxIN
Regarding 2), the RxWCK is used to write to the second decompression buffer 34, and the RxRCK is used to read from the second decompression buffer 34 as the second reception output data (RxOUT2).

[0010]

Therefore, in the prior art, for example, two circuits having the same structure are provided.
There is a problem that the circuit scale is doubled.

It is an object of the present invention to reduce the circuit scale by sharing a compression / expansion buffer by multiplexing / separating data when, for example, compressing / expanding data on two transmission lines. And

[0012]

In order to achieve the above object, as shown in FIG. 1, it is equivalent to a compression buffer 2 which performs the same data compression on data sent from a plurality of transmission lines. A demultiplexer 1 provided with a decompression buffer 5 for decompressing data, which is connected to an input side of the compression buffer 2 and multiplexes data of the plurality of systems.
The demultiplexing unit 3 is connected to the output side of the compression buffer 2 to separate the data of the plurality of systems, and is connected to the input side of the decompression buffer 5 to multiplex the data of the plurality of systems. Multiplexer 4 and decompression buffer 5
A separating unit 6 is provided which is connected to the output side of and separates the data of the plurality of systems.

[0013]

In the present invention, as shown in FIGS. 1 to 3, when data is compressed, two systems of TxIN1 which are continuous data are used.
(a) and TxIN2 (b) are added to the multiplexing unit 1, multiplexed data (c) is created using TxWCK, and the TxWCK is added to the compression buffer 2 to generate compressed data (d) from the multiplexed data (c). ) Is created and the compressed data (d) is written in the compression buffer 2.

Then, the compressed data (d) written in the compression buffer 2 is read to the separation unit 3 by using TxRCK, and TxOUT1 (e which is burst data separated by the separation unit 3 by using the TxRCK. ) And T
Create and output xOUT2 (f).

In the case of decompressing data, two systems of RxIN1 (g) and RxIN2 (h), which are continuous data, are added to the multiplexing unit 4, and multiplexed data (i) multiplexed using RxWCK is added. That is, the RxWCK is added to the decompression buffer 5 to decompress the multiplexed data (i) to decompress the decompressed data (j).
And write the decompressed data (j) in the decompression buffer 5.

Then, the decompressed data (j) written in the decompression buffer 5 is read out to the separation unit 6 by using RxRCK, and RxOUT1 (k) which is burst data demultiplexed by the separation unit 6 by using the RxRCK. And Rx
Create and output OUT2 (l).

Therefore, the circuits of the compression buffer and the expansion buffer of the two transmission lines can be made common, and the circuit scale can be reduced.

[0018]

Embodiments of the present invention will be described below with reference to FIGS. 4 and 5-8. 4A and 4B are diagrams showing a circuit of a compression buffer and a decompression buffer according to an embodiment of the present invention. FIG. 4A shows a compression buffer part and FIG. 4B shows a decompression buffer part.

In FIG. 4, 11, 12, 14, 16 to 20 and 2
1,22,24,26 to 30 are flip-flop circuits (FF). In addition, 13 and 23 are 2-1 selectors that select one signal from two signals, and 15 is a compression buffer,
25 is a decompression buffer.

5 to 8 are diagrams showing the timing of the present invention, FIG. 5 is a diagram showing the timing of the compression buffer of the embodiment of the present invention (No. 1), and FIG. 6 is the present invention. FIG. 8 is a diagram (No. 2) showing the timing of the compression buffer of the embodiment.

FIG. 7 is a diagram (No. 1) showing the timing of the decompression buffer according to the embodiment of the present invention, and FIG. 8 is a diagram (No. 2) showing the timing of the decompression buffer according to the embodiment of the present invention. Is.

Further, (a1) to (a16) show data of each part of the compression buffer, and (b1) to (b16) show data of each part of the decompression buffer. Figure 4 shows the compression buffer.
This will be described with reference to (A), FIG. 5 and FIG.

Two TxIN1 (a1) and TxIN2 (a2)
For example, continuous data having a speed of 0.4 Kbit / sec (bps) is continuously hit with continuous data (a4) having the same speed by striking each FF11 and FF12 with 0.4KTWCK (a3) which is a transmission clock of the same speed Create data (a5).

In the 2-1 selector 13, the 0.4 KT
Continuous data (a6) that was multiplexed by selecting two alternatives with WCK (a3)
, And 0.8KTW with 0.8Kbps speed in FF14
CK (a7) is tapped again to create continuous data (a8) of the same speed, and the data (a8) is written in the compression buffer 15 using 0.8KTWCK (a7).

The compression buffer has a speed of 15 to 8 Kbps
Burst data of the same speed (a1
0) is read and the burst data (a10) is re-beaten by 8K TRCK (a9) in the FF16 to create burst data (a11) of the same speed.

Burst data (a13) and (a14) of the same speed are separated from FF17 and FF18 by using the rising and falling edges of 4KTRCK (a12) having a speed of 4 Kbps. Then, in FF19 and FF20, it is tapped again with 4K TRCK (a12), and TxOUT1 (a1) which is burst data of the same speed.
5) and TxOUT2 (a16) are output.

Next, the decompression buffer is shown in FIG.
And FIG. 7 and FIG. Two RxIN1 (b1) and RxIN2 (b2), eg 4Kbp
Burst data having a speed of s (the same speed as the above TxIN1 (a1) and TxIN2 (a2)) is sent to FF21 and F respectively.
4KRWCK which is the same speed reception clock in F22
Hit at (b3) to create burst data (b4) and burst data (b5) with the same speed.

In the 2-1 selector 23, the 4KRW
The burst data (b
6), and 8KRWCK (b at 8Kbps speed in FF24
The burst data (b8) having the same speed is created by tapping in step 7), and the data (b8) is written in the decompression buffer 25 using 8KRWCK (b7).

From the expansion buffer 25, 0.8KRRCK (b9) having a speed of 0.8 Kbps is used to obtain continuous data (b1
0) is read out, and the continuous data (b10) is tapped again with 0.8KRRCK (b9) in the FF26, and continuous data (b
11) Create

0.4KRRCK (b1 with a speed of 0.4Kbps
2) FF27 and FF28 using the rising and falling edges
Is separated into continuous data (b13) and (b14) with the same speed. Then, in FF29 and FF30, it is tapped again with 0.4KRRCK (b12), and RxOUT1 (b1) which is continuous data of the same speed.
5) and RxOUT2 (b16) are output.

[0031]

As is apparent from the above description, according to the present invention, it is possible to reduce the circuit scale of the related art when implementing compression / expansion of data of two systems. .

[Brief description of drawings]

FIG. 1 is a diagram showing a circuit of a principle configuration of the present invention.

FIG. 2 is a diagram showing the principle of data compression timing in the present invention.

FIG. 3 is a diagram showing the principle of data expansion timing in the present invention.

FIG. 4 is a diagram showing circuits of a compression buffer and an expansion buffer according to an embodiment of the present invention.

FIG. 5 is a diagram (No. 1) showing the timing of the compression buffer according to the embodiment of the present invention.

FIG. 6 is a diagram (No. 2) showing the timing of the compression buffer according to the embodiment of the present invention.

FIG. 7 is a diagram (No. 1) showing the timing of the decompression buffer according to the embodiment of the present invention.

FIG. 8 is a diagram (No. 2) showing the timing of the decompression buffer according to the embodiment of the present invention.

FIG. 9 is a diagram showing a circuit of a conventional example.

[Explanation of symbols]

 1 and 4 are multiplexers 3, 6 are demultiplexers 2 are compression buffers 5 are decompression buffers

Claims (1)

[Claims] 1. A compression buffer (2) for performing equivalent data compression on data sent from a plurality of transmission lines.
In a circuit equipped with a decompression buffer (5) for decompressing data equivalent to, a multiplexing unit (1) connected to the input side of the compression buffer (2) for multiplexing the data of the plurality of systems, and the compression unit The separation unit (3) is connected to the output side of the buffer (2) and separates the data of the multiple systems, and is connected to the input side of the decompression buffer (5) to store the data of the multiple systems. A compression / expansion unit, which is provided with a multiplexing unit (4) for performing multiplexing and a demultiplexing unit (6) connected to the output side of the decompression buffer (5) for demultiplexing the data of the plurality of systems. Common buffer circuit.