JPH0756962B2 - Data communication system - Google Patents

Description

The present invention relates to a data communication system.

[Conventional technology]

An example of frame synchronous multiplexing and demultiplexing in a conventional data communication system will be described with reference to FIGS. 4, 5, and 6. In FIG. 4, the device (A) 101 is connected to the device (B) 103 via the communication line 102. Device 101
Inputs serial data of each channel of channel A, channel B and channel C, frame pulse and clock. Channel A, channel B, channel C inputs are devices
The signals are input to the serial-parallel conversion circuits 111, 112 and 113 in 101, respectively, and the frame pulse and the clock are input to the timing generation circuit 114. Serial-parallel conversion circuit 11
The 8-bit parallel signals output from 1,112,113 are temporarily stored in buffer memories 115,116,117 respectively, read at required timing, multiplexed by a multiplexing circuit 118, converted to serial data by a parallel-serial conversion circuit 119, and then transferred to the communication line 102. Sent out. These cereals
Parallel conversion circuits 111, 112, 113, buffer memories 115, 11
6,117, multiplex circuit 118, parallel-serial conversion circuit 119
All operate according to the output timing of the timing generation circuit 114.

On the other hand, in the device 103, the clock component is extracted from the multiplexed data that has arrived from the communication line 102 by the clock extraction circuit 130 and is input to the timing generation circuit 131, and the data that has become 8-bit parallel by the serial-parallel conversion circuit 132 is separated by the separation circuit. At 113, channels A, B, and C are separated and temporarily stored in buffer memories 134, 135, and 136. Further, the frame pattern is input to the frame pulse extraction circuit 137 and the frame pattern in the data is extracted. As a result, a frame pulse is generated and input to the timing generation circuit 131. Each output of the buffer memories 134, 135, 136 is converted into serial data of each channel by the parallel-serial conversion circuits 138, 139, 140 and output. These serial-parallel conversion circuit 132, separation circuit 113, buffer memories 134, 135, 136, parallel-serial conversion circuit 13
All of 8,139,140 operate according to the output timing of the timing generation circuit 131.

The flow of the above series of operations is shown in the time chart of FIG. 5, and taking the channel A as an example, the time chart of FIG. 6 shows the timing of writing and reading to and from the buffer memory. . As is apparent from FIG. 6, in the conventional multiplexing method, the frame pattern F on the multiplexed communication line is generated in phase synchronization with the frame pulse on the transmitting side, and therefore the serial data of each channel does not have 8 bits. Multiplexing in stages is not possible, 1
Temporarily stores all the data of each channel in the frame,
In the next frame, this temporary storage data was sequentially multiplexed and output to the communication circuit. Similarly, at the time of separation, frame synchronization is taken and a serial signal is output from the next frame.

[Problems to be Solved by the Invention]

In the above-mentioned conventional system, a time for one frame is required for multiplexing and demultiplexing, so that a delay of a total of two frames occurs in one-way communication. As a result, for example, in the case of voice data, two lines are
When the 4-wire conversion circuit is provided, the wraparound of the voice due to the mismatch of the 2-wire to 4-wire conversion circuit becomes an echo due to the delay, which causes a problem that the communication quality is deteriorated. In addition, a means for temporarily storing data for one frame is required for each channel when multiplexing and demultiplexing, and the higher the channel speed and the larger the data amount, the larger the circuit scale of the temporary storage means. I will end up.

[Means for Solving the Problems]

The present invention relates to a data communication system in which serial data of a plurality of channels are multiplexed to form multiplexed serial data, and data communication is performed between opposing devices via a communication line while frame synchronization is performed by a frame pulse on the data transmission side. In synchronization with the delayed frame pulse from the first means, the first means delays and generates the frame pulse in order to define the output timing of the multiplexed serial data to the communication line on the transmission side. A second means for outputting the multiplexed serial data, and delaying the frame pulse extracted from the frame pattern on the communication line in order to regulate the output timing of the data of each channel after separation to the separation receiving side. And the respective channels after separation in synchronization with the frame pulse from the third means. And a fourth means for outputting the data.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

Referring to FIG. 1 showing the configuration of an embodiment of the present invention, a device (A) 1 is connected to a device (B) 3 via a communication line 2. The device 1 has serial data input for each channel of channel A, channel B, and channel C, and each data input is connected to serial-parallel conversion circuits 11, 12, 13 and converted into 8-bit parallel data, Input to buffer memories 14, 15 and 16. Buffer memory 14,15,16
Are multiplexed by the multiplexing circuit 17, converted into serial data by the paramel-serial conversion circuit 18, and output to the communication line 2.

Further, the device 3 is a clock extraction circuit connected to the communication line 2.
A clock is extracted from the serial data, the data is input to the serial-parallel conversion circuit 31, the serial data is converted to 8-bit parallel data, and the data is input to the separation circuit 32 and the frame pulse extraction circuit 33. The 8-bit parallel data of each channel separated by the separation circuit 32 is held in the buffer memories 34, 35, 36, respectively. The outputs of the buffer memories 34, 35, 36 are converted into serial data of each channel by the parallel-serial conversion circuits 37, 38, 39 and output to the outputs of channel A, channel B, channel C, respectively.

The apparatus 1 has a timing generation circuit (A) 19 and a timing generation circuit (B) 20. The timing generation circuit 19 inputs a clock input and a transmission frame pulse, and outputs the output from the serial-parallel conversion circuit 11 , 12,13,
It is input to the buffer memories 14, 15, 16 and the first frame pulse generation circuit 21. Further, the timing generation circuit 20 inputs the clock and the output of the first frame pulse generation circuit 21, and inputs the output to the multiplexing circuit 17 and the parallel-serial conversion circuit 18. The device 3 has a timing generation circuit (C) 40 and a timing generation circuit (D) 41, and the timing generation circuit 40 receives the clock output of the clock extraction circuit 30 and the output of the frame pulse extraction circuit 33 as inputs. The output of the timing generation circuit 40 is a serial-parallel conversion circuit 31, a separation circuit 32, buffer memories 34, 35, 36,
It is input to the second frame pulse generation circuit 42. Also,
The timing generation circuit 41 receives the clock output of the clock extraction circuit 30 and the output of the second frame pulse generation circuit 42 as inputs. The output of the timing generation circuit 41 is a buffer memory
It is input to 34, 35, 36 and parallel-serial conversion circuits 37, 38, 39.

Next, the detailed operation will be described with reference to FIGS. 1, 2, and 3. FIG. 2 is a diagram for explaining the frame synchronization method in the same embodiment, and FIG. 3 is a time chart showing the timing of writing and reading to and from the buffer memory, taking the channel A in the same embodiment as an example.

In FIG. 2, the serial data input of each channel of channel A, channel B, and channel C is divided into blocks of 1 byte (8 bits) and numbered as A0 to A3, B0 to B1, C0 to C7, respectively. deep. The input of each channel is converted into parallel data by the serial-parallel conversion circuits 11, 12 and 13 every time 8 bits are prepared, and temporarily stored in the buffer memories 14, 15 and 16, respectively. The operation up to this point operates at the timing by the timing generation circuit 19 defined by the transmission frame pulse and the clock. The transmission frame pulse is the position where the data of each channel is aligned by 1 byte by the first frame pulse generation circuit 21, that is, the channel B is aligned at 1 byte in the example of FIG. Together, they are delayed by half a frame and then output. By the output of the timing generation circuit 20 synchronized with this pulse, the contents of the buffer memories 14, 15, 16 are read,
After being multiplexed by the multiplexing circuit 17, the parallel-serial conversion circuit 18 sends it as serial data to the communication line 2 at a timing delayed by a half frame from the frame pulse for transmission. The timing of writing and reading of the buffer memories 14, 15, 16 is as shown in FIG. Device 3
Then, the multiplexed serial data that has arrived from the communication line 2 is input to the clock extraction circuit 30 and the clock component in the data is extracted. The device 3 is operated by this clock.
Further, the data is input to the serial-parallel conversion circuit 31, where it is converted into 8-bit parallel data, and the separation circuit
32 and the frame pulse extraction circuit 33. The frame pulse extraction circuit 33 finds a frame pattern in the data and generates a reception frame pulse at that timing. The 8-bit parallel data of each channel separated by the separation circuit 32 is held by the buffer memories 34, 35, 36 at the timing generated by the timing generation circuit 41 to which the clock and the reception frame pulse are input. The reception frame pulse is input to the second frame pulse generation circuit 42, where it is delayed by the minimum time (half frame in FIG. 2) at which parallel data of each channel can be simultaneously converted into serial data. Converted to frame pulse. The converted frame pulse is input to the timing generation circuit 41. The timing generation circuit 41 generates timing synchronized with the output of the second frame pulse generation circuit 42, and the contents of the buffer memories 34, 35, 36 are read at this timing, and the parallel-serial conversion circuit 37, It is converted into serial data of each channel by 38 and 39 and output. The timing of writing and reading of the buffer memories 34, 35, 36 is as shown in FIG.

When such a frame synchronization system is used, there is a delay of about one frame between the serial data input of each channel to the device 1 and the serial data output of each channel from the device 3, which is half that of the conventional system. Will be delayed.

Note that transmission from the device 3 to the device 1 can be realized by adopting the same circuit configuration, and bidirectional communication becomes possible.

〔The invention's effect〕

As described above, according to the present invention, when the data is multiplexed and demultiplexed, the frame pulse is provided on the input side and the output side by shifting the phase by the time required for the data multiplexing and demultiplexing. Since the delay at the time of synchronization can be reduced, not only the transmission efficiency can be improved, but also the echo in the case of voice data can be alleviated. Further, since the capacity of the buffer memory for temporarily storing data for frame synchronization is not required for one frame, the circuit scale can be reduced.

[Brief description of drawings]

FIGS. 1, 2 and 3 are views showing an embodiment of the present invention, and FIGS. 4, 5, and 6 are views showing conventional examples. 1 ... Device (A), 2 ... Communication line, 3 ... Device (B), 11, 12, 13 ... Serial-parallel conversion circuit, 1
4,15,16 …… Buffer memory, 17 …… Multiplex circuit, 18 ……
Parallel-serial conversion circuit, 19 ... Timing generation circuit (A), 20 ... Timing generation circuit (B), 21 ... First frame pulse generation circuit, 30 ... Clock extraction circuit, 31 ... Serial-parallel Conversion circuit, 32 ... Separation circuit, 33 ... Frame pulse extraction circuit, 34, 35, 36 ... Buffer memory, 37, 38, 39 ... Parallel-serial conversion circuit, 40 ... Timing generation circuit (C), 41 ... Timing generation circuit (D), 42 ... Second frame pulse generation circuit.

Claims (1)

[Claims] 1. A data communication system in which serial data of a plurality of channels are multiplexed to form multiplexed serial data, and data communication is performed between opposite devices via a communication line while frame synchronization is performed by a frame pulse on the data transmission side. First means for delaying and generating the frame pulse in order to define the output timing of the multiplexed serial data to the communication line on the multiplexing transmission side, and synchronization with the delayed frame pulse from the first means And a second means for outputting the multiplexed serial data, and a frame pulse extracted from the frame pattern on the communication line for defining the output timing of the data of each channel after separation on the separation receiving side. Delayed and generated third
And a fourth means for outputting the separated data of each channel in synchronization with the frame pulse from the third means.