JPH059868B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a mute circuit, for example, a VTR.
This system is designed to attenuate the audio output when the limit exceeds a predetermined number during playback after PCM playback using a digital audio disk player or when the number of limits exceeds a predetermined number during playback.

Generally, if a PCM player cannot reproduce correct data due to noise in the data transmission path,
Pulse-like residual sound may be output. Even if the noise generated in the analog signal transmission path is at a small level, if it enters the PCM data stream, it will be affected at that location (data MSB or synchronization pulse).
may be reproduced as excessive noise. Therefore, an error correction code or an error detection code is sometimes combined with the PCM data string to reproduce correct data or take measures against noise such as holding previous values. Furthermore, when using a PCM player, large dropouts of data often occur due to scratches or the like in the recording medium. If such excessive noise is input, even if there is a data correction code or an error detection code as described above, if the correction capability is exceeded, it is difficult to expect correct reproduction.

For this purpose, the number of errors within a certain period, that is, the error rate or the number of missing synchronization signals, etc., is detected, and if the same number exceeds a certain number, it can be set to zero in the digital signal or zero in the analog signal. Therefore, methods are being taken to prevent the reproduction output of abnormal persons caused by the same situation. However, in this case, if the error rate exceeds a certain level, the average value interpolation, etc. will be performed many times in the previous value holding area, but even though the signal can be reproduced, there is a problem because the reproduced sound will completely disappear during the above period. It was hot.

Furthermore, there was the inconvenience that upon recovery from the mute period, the reproduction sound level suddenly returned to the normal reproduction sound level.

The present invention was invented in view of the above-mentioned phenomenon, and it counts the number of error signals, and when the number exceeds a predetermined number, starts muting that provides attenuation according to the number of error signals, and It is an object of the present invention to provide a mutating circuit which releases the above-mentioned muting state when the number of error signals becomes less than a predetermined number for canceling muting after a predetermined period of time after the number of error signals becomes less than a predetermined number. .

The present invention counts the number of error signals, sets it as a muting state when it reaches a certain number, controls the muting condition based on the number, and when the number of error signals becomes less than a certain number, a predetermined state is set. The present invention is characterized in that the muting state is canceled when the number of error signals becomes less than a certain number after a certain period of time.

The present invention will be explained below with reference to an embodiment of a compact disk format playback device. FIG. 1 is a block diagram showing the overall configuration of a PCM reproducing device including a muting circuit according to the present invention.

In FIG. 1, the digital reproduction output signal 11
takes in data by a data synchronization circuit 1 and obtains an output 12. Input the output 12 to the demodulation circuit 2,
The signal is demodulated and errors are detected by the error detection circuit 3.

Furthermore, a synchronization signal extraction circuit extracts a synchronization signal from the output 12, and a control circuit 9 generates a data synchronization signal.

The data in which an error has been detected is deinterleaved by the deinterleave circuit 4. The deinterleaved data undergoes predetermined error correction processing by the error correction circuit 5.

The error signal 13 of the error detection circuit 3 is counted by the error control circuit 10 to obtain the number of errors within a predetermined period,
A signal 14 is generated according to the number of errors. The output control circuit 6 controls the data subjected to error correction processing using the output 14 of the error control circuit 10, and performs processing according to the number of errors.

The output-controlled data is converted into an analog signal by a digital-to-analog conversion circuit 7, and an analog reproduction signal 15 is obtained.

Here, the error control circuit 10 and the output control circuit 6
This will be explained in more detail with reference to FIG.

The error number counting circuit 17 counts the error signals 13 and determines the counting period using the counting control signal 25.

The counting circuit 17 outputs a count value 24, a mute start signal 29, and a mute release control signal 13-2 every period determined by the counting control signal 25. Here, for example, the counting period length is 128 frames, and the mute start signal 9 is the number of error signals.
It is output when the number of frames is 64 or more, and the mute cancellation signal 28 is output when the number of error signals within the period becomes 4 or less.

Next, the counting circuit 18 counts the counting signal 22 and generates a counting control signal 25. Here, for example, the count signal 22 is a frame synchronization signal, and the count value of the counting circuit 18 is set to 128, so that the count period length is set to 128 frame periods.

During this 128-frame period, the interleaving interval of the compact disk format is approximately
It is 108 frames, and the value is close to that.
Furthermore, an error rate of 64 frames at the start of Mute is about 40 to 50 frames, which cannot be corrected due to continuous errors and cannot be averaged by interpolating the previous and subsequent data.
frame, and was set to a value close to the value at which the above interpolation becomes a problem. Therefore, these values must be set to appropriate values according to the format.

Furthermore, a duration of 1 second as a release condition was set as the minimum time during which the start and return of the mute cannot be repeated. Further, the number of errors 4 in the recovery condition is a frame error rate of 3×10 ⁻² , which is close to the upper limit of the normally predicted disk error rate and is a value that allows sufficient error correction.

Next, the attenuation amount control signal 14-1 is generated from the count output 24 by the decoder 16.

Here, for example, the attenuation amount control signal 14-1 is set so that the attenuation amount becomes the following values.

Based on the case where the error count value is 64, first 64
-18d _B for 72 pieces, then -21d _B for 72 pieces,
-24d _B for 80 pieces, -27d _B for 88 pieces,
-30d _B for 96 pieces, -33d _B for 104 pieces,
−38d _B for 112 pieces and −38d B for 120 pieces.
39d _B and in case of 128 or all data errors -
Make it so that ∞d _B. By doing this, 80
~62~ when listening at a volume of ~90d _B SPL
The output is attenuated from 72d _B SPL to 41 to 51d _B SPL.

This is because the abnormal sound output is lowered and the volume is audible, so the influence of the abnormal sound can be reduced and the content of the reproduced signal can be known.

Therefore, in the output control circuit 6, the input data 27
is attenuated by the attenuation amount control signal 14-1 during the period of the attenuation control signal 14-2 to obtain an output 21.

Here, the control circuit 19 generates the attenuation control signal 14-2 based on the mute start signal 29, the mute return signal 28, and the mute duration signal 26.

Here, for example, the mute start signal 29 generates a mute start signal when the number of error frames is 64 or more out of 128 frames, and when the number of error frames is 4 or less after a predetermined period of time, for example 1 second, after the generation of the mute start signal. If you become tired, release Miyuto and restore it.

The mute period generating circuit 20 starts counting pulses in response to the mute start signal 29, counts a predetermined number of pulses, and generates a duration signal 26.

Here, the counting pulse is the counting control signal 25
to obtain a signal 26 with a duration of about 1 second.

According to the present invention, when the number of data errors increases and the number within a predetermined period exceeds a certain value, the output signal amplitude can be attenuated in accordance with the number of errors, so that it is possible to attenuate the amplitude of the output signal according to the number of errors. The abnormal sound level can be lowered, and the signal content during that period can also be heard.

Further, when an error is greater than a predetermined value or when all data are erroneous, the attenuator is set to -∞, so the reproduction output becomes zero when the power is turned on or when there is no signal, making it possible to completely prevent abnormal sound from being output.

[Brief explanation of drawings]

Figure 1 shows a PCM including the mute circuit of the present invention.
A block diagram showing one embodiment of the reproducing circuit, FIG. 2 is a block diagram of a configuration of a mute circuit. 17...Error number counting circuit, 6...Output control circuit.

Claims (1)

[Claims] 1 Convert analog signal to digital signal,
In a signal recording and reproducing device that records on a recording medium, reads a reproduced digital signal from the recorded recording medium, performs predetermined signal processing such as error detection and correction, and then converts it into an analog signal and outputs it. , comprising a first means for detecting an error rate in a reproduced digital signal and a second means for detecting whether the error rate is larger than at least two types of error rates, the second means 1. A mute circuit characterized in that the attenuation amount of an attenuator that receives a reproduced demodulated signal as input is controlled to at least three types of values including 0 and -∞dB including a predetermined attenuation amount by the output of the mute circuit.