JPS6329349B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a mutating circuit, e.g.
In a PCM player using a VTR as a recording medium, the audio output is muted when the horizontal synchronization signal is continuously lost during playback.

Generally, if a PCM player cannot reproduce correct data due to noise in the data transmission path,
Pulse noise may be output. Even if the noise generated in the analog signal transmission path is at a small level, if it enters the PCM data stream, it will be affected at that location (data MSB or synchronization pulse).
may be reproduced as excessive noise. Therefore, an error correction code or a cyclic code (CRC) is sometimes combined with the PCM data string to reproduce correct data and take measures against noise such as holding previous values. By the way, when using a consumer PCM player that uses a home VTR as a recording medium,
Because VTRs do not have the same performance as industrial VTRs, large data dropouts often occur.
In addition, since the users are ordinary people at home, if signals other than data are input by incorrect usage such as playing a tape containing image signals,
This results in excessive noise. When excessive noise is input in this way, the data correction code and
Even if there is a CRC, it is difficult to expect correct reproduction if the correction capability is exceeded.

Furthermore, when data becomes discontinuous due to missing horizontal synchronizing signals, etc., it is impossible to prevent abnormal noises caused by discontinuous data and incorrect corrections caused by it. noticeable.

The present invention was invented in view of the above-mentioned phenomenon, and it counts the number of missing synchronization signals and starts muting when the number of missing synchronization signals exceeds a predetermined number in a row to prevent noise output. It is an object of the present invention to provide a muting circuit which releases the above-mentioned muting state after a predetermined period of time after there are no more consecutive omissions.

The present invention counts the number of consecutive missing synchronization signals, sets it as a muting state when it reaches a certain number, and cancels the muting state after a predetermined period of time after the continuous missing synchronization signals stop. Characterized by what has been done.

The present invention will be explained below with reference to embodiments shown in the drawings. FIG. 1 includes a muting circuit of the present invention.
A block diagram showing the overall configuration of a PCM recording and playback machine.
A digital recording and playback system for audio signals is constructed using a VTR.

In FIG. 1, an analog signal a input from an input terminal 1 is sampled and held by a sampling hold circuit 2 at a predetermined sampling period. Here, the sampling period is, for example, 22.7
Microseconds are used. The output b from the sampling hold circuit 2 is converted into a digital signal c by the A/D converter 3 at the same period as the above-mentioned sampling period. The digital signal c is, for example,
This is a 16-bit offset binary code. The digital signal c is recorded in the recording system memory 4 at the same period as the above-mentioned sampling period. Recording and reproducing operations in the recording system memory 4 are controlled by a control signal d from the memory control circuit 5. The content recorded in the recording system memory 4 is read out at a short cycle and at a predetermined timing, which is different from the cycle at the time of recording, so that the content is time-compressed and converted into a video signal waveform, which will be described later. The output signal e from the recording system memory 4 is input to the error correction data/error detection data generation circuit 6 and output as a digital recording signal f. A video signal generation circuit 8 adds the signal g to obtain a video recording signal h. This video recording signal h is input to the VTR 9 and recorded.
The above is the configuration and operation of the recording system R.

Next, the configuration and operation of the reproduction system P will be described.
A video reproduction signal i from the VTR 9 is separated into a digital signal j and a synchronization signal k by a signal extraction circuit 10 and output. The digital signal j is input to an error detection circuit 11, where it is checked for the presence or absence of an error. The synchronizing signal k is input to the recording control circuit 12 and output as a recording control signal l to control the recording operation of the reproducing memory 13. The output m of the error detection circuit 11 is sequentially recorded in the reproduction memory 13 together with the digital signal j. This recording signal is read out from the reproduction system memory 13 by a reproduction control signal n generated by the reproduction control circuit 14, and a digital signal q is output. Here, time expansion and wow/flutter absorption are performed by the reproduction control signal n. The read digital signal q enters the error signal processing circuit 15, where erroneous data is corrected. This correction process is carried out by the reproduction control circuit 1.
It is controlled by the processing control signal p output from 4. The output 8 from the error signal processing circuit 15 is D/
It is converted into an analog output signal r by the A converter 16 and output from the output terminal 17.

Here, the muting circuit 18 has a function of monitoring the number of error outputs s of the error detection circuit 11 and the number of consecutive omissions of the horizontal synchronization signal output t of the recording control circuit 12, and monitors the number of error outputs s or the number of consecutive omissions of the horizontal synchronization signal output t of the recording control circuit 12. When the number of consecutive omissions reaches a predetermined value within a certain period of time, a muting signal v is outputted from the terminal 19, and the analog signal r is brought into a muting state by grounding or other means (not shown). The muting state is canceled after a predetermined period of time after the error output s and/or the horizontal synchronization signal are no longer continuously missing (after returning to the normal state).

Next, the muting circuit will be explained in more detail using the block diagram of one embodiment shown in FIG. 2 and the time chart shown in FIG. In FIG. 2, t, s, u ₁ , u ₂ and v are the horizontal synchronizing signal output t, the error output s of the error detection circuit 11, the first clock pulse u ₁ , the second clock pulse u ₂ and the muting signal in FIG. These are signal lines for each output signal v.

In the figure, 18a is the first clock pulse u ₁
When the horizontal synchronizing signal t is normally obtained, the above-mentioned count is cleared each time the horizontal synchronizing signal t is successfully obtained, and when a predetermined number of horizontal synchronizing signals t are missing consecutively, It is set to output an output w. That is, the repetition frequency of the clock pulse _u1 , which is the input of the N-ary counter 18, is
_o , and the repetition frequency of the horizontal synchronization signal t _{is H}
If the number of consecutive missing horizontal synchronizing signals t to which muting is applied is 4, then the N-ary counter 18a
is set to _3o / _H <N< _4o / _H . Also 1
8b has the horizontal synchronizing signal t as a set input, and the N
A set-reset type flip-flop (hereinafter simply referred to as
RS-FF).

The operations of the N-ary counter 18a and the RS-FF 18b will be explained using FIG.

In FIG. 3, t is a waveform diagram showing the output status of the horizontal synchronization signal, and as shown in _t1 in the figure, in the interval where the horizontal synchronization signal t is not missing, the signal t causes the N-ary counter 18a to It is always cleared (reset) and no output w is produced.

Next, even in the section where one signal t is missing, as shown at _t2 in the same figure, it is cleared by the next signal and no count output w is produced. Similarly, in the sections t ₃ and t ₄ where two and three signals t are missing, the N-ary counter 18a is cleared before counting N clock pulses u ₁ , so no count output w is output. Next, when four signals t are missing as shown in section _t5 , the reset signal t does not arrive until the predetermined set value N is counted, so the N-ary counter 18a receives a clock pulse.
When N pieces of u ₁ are counted, output w is output. By the count output w of this N-ary counter 18a, RS-FF18b
is reset, and here RS-FF18b is set by the next horizontal synchronization signal t, so RS-FF18b is reset.
The output x of the FF 18b is as shown in FIG.

Next, the M-ary counter 18c, which is the next stage configuration, and
RS-FF18d will be explained.

The M-ary counter 18c is used to set the muting release time after the normal horizontal synchronization signal is recovered, and is set to, for example, one second. That is, if _n is the repetition frequency of the clock pulse _u2 input to the M-ary counter 18c, the M-ary counter 18c is set to M= _n . Returning to Figure 3, if four horizontal synchronizing signals are missing in section _t5 as described above, the output x of RS-FF18b
The RS-FF 18d is reset by this. Therefore, if four or more consecutive horizontal synchronization signals are missing,
The RS-FF18d output y becomes "0", and the count output from the M-ary counter 18c after one second causes the RS-
The FF18d output becomes "1". This "0" section is the muting section.

Here, for example, if four or more horizontal synchronization signals are missing, muting is applied, and in order to cancel the muting one second after four or more are missing, the N-ary counter 18
The repetition frequency of clock pulse u ₁ of a is _o =
2.6MHz, clock pulse of M-ary counter 18c
Let the repetition frequency _n of u ₂ be 59.9Hz, N=756, and M=60. In this case, there is a relationship _o = _168H , which corresponds to 4.5H when N=756.

Therefore, if four or more horizontal synchronizing signals are missing, the N-ary counter 18a is not cleared and the N-ary counter output is output. However, as described above, if there are three or less clock pulses, the clock pulse _o is cleared by the horizontal synchronizing signal before counting 756 pulses, and the N-ary counter output is not output.

Furthermore, when 60 clock pulses u ₂ are counted, after the M-ary counter 18c starts counting, the output of the M-ary counter 18c is output and the RS
-The time it takes to switch the output y of the FF 18d is approximately 1 second, as shown by T ₀ in FIG. In this way, if there are three or less consecutive horizontal synchronization signal losses, no muting will be applied, but if four or more consecutive horizontal synchronization signals are missing, muting will be applied. It will be canceled one second after.

In addition, in parallel with the horizontal synchronization signal monitoring system, a CRC signal monitoring device 1 of the error detection circuit 11 is installed.
8e is provided, and both outputs are NAND gates 18
has been entered. This monitoring device 18e is used to perform muting when there are many data errors, and calculates the CRC muting output z obtained by counting the data errors, that is, the CRC signal s.
The signal is sent to the NAND gate 18 to generate a muting signal v. Here, the CRC muting signal z is in a muting state during the "0" period, similar to the mutating signal y related to the horizontal synchronization signal. Both signals are added by the NAND gate 18, and are muted when either the muting signal y or the CRC muting signal z related to the horizontal synchronization signal satisfies a predetermined condition.

In the above explanation, the value of the N-ary counter 18a is 756 and the value of the M-ary counter 18c is 60, but by setting these values appropriately, the number of consecutive missing horizontal synchronization signals subjected to muting and You can decide the length of time for canceling mutating.

As explained above, according to the present invention, by blocking the output signal when the synchronization signal is continuously lost, it is possible to prevent the generation of abnormal sounds or the output of erroneous data due to correction errors, and furthermore, the output By confirming that there are no errors within a predetermined time before returning from the signal blocking state, it is possible to smoothly return to the normal reproduction state.

[Brief explanation of the drawing]

FIG. 1 includes a muting circuit of the present invention.
A block diagram of an embodiment of a PCM signal recording and reproducing device,
FIG. 2 is a block diagram of an embodiment of the muting circuit according to the present invention, and FIG. 3 is a time chart of the muting circuit of FIG. 10: Signal extraction circuit, 11: Error detection circuit, 1
2: recording control circuit, 18: mutating circuit,
18a: N-ary counter, 18b: RS-FF, 18
c: M-ary counter, 18d: RS-FF.

Claims (1)

[Scope of Claims] 1. A PCM signal reproducing device having means for detecting a synchronization signal loss in a PCM signal including a synchronization signal and muting the level of a PCM signal reproduction output, wherein the means detects a synchronization loss within a predetermined time. A muting circuit, characterized in that it is a control circuit that mutes a PCM signal reproduction output when detected, and cancels the muting only after detecting that there is no synchronization loss for a period longer than the predetermined time. 2. In a PCM signal reproducing device having a means for detecting a synchronization signal loss of a PCM signal including a synchronization signal and muting the level of the PCM signal reproduction output, muting the PCM signal reproduction output when a synchronization loss is detected within a predetermined time. a first control circuit that cancels the mutating only after detecting that there is no loss of synchronization for a period longer than the predetermined time; and a first control circuit that counts the number of errors detected in the PCM signal and performs muting according to the number of errors. 1. A muting circuit, comprising: two control circuits, which performs muting control on a PCM signal reproduction output according to an output of the first control circuit or an output of the second control circuit.