JPH0580977A - Data processor - Google Patents

Abstract

PURPOSE:To reduce the load of a host device and to improve the sort processing performance by merging plural partial sort strings in an arithmetic processor. CONSTITUTION:A data base arithmetic processor 16 applies a multiprocessor constitution. The data input/output processing is carried out between the processor 16 and a magnetic disk device 17 by an engine interface processor EIP 161. A hardware sorter control processor ECAM 164 perform the sort processing with use of the hardware arithmetic circuits of a parallel sorting module PSOM 165 and a parallel relation algebraical arithmetic module PRAM 166. Then an engine control processor ECP 162 performs the n-way merge processing to merge the total control with plural partial sort strings. Furthermore the external sort input processing and the sort processing as well as the n-way merge processing and the output processing are carried out in parallel with each other.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing device having an arithmetic processing device for executing arithmetic processing such as sorting on file data to be operated in response to a request from a host device.

[0002]

2. Description of the Related Art Generally, a computer system is provided with a dedicated database arithmetic processing unit for executing sort processing and search processing of a relational database at high speed. This database arithmetic processing unit includes an arithmetic circuit called a hardware sorter. This hardware sorter is a pipeline sorter composed of a plurality of sort cells that perform 2-way merge, and can sort (sort) a plurality of data at a time.

When the data amount of the calculation target file is small, the sorted string (partial sorted string) can be generated by only one sort process by the hardware sorter. The process of sorting all the data to be calculated by the hardware sorter at once is called an internal sort process and can be executed at high speed by the hardware sorter.

However, when the amount of data to be calculated is large, or when a plurality of files are to be calculated, the hardware sorter cannot sort at once, so a plurality of partial sort sequences generated by the hardware sorter cannot be sorted. Need to merge. The sort process requiring the merge process is called an external sort, and conventionally, there are the following two methods for performing the merge process.

The first is a method of merging with a host device. In other words, in this method, the database processing unit is in charge of only sorting using the hardware sorter,
All subsequent processing is performed by the host device.

However, when merging is performed by the host device in this way, the load of the host device is increased. Further, in order for the host device to perform merging, since the partial sort sequence generated by the hardware sorter must be transferred from the database arithmetic processing device to the host device, the overhead caused by the data transfer is also very large. Become.

The second is a method of performing a merge process by a hardware sorter in the database arithmetic processing device, not by the host device. However, as described above, since the hardware sorter is formed by cascade-connecting 2-way merge sort cells, the number of sorted partial sort sequences that can be merged is limited to two because of its nature. Therefore, when there are more than two partial sort sequences initially generated by the hardware sorter, it is necessary to repeat the merge process by the hardware sorter in a tournament manner.

In this way, the hardware sorter 2
-If the way merge process is repeatedly executed, the load on the host device can be reduced, but since the amount of data movement in the database arithmetic processing device and the number of data comparisons by the hardware sorter increase, a lot of time is required for the merge process. This leads to the inconvenience of being required.

As described above, conventionally, high performance can be expected when all the data can be sorted at once by the hardware sorter, but when, for example, external sorting cannot be sorted at once and merge processing is required. However, there is a problem that the performance of the host device is lowered due to the increase of the load of the host device or the increase of the calculation time.

[0010]

Conventionally, when the data to be calculated cannot be sorted at one time and merge processing is required, the load on the host device increases or the performance decreases due to an increase in calculation time. was there.

The present invention has been made in view of the above circumstances, and enables a plurality of partial sort sequences to be merged in the arithmetic processing device without using a hardware sorter, thereby significantly reducing the load on the host device. Moreover, it is an object of the present invention to provide a data processing device capable of realizing a sufficiently high-speed sort process.

[0012]

Means and Actions for Solving the Problems
A host device, a secondary storage device in which file data to be operated are stored, and a path for directly accessing the secondary storage device, and the file data to be operated is converted to the file data to be operated in response to a request from the host device. In a data processing device including an arithmetic processing device that executes a predetermined arithmetic processing, means for inputting file data to be operated from the secondary storage device via the path to the arithmetic processing device, An operation circuit that performs a predetermined operation process on the input file data of the operation target to generate a plurality of partial sort sequences and a plurality of partial sort sequences generated by the operation of this arithmetic circuit are merged together. By 1
In the arithmetic processing device, there are provided merge means for generating a sorted sort sequence of the book, and means for outputting the sort sequence generated by the merge means to the secondary storage device via the path. The first feature is that the plurality of partial sort sequences are merged together.

In this data processing device, the merging means is provided in the arithmetic processing device, and the plurality of partial sort sequences generated by the arithmetic circuit are provided not in the arithmetic circuit but in the arithmetic processing device. By the merging means, they are collectively merged (n-way merge) at one time, and thereby, one sorted sort sequence is generated. And
The sort sequence generated by this merging means is directly output from the arithmetic processing unit to the secondary storage unit. For this reason, a plurality of partial sort sequences can be merged in the arithmetic processing device without using the arithmetic circuit, the load on the host device can be significantly reduced, and the amount of data movement can be reduced more than when the arithmetic circuit is repeatedly used. Since it can be reduced, high speed sort processing can be realized.

Further, according to the present invention, a multiprocessor configuration including first to third processors is adopted in the arithmetic processing device, and data input / output between the arithmetic processing device and the secondary storage device is performed in the first processor. , The arithmetic processing using the arithmetic circuit is distributed to the second processor, and the overall control and merge processing are distributed to the third processor.
The data input by the first processor and the arithmetic processing by the third processor are operated in parallel, and the merge processing by the third processor and the data output processing by the first processor are operated in parallel. This is the second feature.

In this configuration, the load distribution is achieved by the first to third processors, and the data input and sort operation processes, and the merge process and data output are operated in parallel, so that the sort process is required. The overall time can be significantly reduced. Therefore, the merge process can be performed in the arithmetic processing device without causing a problem that the total sort process time is increased by the time required for the merge process, and a high-performance device can be realized.

[0016]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows the overall system configuration of a data processing apparatus according to an embodiment of the present invention. This data processing device includes a host computer 10 and a database arithmetic processing device (database engine; DBE).
16 and a magnetic disk device 17. The host computer 10 is composed of a CPU 11, a main storage device 12, and first and second channel devices 14 and 15, and these CPU 11 and main storage device 1
2 and the channel devices 14 and 15 are the system bus 13
Are interconnected via.

The host computer 10 and the database processing unit 16 are connected by a channel unit 14,
The host computer 10 and the magnetic disk device 17 are connected by a channel device 15. Further, the database arithmetic processing unit 16 and the magnetic disk unit 17 are connected via a dedicated path 18.

The CPU 11 controls the host computer 10 as a whole, and requests the database arithmetic processing unit 16 to execute various arithmetic processes such as sorting and relational algebraic arithmetic. The main storage device 12 stores a command for instructing the database operation processing device 16 about an operation target file and operation contents.

Database processing unit (DBE) 16
Is for executing arithmetic processing on the data of the calculation target file based on a command from the CPU 11,
The magnetic disk device 17 is directly accessed via the path 18 in order to input the calculation target file and output the calculation result.

This database processing unit (DBE)
16 is an engine interface processor (EI
P) 161, engine control processor (ECP) 16
2. A large capacity memory (EBDM) 163, a hardware sorter control processor (ECAM) 164, a parallel sorting module (PSOM) 165, and a parallel relational algebraic operation module (PRAM) 166.

Engine interface processor (E
IP) 161, engine control processor (ECP) 16
2 and hardware sorter control processor (ECA
M) 164 of the three processors are interconnected by an internal bus 167, and a large capacity memory (EBDM) 1
A tightly coupled multiprocessor having 63 as a shared memory is configured. The large capacity memory (EBDM) 163 is arranged in a common address space of each of the three processors. Further, the functions are distributed to these three processors, that is, the engine interface processor (EIP) 161, the engine control processor (ECP) 162, and the hardware sorter control processor (ECAM) 164. In this case, in order to efficiently perform their respective unique roles, the respective processors are configured to be tightly coupled and controlled by independent monitors suitable for the respective processors.

Engine interface processor (E
IP) 161, engine control processor (ECP) 16
2 and hardware sorter control processor (ECA
The function distribution of M) 164 is as follows.

That is, the engine interface processor (EIP) 161 performs communication between the host computer 10 and the database arithmetic processing unit 16, and
It is also connected to the disk controller of the magnetic disk device 17 via a path 18, and controls data input / output with the magnetic disk device 17. Further, the engine interface processor (EIP) 161 also performs reconfiguration processing of an output file when outputting data to the magnetic disk device 17.

In communication with the host computer 10, an engine interface processor (EI) is used.
P) 161 is the CPU via the first channel device 14
It receives the command sent from 11 and sends it to the engine control processor (ECP) 162. Also,
Engine interface processor (EIP) 161
Receives the status as a command result sent from the engine control processor (ECP) 162, and sends it back to the CPU 11 via the first channel device 14.

In the data input / output processing with the magnetic disk device 17, the engine interface processor (EIP) 161 includes an engine control processor (EC).
P) receives an input / output request from 162 and transfers data between the large capacity memory (EBDM) 163 and the magnetic disk device 17.

Engine Control Processor (ECP) 162
Is an engine interface processor (EIP) 1
61, a mass memory (EBDM) 163, and a hardware control processor (ECAM) 164 on the internal bus 1
67 and a large-capacity memory (EBD
M) The n-way merge is performed on the partial sort sequence stored in 163.

This n-way merge processing is to merge all the plurality of partial sort sequences to be merged together. That is, the engine control processor (ECP) 1
62 is a hardware control processor (ECAM) 16
4, parallel sorting module (PSOM) 165,
And parallel relational algebra operation module (PRAM) 166
The software performs a process of selecting, for example, the element having the smallest value from among the first elements of the plurality of partial sort sequences generated by the sorting process according to 1. In this case, for the partial sort sequence in which the leading element is moved to the output sequence, the next element becomes the leading element, and this leading element is compared with the leading elements of other partial sorting sequences. A specific processing procedure of such an n-way merge by the engine control processor (ECP) 162 will be described later with reference to FIG.

A large-capacity memory (EBDM) 163 is a file data to be operated, which is read from the magnetic disk device 17, a hardware sorter control processor (ECA).
M) 164, Parallel Sorting Module (PSOM)
165, and parallel relational algebra operation module (PRA
M) 166 is a shared memory for storing the sort processing result by the engine control processor (ECP) 162 and the merge result by the engine control processor (ECP) 162. The file data to be operated is stored in the input buffer unit in the large capacity memory (EBDM) 163, and the sorting result and the merge result are stored in the output buffer unit in the large capacity memory (EBDM) 163.

Hardware sorter control processor (EC
AM) 164 is an engine control processor (ECP) 1
Based on the command from 62, the operations by the parallel sorting module (PSOM) 165 and the parallel relational algebraic operation module (PRAM) 166 are controlled.

In this case, the hardware sorter control processor (ECAM) 164 is a large capacity memory (EBDM).
Parallel sorting module (PS
The OM) 165 and the arithmetic result output from the parallel relational algebraic arithmetic module (PRAM) 166 are stored in the large capacity memory (EBDM) 163. When the data is input to the parallel sorting module (PSOM) 165, Execute the key cutout process. In this key cutout processing, the hardware sorter control processor (ECAM) 164 cuts out only the key necessary for the calculation from each record to be calculated, and adds the record identification number (the start address of the record in the large capacity memory 163) to it. Add parallel parallel sorting module (PSO
M) Send to 165.

Parallel sorting module (PSOM)
165 is a hardware sorter control processor (ECA
M) is a dedicated hardware circuit that is driven by 164 and executes sorting in parallel, and is connected to a parallel relational algebra operation module (PRAM) 166. The parallel sorting module (PSOM) 165 is called a pipeline merge sorter, and is composed of a plurality of sort cells cascade-connected to perform 2-way merge.

Parallel Relational Algebra Operation Module (PRAM)
Reference numeral 166 denotes a dedicated hardware circuit that executes relational algebraic operations such as JOIN (join) and RESTRICT (restriction) in a relational database in parallel, and inputs sorted data from the parallel sorting module (PSOM) 165 to perform arithmetic operations. The result is output to the hardware sorter control processor (ECAM) 164. When only the sorting process is executed, the parallel relational algebraic operation module (PRAM) 166 functions as the final sort cell.

As described above, the functions for external sorting are distributed to the engine interface processor (EIP) 161, the engine control processor (ECP) 162, and the hardware sorter control processor (ECAM) 164. In this case, these processors operate asynchronously except for the exchange of buffers on the large capacity memory (EBDM) 163, and execute the respective functions in parallel. That is, the external sort is composed of an input process, a sort process, a merge process, and an output process, but the sort operation process under the control of the hardware sorter control processor (ECAM) 164 is an operation by the engine interface processor (EIP) 161. The data output processing executed by the engine interface processor (EIP) 161 in parallel with the input processing of the target data is the engine control processor (ECP).
It is executed in parallel with the merge processing by 162.

Next, the operation of the external sort processing executed by the data processing apparatus of FIG. 1 will be described.

First, an outline of the processing flow of the entire data processing apparatus will be described.

The CPU 11 issues commands such as sorts stored in the main memory 12 to the database arithmetic processing unit 16 via the system bus 13. The command is stored in the large capacity memory (EBDM) 163. The engine control processor (ECP) 162 analyzes the command, reads the data to be processed from the magnetic disk device 17 into the large capacity memory (EBDM) 163 via the engine interface processor (EIP) 161, and reads it. Wear sorter control processor (ECA
M) Pass to 164 to execute sort processing. The hardware sorter control processor (ECAM) 164 processes the target data in the parallel sorting module (PSO).
M) 165 to parallel relational algebra module (PRA
M) 166, and when the processing is completed, it reports to the engine control processor (ECP) 162. The engine control processor (ECP) 162 merges (n-way merge) the sorting results including a plurality of sorting strings. Engine interface processor (EI
P) 161 outputs the processing result to the disk device 17,
Then, the response corresponding to the given command is returned to the CPU 11 via the system bus 13.

Next, referring to the flow chart of FIG.
The operation in the database arithmetic processing unit 16 will be described.

As described above, the large capacity memory (EBD
M) 163 stores data to be sorted by the input processing by the engine interface processor (EIP) 161, and arithmetic control by the hardware sorter control processor (ECAM) 164 is executed in parallel with this input processing. That is, the engine interface processor (EIP) 161 is the magnetic disk device 1
As long as the target data exists in 7, the input is made to the large capacity memory (EBDM) 163, which is passed to the hardware sorter control processor (ECAM) 164.

Hardware sorter control processor (EC
The AM) 164 transfers the data stored in the large capacity memory (EBDM) 163 to the parallel sorting module (PS).
OM) 165 and parallel relational algebra calculation module (PR
(AM) 166 divides into strings for each number that can be sorted at a time, and sort processing is executed for each string until there is no unprocessed data (steps S11, S).
12). Parallel sorting module (PSOM) 16
5 and parallel relational algebra operation module (PRAM) 16
6 sequentially generates a sorted data string (partial sort string) of a certain size by the sorting process.

Now, with reference to FIGS. 3 and 4, a specific example of the operation target data stored in the large capacity memory (EBDM) 163 and the partial sort sequence generated by the sorting process will be described.

As shown in FIG. 3, the operation target data is composed of, for example, n × 4 records R1, R2, ..., Each record including, for example, five fields F1 to F5. I'm out. When the number of items that can be sorted at a time by the parallel sorting module (PSOM) 165 and the parallel relational algebra operation module (PRAM) 166 is n, as shown in the figure, the operation target data is four records each consisting of n records. Split into strings.

When such operation target data is sorted, for example, using the third field F3 as a key field, the hardware sorter control processor (ECAM) 164 uses the respective records R1 to be operated. R
2 ... from the third field F3 (K1, K
2, ...) are cut out and the record identification number (the head address AD1, AD of the record on the memory 163) is added to it.
2, ...) are added and passed to the parallel sorting module (PSOM) 165 and the parallel relational algebra operation module (PRAM) 166.

Parallel sorting module (PSOM)
165, parallel relational algebra operation module (PRAM) 16
6 sorts each string to generate a partial sort sequence sorted in ascending or descending order.

FIG. 4 shows partial sort sequences S1 to S4 in the case of sorting in ascending order. These partial sort sequences S1 to S4 correspond to the first to fourth strings of the calculation target data, respectively. As shown in the figure, the elements of each partial sort sequence S1 to S4 are composed of a record identification number and a key part, and such partial sort sequences S1 to S4 are stored in the large capacity memory (EBDM) 163 as the sorting result. Stored in.

When all sort processing of the data to be calculated is executed, the engine control processor (ECP) 162
The partial sort sequences S1 to S4 are merged together to generate one aligned string as shown in FIG. 5 (step S13). As shown in FIG. 5, each element of the string generated by the engine control processor (ECP) 162 merge consists of a record identification number only,
The record identification numbers are arranged in order from the smallest value in the key part. The merged result is stored in the large capacity memory (EBDM) 163.

Next, referring to FIG. 6, a specific processing procedure of the n-way merge executed by the engine control processor (ECP) 162 by software will be described.

In FIG. 6, for simplification of explanation, the record identification number and the key part forming each element of the partial sort sequences S1 to S4 are collectively shown as R (n). Here, the value of n in parentheses corresponds to the value of the key part.

First, the engine control processor (ECP)
162 extracts the head element {R (1), R (2), R (9), R (10)} from each of the partial sort sequences S1 to S4, and compares the head elements between the partial sort sequences S1 and S2. By selecting the first element (here, R (1)) having a smaller value between the two partial sort sequences S1 and S2 as the first output, and comparing the leading elements between the partial sort sequences S3 and S4. Two partial sort sequences S3 and S4
The first element with the smaller value (in this case, R (9))
Is selected as the second output. Next, the engine control processor (ECP) 162 compares the elements of the first output and the second output, and determines the smaller element (here, R (1)) as the four leading elements of the partial sort sequences S1 to S4. R (1), R
(2), R (9), R (10)} is moved to the merge result output sequence as the smallest element.

In this way, when the head element of the partial sort sequence S1 is moved to the merge result output sequence, the partial sort sequence S1.
The second element of 1 (here, R (3)) becomes a new top element of the partial sort sequence S1, and the engine control processor (ECP) 162 causes the new top element of the partial sort sequence S1 (R (3)). ) And the first element of the partial sort sequence S2 (R
By comparison with (2)), the first output (here, R
(2)) is selected. The engine control processor (ECP) 162 then compares the elements of the first output (R (2)) and the second output (R (9)) and determines the smaller element (here, R (2)). It is moved to the merge result output string as the smallest element among the four leading elements {R (3), R (2), R (9), R (10)} of the partial sort strings S1 to S4.

When the head element of the partial sort sequence S2 is moved to the merge result output string, the second element of the partial sort sequence S2 (here, R (4)) is set as a new head element of the partial sort sequence S2. The same processing as the previous time is performed.

Thus, the engine control processor (E
CP) 162 is four partial sort sequences S1 to be merged.
From among the first elements of each of S4 to S4, for example, the element having the smallest value is selected and moved to the output column. Then, for the partial sort sequence in which the first element is moved to the output column, the next element is treated as the first element. 4-way merge is executed for the partial sort sequences S1 to S4.

Engine Control Processor (ECP) 162
The result of merging is output to the magnetic disk device 17 by the engine interface processor (EIP) 161. In this case, as described with reference to FIG. 5, since the merged result is composed only of the arrangement of the record identification numbers, the engine interface processor (EI
The P) 161 performs an output file reconstruction process when outputting data to the magnetic disk device 17.

That is, the engine interface processor (EIP) 161 reconstructs the record of the data to be operated in FIG. 3 according to the order of the merged result in FIG. 5, and outputs it to the magnetic disk device 17. The reconstruction and output processing by the engine interface processor (EIP) 161 is executed in parallel with the n-way merge processing by the engine control processor (ECP) 162.

FIG. 7 shows a timing chart in the database arithmetic processing unit 16 at the time of executing the external sort in this embodiment.

As shown in FIG. 7, the input processing by the engine interface processor (EIP) 161 and the parallel sorting module (PSOM) 165.
And parallel relational algebra operation module (PRAM) 166
Hardware Control Processor (ECAM) 16
The sorting process by 4 is operated in parallel. Further, an engine control processor (ECP) 1 for merging the partial sort sequences S1 to S4 generated by the sorting process together.
The n-merge processing by 62 and the output processing by the engine interface processor (EIP) 161 are also operated in parallel.

As can be seen from the timing chart of FIG. 7, in the apparatus of this embodiment, the total processing time required for the external sort is almost determined by the input / output time, and the processing time required for the sort processing and the merge processing is not so problematic. Not Therefore, a sufficient performance improvement can be realized as compared with the case where the host computer 10 executes the merge process.

As described above, in this embodiment, the engine control processor 162 is provided with the function of n-way merge, and is generated by the hardware sorter (164, 165, 166) which performs the 2-way merge processing. The partial sort sequences S1 to S4 are merged at once by the n-way merge process by the engine control processor 162, not by the hardware sorter thereof, thereby generating one sorted sort sequence. Therefore, a plurality of partial sort sequences can be merged at once in the database arithmetic processing unit 16, and the host computer 10
The load of can be significantly reduced, and the amount of data movement can be reduced as compared with the case where the hardware sorters (164, 165, 166) are repeatedly used, and accordingly, high speed sort processing can be realized.

Further, in this embodiment, a multiprocessor configuration is adopted for the database arithmetic processing unit 16, and data input / output with the magnetic disk unit 17 is carried out by an engine interface processor (EIP) 161 and a parallel sorting module (PSOM). 165 and a parallel relational algebraic operation module (PRAM) 166 using a hardware circuit for control of sort processing by a hardware sorter control processor (ECAM) 164, and overall control and merge processing by an engine control processor (ECP) 1
Since the functions are respectively distributed to 62, the input process and the sort process, and the merge process and the output process in the external sort are operated in parallel. Therefore, the total time required for the external sort processing can be significantly reduced, and a high performance device can be realized.

[0060]

As described above, according to the present invention, a plurality of partial sort sequences can be merged in the database arithmetic processing device without using a hardware sorter, and the load on the host device is greatly reduced. Moreover, it is possible to realize a sufficiently high-speed sort process.

[Brief description of drawings]

FIG. 1 is a block diagram showing a system configuration of a data processing device according to an embodiment of the present invention.

FIG. 2 is a flowchart for explaining the operation of the database arithmetic processing device in the system of FIG.

FIG. 3 is a diagram showing an example of a data structure of calculation target input data in the system of FIG.

4 is a diagram showing an example of a data structure of a partial sort sequence in the system of FIG.

5 is a diagram showing an example of a data structure of a merge result in the system of FIG.

6 is a diagram showing an operation procedure of an n-way merge process executed in the database arithmetic processing unit of the system of FIG.

FIG. 7 is a timing chart for explaining an operation when executing an external sort in the system of FIG.

[Explanation of symbols]

10 ... Host computer, 16 ... Database operation device, 17 ... Magnetic disk device, 161, 162, 164
... processor, 163 ... mass memory, 165 ... parallel sorting module, 166 ... parallel relational algebra operation module.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Asahiko Yamada 2-9 Suehiro-cho, Ome-shi, Tokyo Incorporated Toshiba Ome Plant

Claims (2)

[Claims] 1. A host device, a secondary storage device for storing file data to be operated, and a path for directly accessing the secondary storage device, wherein the operation is performed in response to a request from the host device. A data processing device comprising: an arithmetic processing device that executes a predetermined arithmetic process on target file data, wherein the arithmetic processing device inputs the operation target file data from the secondary storage device via the path. Means, an arithmetic circuit that executes a predetermined arithmetic process on the input file data to be arithmetically operated to generate a plurality of partial sort sequences, and a plurality of partial sort sequences generated by the arithmetic operation by the arithmetic circuit. Means for generating one sorted sort sequence by merging together and outputting the generated sort sequence to the secondary storage device via the path. And means for data processing apparatus characterized by merging together the plurality of the partial sort columns within the processor. 2. A host device, a secondary storage device in which file data to be operated are stored, and a path for directly accessing the secondary storage device, and the operation is performed in response to a request from the host device. A data processing device comprising: an arithmetic processing device that executes a predetermined arithmetic process on target file data, wherein the arithmetic processing device communicates with the host device, and communicates with the secondary storage device. Processor for executing data input / output, an arithmetic circuit for performing sorting or relational algebraic operation, a second processor for executing and controlling the arithmetic operation by the arithmetic circuit, and an operation target input by the first processor From the host device supplied via the first processor and an internal memory for storing the file data of A third processor that controls the operations of the first and second processors based on an instruction, wherein the third processor collectively merges a plurality of partial sort sequences generated by the arithmetic operation by the arithmetic circuit. To generate a single sorted sequence, the input processing of the calculation target data by the first processor and the calculation processing by the second processor are executed in parallel, and the third processor The data processing apparatus is configured such that the merging process by the above and the data output process of the calculation result by the first processor are executed in parallel.