JPH0581343A - Data processor - Google Patents

Abstract

PURPOSE:To reduce the total number of commands and to improve the arithmetic processing performance by constituting an arithmetic processor so that a series of processings required for an arithmetic processing can be executed by one command. CONSTITUTION:One composite command obtained by collecting information of a plural command portion is issued from a CPU 11, and its composite command is interpreted by an engine control processor(ECP) 162 of a data base arithmetic processor 16. Subsequently, in accordance with designating information and arithmetic information of an input file contained in its composite command, and output destination designating information of a result of its operation, an input processing and an output processing by an engine interface processor(EIP) 161, and a control processing of an operation by a hardware sorter control processor (ECAM) 164 are controlled. Accordingly, a processing of a plural command portion can be instructed in a lump by one command, the total number of commands is reduced, and the arithmetic processing performance can be improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing device having an arithmetic processing device for executing arithmetic processing such as sorting or relational algebraic arithmetic on file data to be arithmetically operated in response to a request from a host device.

[0002]

2. Description of the Related Art Generally, a computer system is provided with a dedicated database arithmetic processing unit for executing sort processing and search processing of a relational database at high speed. This database arithmetic processing device is provided with an arithmetic circuit called a hardware sorter, and by using this arithmetic circuit, sorting and relational algebraic arithmetic etc. are executed at high speed according to arithmetic processing requests from the host device.

In this database processing device,
When processing the file data on the secondary storage device of the host device, first, the data to be processed is input from the secondary storage device in accordance with a read command from the host device. Then, a sort or relational algebraic operation is executed according to a predetermined operation designation command from the host device, and then the operation result is displayed on a predetermined output file on the secondary storage device according to a command for data output from the host device. Is output.

As described above, conventionally, the command issued from the host device requires only one function,
Each time the database processing device receives a command from the host device, it executes one function specified by the command.

However, in this way, one command
When one processing target is designated, the structure of the command becomes simple, but (1) the total number of commands issued from the host device increases, and (2) the host device and the database calculation process due to the increase in the total command number. This causes a problem that communication between devices becomes complicated, and (3) a series of processes such as data input, calculation, and output are serially performed, resulting in deterioration of calculation processing performance.

Further, when input data is sorted out under a relatively complicated selection condition including a plurality of selection conditions, the host device needs to issue a calculation instruction command to the database calculation processing device for each selection condition. It is said that.

In this case, the data base arithmetic processing device performs processing such as reading processing data to be operated from the internal memory, selecting processing according to a single selection condition for the data, and writing processing result to the internal memory. It is necessary to repeatedly execute each instruction command.
When the calculation is repeated many times for the same data in this manner, the amount of movement of the data is increased, and a long time is required for the calculation process.

[0008]

Conventionally, the command issued from the host device requires only one function, the communication with the host device is complicated due to the increase in the total number of commands, and one command is also required. There is a drawback that the processing performance is lowered by serially executing the processing of one function for a plurality of commands.

The present invention has been made in view of the above circumstances, and enables an arithmetic processing unit to execute a series of processing required for arithmetic processing with one command, thereby reducing the total number of commands and improving arithmetic processing performance. An object of the present invention is to provide a data processing device capable of realizing the above.

[0010]

Means and Actions for Solving the Problems
A host device, a secondary storage device in which file data to be operated are stored, and a path for directly accessing the secondary storage device, and the file data to be operated is converted to the file data to be operated in response to a request from the host device. In a data processing device including an arithmetic processing device that executes a predetermined arithmetic processing, an input means for inputting the file data of the arithmetic object to the arithmetic processing device via the path, and the input data. Arithmetic processing means for performing sorting or relational algebraic arithmetic on the same, output means for outputting the arithmetic processing result by the arithmetic processing means to the secondary storage device via the path, and a plurality of means issued from the host device. Interpret a compound command that summarizes the information for the command, specify the operation target file included in the compound command, specify the operation processing content And said input means in accordance with the output destination designation information of the calculation result, the first characterized in that a control means for controlling the processing means and output means.

In this data processing device, the host device issues one composite command in which information for a plurality of commands is collected, and the composite command is interpreted by the arithmetic processing device. Then, the input processing, the arithmetic processing, and the output processing are controlled according to the designation information of the computation target file, the designation information of the computation processing content, and the output destination designation information of the computation result included in the composite command. Therefore, the arithmetic processing device can execute the processing for a plurality of commands with one command, and it is possible to reduce the total number of commands and improve the arithmetic processing performance.

Further, according to the present invention, a multiprocessor configuration including first to third processors is adopted in the arithmetic processing device, and data input / output between the arithmetic processing device and the secondary storage device is performed in the first processor. , The arithmetic processing using the arithmetic circuit is distributed to the second processor, and the overall control is distributed to the third processor, and the third processor interprets the composite command and is included in the composite command. The data input / output processing by the first processor and the arithmetic control processing by the second processor are controlled according to the designation information of the computation target file, the designation information of the computation processing content, and the output destination designation information of the computation result. The second feature is that it is configured.

In this configuration, the load can be efficiently distributed by the first to third processors, and a plurality of functions included in the composite command can be recognized at once by the third processor that interprets the composite command. ,
Operations of the first and second processors can be controlled so that the processors are operated in parallel. Therefore, the operation performance of the arithmetic processing device can be sufficiently improved.

[0014]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows the overall system configuration of a data processing apparatus according to an embodiment of the present invention. This data processing device includes a host computer 10 and a database arithmetic processing device (database engine; DBE).
16 and a magnetic disk device 17. The host computer 10 is composed of a CPU 11, a main storage device 12, and first and second channel devices 14 and 15, and these CPU 11 and main storage device 1
2 and the channel devices 14 and 15 are the system bus 13
Are interconnected via.

The host computer 10 and the database processing unit 16 are connected by a channel unit 14,
The host computer 10 and the magnetic disk device 17 are connected by a channel device 15. Further, the database arithmetic processing unit 16 and the magnetic disk unit 17 are connected via a dedicated access path 18.

The CPU 11 controls the host computer 10 as a whole, and requests the database arithmetic processing unit 16 to execute various arithmetic processes such as sorting and relational algebraic arithmetic. The main storage device 12 stores a command for instructing the database operation processing device 16 about an operation target file and operation contents. This command includes a READ (read) command for reading data from the magnetic disk device 17, and a PROJ for outputting data in the specified format to the magnetic disk device 17.
ACTION (projection) command, SORT (sort) command to sort by specified key fields, RESTRICT (constraint) command to perform constraints on fields of different files (tables), on the same file SELECT command to select by field or constant, JOIN to combine by specified key field
There are a (join) command, a WORKFILE command for designating a work file on the magnetic disk device 17, and the like.

Further, as a command obtained by grouping these commands, for example, SEL-SORT-PRO
There are J command and SEL-SEL-JOIN command. The SEL-SORT-PROJ command is
Input data selection process by CT command, marshalling process by SORT command, and PROJECTION
This is a command for collectively instructing projection output processing by a command. The SEL-SEL-JOIN command is a SELECT for each of the two input files.
It is a command that collectively instructs the command selection process and the joining process of the selection results by the JOIN command.

Further, each command for these operations can include a plurality of selection conditions for selecting data. In this case, these plural selection conditions are converted into one conditional expression by the reverse Polish method.

In other words, the CPU 11 uses the SQL language IN
Terminology, BETWEEN terminology is compared terminology (<,>, ≤,
≤, =, etc.), and by expressing special conditional expressions such as the NULL term and the LINK term in the expanded form of the comparative term, the selection condition consisting of a plurality is converted into the reverse Polish expression, Convert to one conditional expression. Here, the inverse Polish formula is a well-known notation in which an operator is placed after an operation number, so that a plurality of AND / OR
It is possible to easily express the selection according to the conditions.

The command generated by the CPU 11 includes not only such a combination of a plurality of calculation instructions but also information necessary for the calculation processing, that is, an input for designating a calculation target file on the magnetic disk device 17. File information, a work file on the magnetic disk device 17 to be used for arithmetic processing, and information for designating an output file on the magnetic disk device 17 to output the arithmetic result are also incorporated.

Therefore, the operation request (engine command) issued by the CPU 11 to the database operation processing device 16 can specify data input processing, operation processing, and operation result output processing at one time.

Database processing unit (DBE) 16
Is for executing arithmetic processing on the data of the calculation target file based on a command from the CPU 11,
The magnetic disk device 17 is directly accessed via the path 18 in order to input the calculation target file and output the calculation result.

This database arithmetic processing unit (DBE)
16 is an engine interface processor (EI
P) 161, engine control processor (ECP) 16
2. A large capacity memory (EBDM) 163, a hardware sorter control processor (ECAM) 164, a parallel sorting module (PSOM) 165, and a parallel relational algebraic operation module (PRAM) 166.

Engine interface processor (E
IP) 161, engine control processor (ECP) 16
2 and hardware sorter control processor (ECA
The three processors M) 164 are interconnected by an internal bus 167, and a large capacity memory (EBDM) 16
3 constitutes a tightly coupled multiprocessor having 3 as a shared memory. The large capacity memory (EBDM) 163 is arranged in a common address space of each of the three processors. Further, the functions are distributed to these three processors, that is, the engine interface processor (EIP) 161, the engine control processor (ECP) 162, and the hardware sorter control processor (ECAM) 164. In this case, in order to efficiently perform their respective unique roles, the respective processors are configured to be tightly coupled and controlled by independent monitors suitable for the respective processors.

Engine interface processor (E
IP) 161, engine control processor (ECP) 16
2 and hardware sorter control processor (ECA
The function distribution of M) 164 is as follows.

That is, the engine interface processor (EIP) 161 performs communication between the host computer 10 and the database arithmetic processing unit 16, and
It is also connected to a disk controller of the magnetic disk device 17 via a path 18 and controls data input / output with the magnetic disk 17. Further, the engine interface processor (EIP) 161 is a large capacity memory (EB).
At the time of data input / output between the DM) 163 and the magnetic disk device 17, a reconstruction process such as deleting or rearranging fields in a record as data is executed.

In communication with the host computer 10, an engine interface processor (EI) is used.
P) 161 is the CPU via the first channel device 14
It receives the command sent from 11 and sends it to the engine control processor (ECP) 162. Also,
Engine interface processor (EIP) 161
Receives the status as a command result sent from the engine control processor (ECP) 162, and sends it back to the CPU 11 via the first channel device 14.

In the data input / output processing with the magnetic disk device 17, the engine interface processor (EIP) 161 includes an engine control processor (EC).
P) receives an input / output request from 162 and transfers data between the large capacity memory (EBDM) 163 and the magnetic disk device 17.

Engine Control Processor (ECP) 162
Interprets a command from the CPU 11 and controls an engine interface processor (EIP) 161, a large capacity memory (EBDM) 163, and a hardware control processor (ECAM) 164 via an internal bus 167. When an integrated composite command (engine command) including information for a plurality of commands is received, the engine control processor (ECP) 162 interprets the composite command and outputs a plurality of commands specified by the composite command. The engine interface processor (EIP) 161, the mass memory (EBDM) 163, and the hardware control processor (ECAM) 164 are controlled so that the functions of

The large-capacity memory (EBDM) 163 is the file data of the operation target read from the magnetic disk device 17, and the hardware control processor (ECAM) 16
4, parallel sorting module (PSOM) 165,
And parallel relational algebra operation module (PRAM) 166
It is a shared memory that stores the calculation processing result by the engine control processor (ECP) 162 and the integration result of the calculation result by the engine control processor (ECP) 162. The file data to be calculated is stored in the input buffer unit in the large capacity memory (EBDM) 163, and the calculation processing result is the large capacity memory (EBDM) 16
3 is stored in the output buffer unit.

Hardware sorter control processor (EC
AM) 164 is an engine control processor (ECP) 1
Based on the command from 62, the operations by the parallel sorting module (PSOM) 165 and the parallel relational algebraic operation module (PRAM) 166 are controlled.

In this case, the hardware sorter control processor (ECAM) 164 is a large capacity memory (EBDM).
Parallel sorting module (PS
The OM) 165 and the arithmetic result output from the parallel relational algebraic arithmetic module (PRAM) 166 are stored in the large capacity memory (EBDM) 163. When the data is input to the parallel sorting module (PSOM) 165, Execute the key cutout process. In this key cutout processing, the hardware sorter control processor (ECAM) 164 cuts out only the key necessary for the calculation from each record to be calculated, and adds the record identification number (the start address of the record in the large capacity memory 163) to it. Add parallel parallel sorting module (PSO
M) Send to 165.

Further, the hardware sorter control processor (ECAM) 164 selects data specified by the command. This selection is executed by successively applying a plurality of selection conditions to each record of the input data.

Parallel Sorting Module (PSOM)
165 is a hardware sorter control processor (ECA
M) is a dedicated hardware circuit that is driven by 164 and executes sorting in parallel, and is connected to a parallel relational algebra operation module (PRAM) 166. The parallel sorting module (PSOM) 165 is called a pipeline merge sorter, and is composed of a plurality of sort cells cascade-connected to perform 2-way merge.

Parallel Relational Algebra Operation Module (PRAM)
Reference numeral 166 denotes a dedicated hardware circuit that executes relational algebraic operations such as JOIN (join) and RESTRICT (restriction) in a relational database in parallel, and inputs sorted data from the parallel sorting module (PSOM) 165 to perform arithmetic operations. The result is output to the hardware sorter control processor (ECAM) 164. When only the sorting process is executed, the parallel relational algebraic operation module (PRAM) 166 functions as the final sort cell.

As described above, the engine interface processor (EIP) 161, the engine control processor (ECP) 162, and the hardware sorter control processor (ECAM) 164 have functions for executing various arithmetic processes distributed therein. .. In this case, these processors operate asynchronously except for the exchange of buffers on the large capacity memory (EBDM) 163, and execute the respective functions in parallel. That is, processing such as sorting and selection is usually composed of input processing, arithmetic processing, and output processing, but the hardware sorter control processor (EC
The calculation processing under the control of the AM) 164 is executed in parallel with the input processing of the calculation target data by the engine interface processor (EIP) 161. Further, when the calculation result from the hardware sorter control processor (ECAM) 164 needs to be integrated by the engine control processor (ECP) 162, the integration processing and the output processing by the engine interface processor (EIP) 161 are performed in parallel. Is executed.

Next, with reference to FIG. 2, an overall processing flow in the data processing apparatus of FIG. 1 will be described.

First, the CPU 11 specifies a plurality of input files with one command (READ), sets a complicated selection condition as one set, and combines the condition expression with sorting, work file, and output file specification information. The command is created and an engine command corresponding to the processing content is created in the main memory 12 (step S11). Then, the CPU 11 causes the main memory 1
The engine command in No. 2 is transmitted to the database arithmetic processing unit (DBE) 16 via the channel device 14 (step S12).

Engine Control Processor (ECP) 162
Is an engine interface processor (EIP) 1
An engine command is received via 61 (step S13). The received engine command is stored in the large capacity memory (EBDM) 163. The engine control processor (ECP) 162 then receives a large amount of memory (ECP).
BDM) 163 analyzes an engine command that is a collection of a plurality of pieces of information, determines necessary processing, and starts up (step S
14).

The engine control processor (EC
P) 162 is a large capacity memory (EBDM) 163 and an engine interface processor (EIP) 161,
And hardware control processor (ECAM) 164
Sort processing is performed while performing input / output / sorting in parallel using (step S15). After that, the engine control processor (ECP) 162 transmits the status of the arithmetic processing completion, and the status is received by the CPU 11 (steps S16, S17).

Next, referring to the flowchart of FIG.
The control operation for input processing, arithmetic processing, and output processing executed by the engine control processor (ECP) 162 will be described.

First, the engine control processor (ECP)
In order to prepare for data input, the information 162 sets the information of the input file obtained by interpreting the command in the engine interface processor (EIP) 161 as an input parameter (step S21). Next, the engine control processor (ECP) 162 uses the hardware control processor (ECA) with the parameters for selection / sort obtained by the interpretation of the engine command in preparation for selection / sort.
M) 164 (step S22).

After this, the engine control processor (EC
P) 162 uses input and sort in parallel,
Engine interface processor (EIP) 161
Control of the input to and the control of the sort to the hardware control processor (ECAM) 164 are executed in parallel (step S23). Then, the engine control processor (ECP) 162 sets the information of the output file obtained by the interpretation of the engine command as an output parameter in the engine interface processor (EIP) 161 in order to prepare for data output (step S24).
After this, the engine control processor (ECP) 162
In order to operate the sort and the output in parallel, the control of the sort for the hardware control processor (ECAM) 164 or the merge processing in the engine control processor (ECP) 162 and the control of the output for the engine interface processor (EIP) 161 are performed in parallel. (Step S25).

Here, the selection / sort setting process of step S22 and the input / sort control process of step S23 are performed redundantly, and the input / sort control process of step S23 and step S24 are performed. The output parameter setting process is also repeated.

Next, referring to the flowchart of FIG.
A data flow in the data processing device of FIG. 1 will be described.

First, the engine interface processor (EIP) 161 reads the data on the magnetic disk device 17 designated by the input parameter setting processing into the large capacity memory (EBDM) 163 (step S3).
1). Hardware Sorter Control Processor (ECAM)
164 applies the selection processing designated by the selection / sort setting processing to each record, and selects or discards the records (step S32). Then, under the control of the hardware sorter control processor (ECAM) 164 according to the designation of the selection / sort setting process, the parallel sorting module (PSOM) 165 and the parallel relational algebraic operation module (PRAM) 166 are operated in step S32. Sort processing is performed on the selected record group (step S33).

Next, the hardware sorter control processor (ECAM) 164 receives the sorting result of step 33 from the parallel relational algebraic operation module (PRAM) 166 and outputs it to the large capacity memory (EBDM) 163 (step S34). .. After this, the engine interface processor (EIP) 161 is replaced by the large capacity memory (EB
The data of the sorting result on the DM) 163 is processed in step S2.
Write to an output file on the magnetic disk device 17 designated by the output parameter setting process of No. 4 (step S
35).

Here, the input processing, the selection processing, and the sorting processing in steps S31 to S33 are executed in parallel, and the sorting result discharging processing in step S34 and the output processing in step S35 are also executed in parallel. .. Such parallel processing adopts a multiprocessor configuration,
In addition, the engine control processor (ECP) 162 interprets an engine command including a plurality of command information, and causes each of the other processors to execute a necessary operation, which is realized by a system configuration.

Next, the flow of the arithmetic processing by the database arithmetic processing unit 16 will be described by taking the sort processing as an example.

In the case of the sort processing, the request (engine command) from the CPU 11 includes information 1: input file designation (one or more), information 2: selection selection (zero or more), information 3: sorting. Specification (1), information 4: specification of output destination of calculation result (1), information 5: specification of work file for temporarily storing partial sort sequence which is an intermediate result of sort calculation (0 to 1) 5) are included.

In this case, for example, the CPU 11 creates an engine command consisting of a plurality of information 1 to form one command, information 2 to information 4 to form one command, and a total of two commands.

This engine command is sent to the engine control processor (ECP) 162. The engine control processor (ECP) 162 interprets the engine command and outputs it to the engine interface processor (EI).
P) 161 and hardware sorter control processor (ECAM) 164 are instructed to perform input processing and selection / sort processing, respectively. In this case, as described above, the engine command contains the information for a plurality of commands in a unified manner, so that the engine control processor (ECP)
At 162, the processes of steps S21 to S25 described in the flowchart of FIG. 3 are continuously performed.

Such an engine control processor (EC
P) 162, the engine interface processor (EIP) 161 follows step S3 of FIG.
The data input process described in 1 and the result data output process described in step 35 are performed. At this time, the input process and the output process do not overlap. on the other hand,
In the sorting process described in step S32 and the sorting process described in step S33 of FIG. Run with.

In this way, the input file designation, calculation instruction,
An engine control processor (ECP) 1 is used to output operation instructions for input processing, arithmetic processing, and output processing by using an engine command in which a single command for specifying an output file is used.
By 62, it becomes possible to carry out collectively.

Next, a specific example of the engine command sent to the database arithmetic processing unit 16 will be described with reference to FIGS.

Here, as shown in FIG. 5, an employee file A having items such as employee name, age, and annual income,
It is assumed that B is a calculation target, and the employees in their twenties are arranged in the order of decreasing annual income and are output to the output file C.

In this case, as shown in FIG. 6, files A and B are designated as the input file designation information, file C is designated as the output file designation information, and a condition α is designated as the selection condition to be over 20 years old. AND condition with the condition β designating under 30 years old, and as sort information, information of ascending order with the annual income γ as a key is given.

Of such information, the designation information of the two input files of file A and file B is one REA.
The D command is combined, and the output file specification information, the selection condition, the sort condition, and the output file information specifying the file C are combined into one SEL-SORT-PROJ command. Then, as shown in FIG. 7, the READ command and SEL-SORT-PROJ
A two-command engine command including a command and a command is created and sent to the database processing unit 16.

As can be seen from FIG. 7, when the command unification is not performed, the file A is read, the file A is selected by the condition α, the selection result is selected by the condition β, and the selection result is Sorting under the condition γ is executed by the first to fourth commands, and similarly, reading of the file B, selection of the file B by the condition α, selection of the selection result by the condition β, and selection result Sorting under condition γ is 4th from 5th to 8th
Is executed by this command. Then, the ninth command merges the file A sort result with the file B sort result, and then the tenth command outputs the merge result.

On the other hand, when the command is unified, the READ command and SEL-SORT-PRO
The same function can be executed by an engine command consisting of two commands, the J command.

As described above, in this embodiment, C
The PU 11 issues one composite command in which information for a plurality of commands is collected, and the composite command is issued to the engine control processor (EC
P) 162. Then, according to the input file designation information, the computation information, and the output destination designation information of the computation result included in the composite command, the input processing and the output processing by the engine interface processor (EIP) 161 and the hardware sorter control processor ( The control processing of the calculation by the ECAM) 164 is controlled. Therefore, it becomes possible to collectively instruct the processing for a plurality of commands with one command, and it is possible to reduce the total number of commands and improve the arithmetic processing performance.

[0063]

As described above, according to the present invention, the arithmetic processing unit can execute a series of processing required for arithmetic processing with one command, which reduces the total number of commands and improves the arithmetic processing performance. Can be realized.

[Brief description of drawings]

FIG. 1 is a block diagram showing an overall system configuration according to an embodiment of the present invention.

FIG. 2 is a flowchart for explaining the operation of the database operation processing device of the embodiment.

FIG. 3 is a flowchart for explaining the operation of the control processor provided in the database arithmetic processing unit of the embodiment.

FIG. 4 is a flowchart illustrating a data flow in the database arithmetic processing apparatus according to the embodiment.

FIG. 5 is a diagram showing an example of an input file that is arithmetically processed by the database arithmetic processing unit of the embodiment.

FIG. 6 is a diagram showing various conditions when performing arithmetic processing on the input file of FIG. 5;

FIG. 7 is a diagram showing an example of an engine command when arithmetic processing is performed under the conditions of FIG. 6;

[Explanation of symbols]

10 ... Host computer, 16 ... Database operation device, 17 ... Magnetic disk device, 161, 162, 164
... processor, 163 ... mass memory, 165 ... parallel sorting module, 166 ... parallel relational algebra operation module.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Asahiko Yamada 2-9 Suehiro-cho, Ome-shi, Tokyo Incorporated Toshiba Ome Plant

Claims (4)

[Claims] 1. A host device, a secondary storage device for storing file data to be operated, and a path for directly accessing the secondary storage device, wherein the operation is performed in response to a request from the host device. In a data processing device including an arithmetic processing device that executes a predetermined arithmetic processing on target file data, the arithmetic processing device, and an input means for inputting the file data of the arithmetic target via the path, Arithmetic processing means for performing sorting or relational algebraic arithmetic on the input data; output means for outputting the arithmetic processing result by the arithmetic processing means to the secondary storage device via the path; and the host device Interprets a compound command that summarizes the information for multiple commands issued from, and specifies the operation target file included in the compound command and the operation processing The data processing apparatus characterized by comprising a control means for controlling said input means, processing means and output means in accordance with the output destination designation information designating information and the calculation result of the volume. 2. The command information of the operation processing content included in the composite command includes a plurality of selection conditions for selecting the operation target data, and the plurality of selection conditions are converted into one conditional expression by a reverse Polish method. The data processing device according to claim 1, wherein the data processing device is converted. 3. The arithmetic processing means comprises an arithmetic circuit for executing sorting or relational algebraic arithmetic, and arithmetic control means for controlling the arithmetic operation by the arithmetic circuit, the arithmetic control means comprising the arithmetic target file data. 3. The input data to the arithmetic circuit are selected by sequentially applying the plurality of selection conditions with respect to.
The described data processing device. 4. A host device, a secondary storage device in which file data to be operated are stored, and a path for directly accessing the secondary storage device, and the operation is performed in response to a request from the host device. A data processing device comprising: an arithmetic processing device that executes a predetermined arithmetic process on target file data, wherein the arithmetic processing device communicates with the host device, and communicates with the secondary storage device. Processor for executing data input / output, an arithmetic circuit for performing sorting or relational algebraic operation, a second processor for executing and controlling the arithmetic operation by the arithmetic circuit, and an operation target input by the first processor From the host device supplied via the first processor and an internal memory storing the file data of A third processor that controls the operation of the first and second processors based on the indication, wherein the third processor is a single composite that collects information for a plurality of commands issued from the host device. The command is interpreted, and the data input / output processing by the first processor and the second processing are performed according to the designation information of the computation target file, the designation information of the computation processing content and the output destination designation information of the computation result included in the composite command. A data processing device, which is configured to control an arithmetic control process by the processor.