JPH0553335B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data transmission method comprising a transmission path for transmitting information and a plurality of data transmission devices connected to the transmission path for exchanging the information. Regarding downloading of software.

[Conventional technology]

Conventionally, in this type of data transmission system, when loading firmware, each data transmission device generally uses a proprietary disk device, cassette magnetic tape device, magnetic tape device, etc. connected to its own device. A method is adopted in which the firmware is directly loaded into the read/write storage section.

[Problem that the invention seeks to solve]

In the above-mentioned method, a device dedicated to boot loading must be connected to each data transmission device, which causes an increase in price. Furthermore, if the firmware is changed, it is necessary to change the bootload dedicated device connected to all data transmission devices, which causes many operational problems and requires a large amount of man-hours. .

In another method, the sending side (host computer side) prepares a program (predetermined for each terminal) to be loaded for each terminal in advance, and loads the program into each terminal at startup (special (Refer to Publication No. 121536/1983), but with this method,
The more complex the configuration on the terminal side, the more difficult it is to manage everything on the loading device, which is a drawback. That is, since the loading device manages the loading of programs for each terminal, as the number of types of programs increases, the number of combinations of programs increases, and the number of types of programs to be prepared for each terminal increases. In particular, when the loading device (terminal) requires a configuration change, not only the terminal side but also the information in the loading device (which is generally the master of the entire system) is also changed. Therefore, the entire system must be stopped or changes must be made to prevent operational errors, which has the disadvantage that the operation is complicated and there are many operational problems.

[Means for solving problems]

The present invention eliminates the above-mentioned drawbacks, and provides a transmission system that includes a transmission path for transmitting information and a plurality of data transmission devices connected to this transmission path for sending and receiving the information. , first status information indicating whether or not all the firmware or software required for each data transmission device is loaded; and second status information indicating the type of the firmware or the software that has not been updated, and one of the plurality of data transmission devices transmits the data at predetermined intervals. the first and second data transmission devices of another data transmission device via a
means for accessing status information of the second data transmission device, wherein the first status information indicates that all firmware or software is not loaded;
This data transmission method is characterized by comprising means for loading the firmware or the software corresponding to the type of the firmware or the software indicated by the status information.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 2 is a diagram showing an example of a data transmission method to which the present invention is applied. In FIG. 2, 1 to 4 are data transmission devices, and 11 to 14 are loop-shaped transmission lines between the data transmission devices 1 to 4. The data transmission system is comprised of a plurality of data transmission devices 1-4 and loop-shaped transmission lines 11-14.

FIG. 1 is a block diagram showing one embodiment of the present invention.

In FIG. 1, the same reference numerals as in FIG. 2 indicate corresponding parts. The data transmission device 1 includes a transmission path control circuit 21, a processor 22 that controls the transmission path control circuit 21 and sends and receives various information (controls firmware), a ROM unit 27 that stores the firmware, and a ROM. an address line 81 indicating an address for accessing the section 27;
It has a data line 82 for reading firmware from the ROM section 27. Furthermore, the data transmission device 1
has a data bus 51, a signal line group 52 for transmitting control signals for controlling the transmission line control circuit 21, and an interrupt line 53 for transmitting interrupt signals to the processor 22. The data transmission device 1 also includes a firmware storage section (i.e., a read/write control section) into which firmware necessary for the data transmission device is written.
23, a signal line group 61 for control signals and address signals for accessing the firmware storage section 23, a data bus 71 connecting the firmware storage section 23 and the processor 22, state information of the firmware of the data transmission device itself; It has a control storage section 24 for storing therein, and a signal line group 62 for control signals and address signals for accessing the control storage section 24. In addition, data transmission device 1
For time monitoring, timer 25, timer 25
A group of control lines 54 for controlling the processor 22 from the timer 25, an interrupt line 55 for indicating an interrupt, an I/O port 26 for controlling other devices other than the loop-shaped transmission line, A control line group 56 for access, an interrupt line 57 indicating an interrupt from the I/O port 26 to the processor 22, and an I/O port 2
6 and an interface line 15 indicating an interface with other devices.

Note that each of the data transmission devices 12, 13, and 14 also has substantially the same circuit configuration as the data transmission device 1 of FIG.

FIG. 3 is a block diagram showing an example of a configuration in which a portion related to the transmission line control circuit 21 in the embodiment of FIG. 1 is extracted.

In FIG. 3, the same reference numerals as in FIGS. 1 and 2 indicate corresponding parts. Transmission line control circuit 21
is a frame detection circuit 3 that detects frames.
1. A frame receiving circuit 32 that receives frames based on a frame reception instruction signal 41 generated from a frame detection circuit 31 and an FCSOK signal 42 that reports the validity of frame reception; a frame transmitting circuit 33 that transmits frames; The reception circuit 32 includes a data line 43 for passing frames unless the frame is addressed to itself.

FIG. 4 is an explanatory diagram showing a general frame format applied to the present invention.

A typical frame flowing through transmission lines 11 to 14 (see Figure 2) has a flag pattern F indicating "01111110" and a destination address indicating the destination address.
DA, source address indicating the address of the source
It consists of SA, control information C, data information I, and a check bit FCS that performs a cyclic redundancy check using a frame check sequence. Note that the data information I may be omitted as part of the frame structure.

FIG. 5 shows the format of the firmware status information written in the control storage section 24 of FIG.
FIG.

Q, R, S and T indicate the type of firmware, and when P=0 and at least one of Q, R, S and T has a value of 1, it is necessary to load the firmware, Q at P=1,
When at least one of R, S, and T has a value of 1, it indicates that the firmware is stored in the firmware storage section 23 of FIG. 1.

Next, the operation of the embodiment shown in Fig. 1 is explained in Figs. 2 and 3.
This will be explained with reference to FIGS. 4 and 5.

Suppose now that data transmission device 1 checks the status of data transmission devices 2 to 4 at regular time intervals.

In the data transmission device 1, the processor 22 connects the ROM 2 through an address line 81 and a data line 82.
I am running the basic firmware stored in 7. Initially, the processor 22 sets m (m is an arbitrary value) to the timer 25 through the control line group 54 and the data bus 51 and starts the timer 25.
After "m×n" (n is an arbitrary value in the counting cycle) time, an interrupt occurs to the processor 22 through the interrupt line 55. This interrupt causes the processor 22 to write into the transmission buffer in the frame transmission circuit 33 through the control line group 52 and the data bus 51 in the format shown in FIG. The control information C at this time is a command to read firmware status information from the control storage unit 24 (hereinafter referred to as read command frame A), and the destination address DA is the data transmission device 2,
The source address SA is the data transmission device 1.
Next, when the processor 22 activates transmission through the control line group 52, the frame transmission circuit 33 outputs the frame to the transmission line 11. Eventually, the frame detection circuit 31 of the data transmission device 2 detects that the frame coming in from the transmission path 11 is addressed to its own station, and the frame reception instruction 41 activates the frame reception circuit 32, and the frame reception circuit 32 starts receiving the frame. Write to Batshua. The frame receiving circuit 32 receives the FCSOK signal 42
Even if the data enters the reception buffer normally due to the output of the data, an interrupt is generated to the processor 22 of the data transmission device 2 through the interrupt line 53. When the processor 22 reads the reception buffer in the frame reception circuit 32 by an interrupt, it finds that it is a read command frame A, and writes it to the transmission buffer in the frame transmission circuit 33 in the format according to FIG. The control information C at this time is a response command for reading from the control storage unit 24 (hereinafter referred to as response command frame A), the destination address DA is the address of the data transmission device 1, and the source address SA is the data transmission device Address No. 2 and data information I are firmware status information read from the control storage unit 24 by the processor 22 through the signal line group 62 and the data bus 51, and the value of P shown in FIG. 5 is 0 and the value of Q is 1. , R, S, and T indicate 0. Further, the processor 22 in the data transmission device 2 activates the frame transmission circuit 33 through the control line group 52 and sends the frame to the transmission line 12. Data transmission device 1
The response command frame A addressed to data transmission device 1
The data is written into the reception buffer in the frame reception circuit 32 of the frame reception circuit 32, and is notified to the processor 22 of the data transmission device 1 through the interrupt line 53. Therefore, the processor 22 in the data transmission device 1 is the frame receiving circuit 3.
By reading the reception buffer in the firmware storage section 23, it is found that the data transmission device 2 requests loading of the firmware Q, and the firmware Q already written in the firmware storage section 23 is transferred to the signal line 61. It is read out through the data bus 71 and written into the transmission buffer in the claim transmission circuit 33 according to the format shown in FIG. Control information C at this time
indicates the firmware load (hereinafter referred to as load command frame B), the destination address DA is the address of the data transmission device 2, the source address SA is the address of the data transmission device 1, and the data information I is the firmware Q. shows. Next, the processor 22 of the data transmission device 1 activates the frame transmission circuit 33 through the control line group 52, and
Send to 1. The load command frame B addressed to the data transmission device 2 is written to the reception buffer in the frame reception circuit 32 of the data transmission device 2, and is notified to the processor 22 of the data transmission device 2 through the interrupt line 53. Therefore, by reading the reception buffer in the frame reception circuit 32, the processor 22 of the data transmission device 2 learns that the firmware Q will be transferred, and reads the reception buffer in the frame reception circuit 32.
Control line group 52, data bus 51, signal line group 6
1. Store the firmware Q through the data bus 71. Thereafter, the processor 22 of the data transmission device 2 sets the value of P in the firmware status information in the control storage section 24 from 0 to 1.

On the other hand, after the data transmission device 1 sends the load command frame B to the data transmission device 2, the data transmission device 3 and the data transmission device 4 perform the same operations as the data transmission device 2.

In the above example, the contents of the response command frame A sent to the data transmission device 1 are such that the value of P is 1, the values of Q, R, and S are 0, and the values of Q, R, and S are 0, according to the format shown in FIG.
If the value of T is 1, when the data transmission device 1 receives the frame, the processor 22 in the data transmission device 1 reads the reception buffer in the frame reception circuit 32, so that the data transmission device 2 Since the value of is 1 and the value of T is 1, it can be seen that the firmware T has already been loaded and there is no request to load new firmware, so monitoring to the next data transmission device 3 is performed without doing anything. Go to action.

As described above, when the data transmission device 1 completes a series of operations from the data transmission device 2 to the data transmission device 4, the processor 22 in the data transmission device 1 transmits the data to the timer 25 through the control line group 54 and the data bus 51.
When m (m is an arbitrary value) is set for , and the timer 25 is started, an interrupt is generated to the processor 22 through the interrupt line 55 after "m x n" (n is an arbitrary value in the counting cycle) time. . The processor 22 of the data transmission device 1 performs monitoring by transmitting the read command frame A from the data transmission device 2 to the data transmission device 4 in the same manner as in the above example in response to an interrupt from the timer 25, and loads the firmware. Load command frame B is transferred if necessary. In this way, the data transmission device 1 monitors each data transmission device at regular intervals.

Next, an explanation will be given of the operation when access is made from another data transmission device when the required firmware has not yet been loaded into the data transmission device.

Data transmission device 4 is I/O of data transmission device 2
The data is transferred to the fourth port 26 to access the device connected through the interface 15.
When the data is transmitted according to the format shown in the figure, it is stored in the reception buffer in the frame reception circuit 32 of the data transmission device 2, and sent to the processor 22 via the interrupt line 53.
Generates an interrupt according to. Then, the processor 22 of the data transmission device 2 reads the contents of the reception buffer in the frame reception circuit 32 and performs I/O processing.
Knowing that data is to be sent to the device connected to the port 26, I went to read the firmware status information written in the control unit 24 and found that the value of P in the firmware status information was 0 and the value of Q was 0. Knowing that the firmware Q necessary for accessing the device connected to the I/O port 26 has not been loaded since the value is 1, the frame transmitting circuit 33 executes the process according to the firmware shown in FIG. Write to the sending buffer. Control information C at this time indicates that the necessary firmware has not been loaded (hereinafter referred to as command frame D).
The destination address DA is the address of the data transmission device 4, the source address SA is the address of the data transmission device 2, and the data information I is firmware status information (content read from the control storage unit 24 by the processor 22 in the data transmission device 2). ) is shown. Next, the processor 22 in the data transmission device 2 activates the frame sending circuit 33 through the control line group 52, and
Send to 2. The command frame D addressed to the data transmission device 4 is written to the reception buffer in the frame reception circuit 32 of the data transmission device 4, and is notified to the processor 22 of the data transmission device 4 through the interrupt line 53. Therefore, the processor 22 of the data transmission device 4
By reading the reception buffer in the frame reception circuit 32, the controller learns that the firmware Q has not been loaded into the data transmission device 2 yet. Therefore, the data transmission device 4 is connected to the I/O of the data transmission device 2.
The reason why the device connected to the O port 26 cannot be accessed can be found, and error handling can be handled efficiently and quickly. As an example of error handling in this case, the data transmission device 1 can notify the data transmission device 2 to load the firmware Q. In this case, the processor 22 of the data transmission device 4 writes into the transmission buffer in the frame transmission circuit 33 according to the format shown in FIG. The control information C at this time indicates a request to load firmware to a certain device according to the data information I (hereinafter referred to as command frame E), and the destination address DA is the address of the data transmission device 1.
The source address SA is the address of the data transmission device 4, and the data information I indicates the transmission status information in the format shown in FIG. In the format shown in Figure 6, the destination address is the address of the destination to load the firmware, and the firmware status information is the 5th address.
This is the format of the figure. Next, data transmission device 4
The processor 22 in the frame activates the frame sending circuit 33 through the control line group 52 and sends the frame to the transmission line 14. The command frame E addressed to the data transmission device 1 is written to the reception buffer in the frame reception circuit 32 of the data transmission device 1, and is notified to the processor 22 of the data transmission device 1 through the interrupt line 53. Therefore, by reading the reception buffer in the frame receiving circuit 32, the processor 22 of the data transmission device 1 knows that the firmware Q has not been loaded into the data transmission device 2 yet. Next, the processor 22 of the data transmission device 1 sends the load command frame B to the data transmission device 2. The method of generating and processing this load command frame B is exactly the same as the method of generating and processing the load command frame B when the data transmission device 1 monitors the data transmission device 2 shown in the previous example.

In the above explanation, the explanation was given under the condition that the firmware to be sent to another data transmission apparatus is already stored in the firmware storage unit 23 of the data transmission apparatus 1. To explain briefly using a diagram, when the data transmission device 1 is started up, the processor 22 of the data transmission device 1 accesses the I/O port 26 through the control line group 56 and the data bus 51, and then accesses the I/O port 26 through the interface 15. The firmware Q, R, S, and T are read by accessing the floppy disk device 5, and the firmware Q, R, S, and T are written into the firmware storage section 23 through the signal line group 61 and the data bus 71. It will be done. At this time, the values of P, Q, R, S, and T of the firmware status information are set to 1 and written into the control storage section 24. Therefore, when load command frame B is sent to each data transmission device, firmware Q,
This means that R, S and T have been written in the firmware storage section 23.

As described above, when transmitting the load command frame B from the data transmission device 1, the firmware was read from the firmware storage section 23, but by directly accessing the floppy disk device 5, the load command frame B may be generated.

In addition, a DIP switch (which can be manually set to a value of 0 or 1 for each bit) is provided inside the processor 22 to initialize the firmware status information written to the control storage unit 24 of each data transmission device.
This can be easily realized by reading the contents of the "DIP" switch only when the processor 22 is started up and writing it into the control storage section 24 as firmware status information.

If the data transmission device 1 as explained above is configured to monitor the information every predetermined time unit, it will not affect the order in which the transmission lines are started up, even if the data transmission device 1 is started up last. It is possible to reliably load the necessary firmware to each data transmission device.

In the above example, the case was explained using a data transmission device via a loop-shaped transmission path.
The present invention is not limited to this, but for example, as shown in FIG.
As shown in FIG.
A method for data transmission device 111 to transmit information to data transmission device 112 via transmission path 611;
As shown in FIG.
(The processing of the data transmission device in the middle of command transfer is the same as the above example except for the processing of converting the command), but all of these are included in the present invention. .

Note that 113 and 114 in FIG. 9 above each indicate a data transmission device, and 121 to 12 in FIG.
8, 713, and 722-723 indicate data transmission devices, respectively.

Further, in the above description, loading of firmware was specified, but needless to say, loading of software is also included in the scope of the present invention, just by changing the terminology.

〔Effect of the invention〕

As explained above, the present invention provides status information that allows it to be determined whether or not the necessary firmware (or software) is loaded on each data transmission device, and allows information on other data transmission devices to be obtained from a specific data transmission device in advance. By reading the data at set intervals and loading the necessary firmware (or software) if it is not loaded, there is no need to connect a dedicated bootload device, except for specific data transmission. ,
This has the advantage that necessary firmware (or software) can be reliably loaded even when starting up a data transmission device during operation.

Furthermore, in the present invention, one of the data transmission devices is
By reading the first and second status information of other data transmission devices, the content of the firmware or software to be loaded for each other data transmission device can be classified, and which firmware or software should be loaded for each data transmission device. Management is easy because it is possible to identify whether to load each time. In particular, when changing the configuration of the data transmission device on the loaded side, the type of firmware or software can be changed by the data transmission device on the loaded side without system down. The effect is that you only need to pay attention to the transmission device, and the work is more efficient.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention;
FIG. 2 is a block diagram showing an example of a data transmission system to which the present invention is applied, FIG. 3 is a block diagram showing an example of a configuration in which the portion related to the transmission line control circuit of FIG. 1 is extracted, and FIG. FIG. 5 is an explanatory diagram showing the format of firmware status information; FIG. 6 is an explanatory diagram showing the format of transmission status information; FIG. 7 is an explanatory diagram showing the format of the transmission status information. FIG. 1 is a block diagram including devices connected to the I/O port, and FIGS. 8, 9, and 10 are block diagrams showing other examples of data transmission systems to which the present invention is applied. 1-5, 101, 102, 111-114, 1
21-127, 711-713, 721-723
...Data transmission device, 11-13,511,61
1... Transmission line, 21... Transmission line control circuit, 22...
...Processor, 23... Firmware storage section,
24... Control storage unit, 25... Timer, 26...
I/O port section, 27...ROM section, 31...Frame detection circuit, 32...Frame reception circuit, 3
3... Frame transmission circuit, 41-43... Signal line, 53, 55, 57... Interrupt line, 61, 61...
...Control and address lines, 51, 71...Data bus, 82...Data lines, 52, 54, 56...
Control line group, 81...address line, 15...interface.

Claims (1)

[Claims] 1. In a transmission system having a transmission path for transmitting information and a plurality of data transmission devices connected to this transmission path for exchanging the information, each data transmission device First status information indicating whether or not all firmware or software required for each data transmission device has been loaded; or second status information indicative of the type of the software, and one of the plurality of data transmission devices transmits the data to the other device via the transmission path at predetermined intervals. said first and said second data transmission device of
means for accessing status information of the second data transmission device, wherein the first status information indicates that all firmware or software is not loaded;
1. A data transmission system comprising means for loading said firmware or said software corresponding to the type of said firmware or said software indicated by the status information.