JPH05327777A - Synchronizing method for atm switch, and atm switch - Google Patents

Abstract

PURPOSE:To more exactly realize the synchronization between plural switch elements in the ATM of a parallel processing type. CONSTITUTION:A reset cell generating part 3 generates a reset cell by an input timing of a cell from an input highway 1-1. A cell separating part 4-1 divides the reset cell into M pieces of divided cells, and sends simultaneously each divided cell to switch elements 5-1-5-M. The switch elements 5-1-5-M detect the divided cell formed by dividing the reset cell, and initialize themselves by synchronizing therewith.

Description

Detailed Description of the Invention

[0001]

The present invention relates to an ATM (Asynchronous
Transfer Mode: See CCITT Recommendation I.361) Transmission equipment and ATM
The present invention relates to an ATM switch used in an exchange, and relates to a technique for synchronizing switch elements in a parallel processing type switch that divides cells transmitted by ATM and processes them in parallel.

[0002]

2. Description of the Related Art A switch for exchanging cells transmitted by ATM usually requires a high switching speed of several hundred Mbps or more.

In order to realize such a high-speed switching operation, the present applicants disclose a parallel processing type switch in Japanese Patent Application No. 2-215703 "ATM switch and its control method".

According to this technique, a cell is divided into a plurality of blocks, and each divided cell is input to a plurality of switch elements installed in parallel. Each switch element simultaneously performs the same operation to perform a switching process on the divided cells. After the switching process is completed, each switch element simultaneously outputs the divided cells and restores the original cell, thereby realizing high-speed cell switching.

[0005]

By the way, in order to increase the speed of the parallel processing type switch according to the technique of Japanese Patent Application No. 2-215703, it is necessary to synchronize the switching elements more accurately. Is required.

Therefore, according to the present invention, a parallel processing type A capable of more accurately synchronizing the switch elements is used.
The purpose is to provide a TM switch.

[0007]

[Means for Solving the Problems] To achieve the above object,
According to the present invention, an ATM cell input from the input highway is M
Cells (M is a natural number of 2 or more), and the divided M blocks are output in parallel. A cell division unit provided for each input highway and M cells output in parallel by the cell division unit are provided. Input each block and switch the input block synchronously with other switch elements M
Switch elements and M switch elements combine the M blocks that were simultaneously switched to output in the output highway direction corresponding to themselves, restore them into cells, and output the restored cells to the corresponding output highways. In an ATM switch having a cell coupling unit provided for each output highway, an ATM cell storing control information for instructing initialization of the switch element is generated before starting processing, and any input highway is generated. And outputs to each of the switch elements, detects whether or not the input block is a block obtained by dividing the ATM cell storing the control information, and detects the A storing the control information.
A method for synchronizing an ATM switch, characterized in that, when a block obtained by dividing a TM cell is detected, the self-switch element is set to an initial state to realize the subsequent synchronous operation of the M switch elements. provide.

In order to achieve the above object, the present invention provides
M ATM cells (M is 2
The above-mentioned natural number) is divided into blocks, and the divided M blocks are output in parallel. The cell division unit provided for each input highway and the M blocks output in parallel by the cell division units are input. Then, the M switch elements that switch the input block in synchronization with other switch elements, and the M switch elements are
A cell coupling unit provided for each output highway, which combines the M blocks simultaneously switched to output to the output highway corresponding to itself and restores the cells, and outputs the restored cells to the corresponding output highway. An ATM switch having the reset cell generating means for generating an ATM cell storing control information for instructing initialization of the switch element and outputting the ATM cell to any of the input highways, and each switch element Reset cell detecting means for detecting whether the input block is a block obtained by dividing the ATM cell storing the control information,
ATM in which the reset cell detecting means stores the control information
There is provided an ATM switch having an initialization means for setting its own switch element to an initial state when a block obtained by dividing a cell is detected.

[0009]

According to the ATM switch of the present invention, the reset cell generating means generates the ATM cell storing the control information for instructing the initialization of the switch element and outputs the ATM cell to one of the input highways. When an ATM cell storing the control information is input from the input highway, the cell division unit inputs M cells (M cells) in the same manner as a normal ATM cell.
Is a natural number of 2 or more) and outputs the divided M blocks in parallel. The initialization means of each switch element sets its own switch element to the initial state when detecting a block into which the ATM cell storing the control information is divided.

That is, an ATM cell storing control information for instructing the initialization of the switch element is flown into the same path as the actual cell path, and each switch element detects this and initializes each switch element. Since this is done, the synchronization operation between the switch elements can be performed accurately. Also, it is not necessary to provide special wiring for initialization and synchronization between switch elements.

[0011]

Embodiments of the ATM switch according to the present invention will be described below.

FIG. 1 shows the structure of an ATM switch according to this embodiment.

As shown in the figure, the ATM switch according to this embodiment is a parallel processing type ATM switch, and has N input highways 1-1 to 1-N and an output highway 2-.
It is an ATM switch for exchanging cells between 1 and 2-M.

In the figure, 5-1 to 5-M are M switch elements arranged in parallel, 3 is a reset cell generator for generating a reset cell, and 4-1 to 4-M are output highways. Cell division units 6-1 to 6-N are cell coupling units, and 7-1 to 7-N are address inspection units provided corresponding to the cell coupling units.

Further, cells are input from each of the input highways 1-1 to 1-N at the same timing. Further, a cell top signal, which is a pulse signal at the same timing as the timing at which the head of the cell is input, is input to the reset cell generation unit 3 and each of the cell division units 4-1 to 4-N. ..

The cell division units 4-1 to 4-M divide the cells and add routing information to the divided cells. The switching elements 5-1 to 5-M perform switching processing of divided cells. The cell combining units 6-1 to 6-N combine divided cells. Address inspection unit 7-1 to 7-N
Checks whether the address values added to the divided cells match. The reset cell generator 3 generates a reset cell that initializes the switch elements 5-1 to 5-M.

The cells input from each input highway are divided into M blocks (hereinafter, referred to as "divided cells"), respectively, before being switched.
-Split at N. The cell division units 4-1 to 4-N perform processing in synchronization with the cell top signal. Further, the cell division units 4-1 to 4-N add routing information necessary for switching in the switching element to each divided cell according to the content of the header of the cell.

FIG. 2 shows an example of this routing information.

As shown in the figure, each cell division unit divides the cell 200 input from the corresponding input highway into M division cells of the same size 230-1 to 230-M, and divides them. Header 210 of previous cell 200
According to the contents of each of the divided cells 230-1 to 230-M
The routing information 240-1 to 240-M that specifies which output highway the cell should be output to.
Is added.

The divided cells to which the routing information is added by each of the cell division units 4-1 to 4-N are bit rates synchronized with the divided cell clock of a rate lower than the input bit rate of the cell. It is converted and sent to the switch elements 5-1 to 5-M at the same time depending on the position on the cell. That is, the divided cell 230-k is sent to the switch element 5-k for processing. The output of the divided cells to the switch elements 5-1 to 5-N is performed in synchronization with the cell top signal. The cell top signal is supplied to each switch element 5-1 to 5- along with the divided cell clock.
Sent to M. The switching process in each of the switch elements 5-1 to 5-M is performed in parallel for each divided cell and in synchronization with the cell top signal and the divided cell clock.
Therefore, the cell switching process can be performed at a speed higher than the switching capability of each switch element.

Here, in FIG. 3, the switch element 5-
The structure of 1-5-M is shown.

Since the configuration of each switch element is the same, only the switch element 5-1 is shown.

As shown, the switch element 5-
Reference numeral 1 denotes an output buffer type switch, which is a multiplexer 10 that multiplexes divided cells input from an input port, and address filters 11-1 to 11-N that perform self-routing according to routing information added to the divided cells. , Buffers 12-1 to 12-N for storing divided cells, control units 13-1 to 13-N for controlling writing and reading of divided cells to and from the buffers 12-1 to 12-N, and cell combining unit It has an address adding unit for adding an address to the cells output to 6-1 to 6-N. Further, it has a reset cell detector 15 for detecting a reset cell described later.

The address filters 11-1 to 11-N are
Based on the routing information added to the divided cells to be input, the buffers 12-1 to 12- connected to the subsequent stage of itself
In N, it is determined whether to store the divided cell. Since the divided cells that have formed the same cell have the same routing information, each of the switch elements 5-1 to 5-1.
In 5-N, the data is written only in the buffer connected to the address addition unit connected to the same cell connection unit. Each of the control units 13-1 to 13-N specifies an address in the buffer and writes the divided cell sent from the connected address filter and reads the divided cell to the connected address addition unit.

The data read from the buffers 12-1 to 12-M is added with the addresses of the buffers written up to that point in the address adding units 14-1 to 14-M, and then the cell combining unit 6 is added. -1 to 6-N (see FIG. 1)
Is output to. This address is added to the part stored in the routing information. The cell combiners 6-1 to 6-N combine the cells divided by the cell combiners 6-1 to 6-N and output the corresponding output highway 2-.
Output to 1 to 2-N. However, each address checker
7-1 to 7-N monitor the address value added to the divided cells to be combined into the same cell, and if the mismatch is detected, consider that it is a malfunction of the switch. Corresponding cell combining units 6-1 to 6- so as to discard them without outputting them to the output highways 2-1 to 2-N.
Processing such as controlling N is performed. However, the malfunction may be determined when the mismatch is detected a predetermined number of times or more.

In the switch according to the present embodiment, the divided cells forming one cell are sent in parallel from the cell dividing section to the switch elements 5-1 to 5-M. In addition, each switch element needs to perform the same operation for each divided cell that constitutes the same cell. Therefore, it is necessary to synchronize the switch elements so that each switch element operates in synchronization.

Therefore, in this embodiment, a control cell having a role of initializing the switch element is defined in advance as a reset cell. And when the power is turned on,
When starting the switching operation, first, the reset cell is generated in the reset cell generator 3 (see FIG. 1) in synchronization with the cell top signal. The reset cell is M in the cell division unit 4-1 like a general cell.
It is divided into pieces and is input to each switch element. However, the cell division unit 4-1 writes the identification that the cell is a division cell constituting the reset cell in the routing information in the division cell obtained by dividing the reset cell,
Each is simultaneously sent to each switch element 5-1 to 5-M.

Then, each switch element 5-1 to 5
In M, the reset cell detection unit 15 detects the reset signal 2 when the divided cells forming the reset cell are detected.
3 is sent to each of the control units 13-1 to 13-N. Receiving the reset signal, each of the control units 13-1 to 13-N clears the buffer content and sets the content of the control unit to a predetermined initial state. That is, the control units 13-1 to 13-N
All the head values of the addresses for writing the divided cells in the corresponding buffers 12-1 to 12-N are set to predetermined values.

The reset operation timing in this switch element is shown in FIG.

In the figure, 400 is a divided cell clock, and 410
Is a cell top signal, 420 is a divided cell obtained by dividing the reset cell, 430 is a reset signal output from the reset cell detection unit 15, and 440 is a write address for writing the divided cell input by the control unit into the buffer.

As shown, the reset cell detector 15
Resets the reset signal when detecting a divided cell obtained by dividing the reset cell. On the other hand, each control unit that receives this waits for the next cell top signal to become significant,
The write address is set to a predetermined value. The above operation is performed by each switch element 5-1 to 5
-M, respectively. The write addresses set by the respective control units of the respective switch elements 5-1 to 5-M are all the same, and henceforth, the divided cells constituting the same cell will be changed to the respective switch elements 5-1 to 5-M.
In, the data will be written to the same address of the buffer, that is, each divided cell obtained by dividing the reset cell is
Since all the switch elements 5-1 to 5-M arrive at the same time, each switch element is simultaneously set to the initial state by the above operation. That is, all switch elements are synchronized.

As described above, after all the switch elements are synchronized, general cells can be processed in parallel. In addition, since all switch elements operate in the same way, a divided cell created by dividing an arbitrary cell is
The addresses stored in the buffer of each switch element match. Therefore, as described above, in the address adding units 14-1 to 14-N, all the address values added to the divided cells obtained by dividing the same cell are the same, and the address checking units 7-1 to 7-N make the same. The malfunction of the switch can be detected by monitoring the mismatch of the address values.

The malfunction of the switch may be detected as follows.

That is, when dividing a cell in each of the cell division units 4-1 to 4-N, the same number is added to all the divided cells forming the same cell, and the cells are sent to the switch element. This number is different for each cell. The number may be generated by incrementing a circulation counter having a predetermined bit width for each input cell. Further, this number may be stored in the routing information.
In the switch element module, this number is buffer-stored together with the divided cells, and when the divided cells are read out, this number is also read out at the same time, and the cell coupling units 6-1 to 7
-Transmit to N. In the cell combination unit, the numbers of all the divided cells are compared, and if they do not match, it is regarded as a malfunction and, for example, processing such as discarding this cell is performed. However, the malfunction may be determined when the non-one is detected a predetermined number of times or more.

In the above embodiment, the reset cell generating unit 3 generates a reset cell, and one cell division unit divides this and distributes it to each switch element. It is also possible to directly create a divided cell instructing each switch element to reset and distribute this to each switch element. Also,
In the above embodiment, the N input highways 1-1 to 1-
The ATM switch that exchanges cells between N and the output highways 2-1 to 2-M has been described as an example, but the number of input highways and the number of output highways may not be equal. Further, since each switch element is the same, it is preferable to configure each as one LSI and use a plurality of these.

By the way, when synchronizing each switch element by directly distributing one reset signal from the outside to the control section of each switch element, wiring to each switch element is required and each It is not always possible to accurately synchronize the switch elements due to differences in the delay amount of the wiring. However, as described above, according to this embodiment, in synchronization with the timing of the actual cell, the reset cell is poured into the same path as the path of the actual cell, this is detected, and the cell top signal is synchronized. Since each switch element is initialized, the initialization operation synchronized with the actual cell can be accurately performed in synchronization between the switch elements. In addition, wiring for resetting is not particularly required.

[0037]

As described above, according to the present invention, it is possible to provide a parallel processing type ATM switch in which the switch elements can be more accurately synchronized.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an ATM switch according to an embodiment of the present invention.

FIG. 2 is an explanatory diagram showing a divided cell that is a target of a switching process in the embodiment of the present invention.

FIG. 3 is a block diagram showing a configuration of a switch element according to an embodiment of the present invention.

FIG. 4 is a timing chart showing the operation of the ATM switch according to the embodiment of the present invention.

[Explanation of symbols]

 1-1, 1-2 to 1-N input highway 2-1, 2-2 to 2-N output highway 3 reset cell generation unit 4-1, 4-2 to 4-N cell division unit 5-1 and 5 -2-5-M switch element 6-1, 6-2-6-N cell coupling unit 7-1, 7-2-7-N address inspection unit 11-1, 11-2-11-N address filter 12 -1, 12-2 to 12-N buffer 13-1, 13-2 to 13-N control unit 14-1, 14-2 to 14-N address addition unit 15 reset cell detection unit 21-1, 21-2 ~ 21-N switch input port 22-1, 22-2 to 22-N switch output port 23 reset command 24-1, 24-2 to 22-N write address 25-1, 25-2 to 25-N read address

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Nobuhiro Ashi 216 Totsuka-cho, Totsuka-ku, Yokohama-shi, Kanagawa Hitachi, Ltd. Information & Communication Division (72) Inventor Takashi Nakajima 1-6, Uchiyuki-cho, Chiyoda-ku, Tokyo No. Japan Telegraph and Telephone Corporation

Claims (7)

[Claims] 1. ATM (Asyn) input from the input highway
chronous Transfer Mode: See CCITT Recommendation I.361) Dividing a cell into M (M is a natural number of 2 or more) blocks and outputting the divided M blocks in parallel. A cell division provided for each input highway. Section and the M number of blocks output by the cell division section in parallel, and the M number of switch elements that switch the input blocks in synchronization with other switch elements, and the M number of switch elements are themselves. A cell combining unit provided corresponding to each output highway for combining the M blocks switched to output in the output highway direction corresponding to the above to restore the cells to the corresponding output highway In an ATM switch having and, prior to the start of processing, an ATM cell storing control information for instructing initialization of the switch element is generated, Output to the input highways of Zureka, In each switch element, the input block detects whether blocks obtained by dividing the ATM cell storing the control information,
When a block obtained by dividing the ATM cell storing the control information is detected, the switch element is set to the initial state to realize the subsequent synchronous operation of the M switch elements. How to synchronize the switches. 2. ATM (Asyn input from the input highway
chronous Transfer Mode: See CCITT Recommendation I.361) Dividing a cell into M (M is a natural number of 2 or more) blocks and outputting the divided M blocks in parallel. A cell division provided for each input highway. Section and the M number of blocks output from the cell division section in parallel, and the M number of switch elements that switch the input blocks in synchronization with other switch elements; and the M number of switch elements, Cell combining provided for each output highway, combining M blocks that are simultaneously switched to output to the corresponding output highway, restoring the cells to the corresponding output highway, and outputting the restored cells to the corresponding output highway And an ATM cell storing control information for instructing initialization of the switch element. Reset cell generating means for outputting to a highway, and each of the switch elements, reset cell detecting means for detecting whether the input block is a block obtained by dividing the ATM cell storing the control information, and reset cell detecting means An ATM switch comprising: an initialization unit that sets its own switch element to an initial state when the unit detects a block obtained by dividing an ATM cell storing the control information. 3. The ATM switch according to claim 2, wherein the switch element includes a set of a buffer, an address filter, and a control means corresponding to each output highway, and each address filter is , It is determined whether the block input to the own switch element is a block to be output to the corresponding output highway, and the control means determines that the address filter in the set is a block to be output to the corresponding output highway. The blocks are sequentially written in the buffers in the set, the blocks stored in the buffers in the set are sequentially read according to the congestion status of the corresponding output highways, and are output in the corresponding output highway direction, and the initialization means When the reset cell detecting means detects a block into which the ATM cell storing the control information is divided, An ATM switch characterized by initializing the contents of each set of buffers and the write address of the buffer of the control unit. 4. The ATM switch according to claim 3, further comprising an address inspection unit for detecting a malfunction of the ATM switch for each output highway, wherein the switch element reads from a buffer and outputs in the output highway direction. The output block is provided with address adding means for adding information for specifying an address stored in the buffer, and the address checking unit is provided with the M number of M cells connected by the cell combining unit corresponding to the corresponding output highway. If all the addresses indicated by the information added to the block do not match, A
AT characterized by detecting malfunction of TM switch
M switch. 5. The ATM switch according to claim 3, further comprising an address checker for detecting malfunction of the ATM switch for each output highway, wherein the switch element reads from the buffer and outputs in the output highway direction. A block for outputting to a block is provided with address adding means for adding information for specifying an address stored in the buffer, and the address checking unit is provided with M number of cells to be connected by a cell combining unit corresponding to a corresponding output highway. ATM switch characterized by determining whether all of the addresses indicated by the information added to the block match, and detecting a malfunction of the ATM switch when a mismatch is detected a predetermined number of times. 6. The ATM switch according to claim 2, further comprising an address inspection unit for detecting a malfunction of the ATM switch for each output highway, wherein the cell division unit divides the cells into M blocks. To
Information that can identify the cell that the block is configured to is added to, and the address checking unit identifies the cells indicated by the information that is added to the M blocks to which the cell combining unit corresponding to the corresponding output highway is connected. ATM if all do not match
An ATM switch characterized by detecting a malfunction of the switch. 7. An ATM (Asyn input from the input highway
chronous Transfer Mode: See CCITT Recommendation I.361) Dividing a cell into M blocks (M is a natural number of 2 or more) and outputting the divided M blocks in parallel. Unit and each of the M blocks output in parallel by the cell division unit, and M switch elements that switch the input blocks in synchronization with other switch elements, and the M switch elements are , A cell combining unit provided for each output highway, which combines M blocks that are simultaneously switched to output to the output highway corresponding to itself and restores the cells, and outputs the restored cells to the corresponding output highways. An ATM switch having a plurality of cells, wherein each cell division unit divides the cell in which control information for instructing initialization of the switch element is stored. A block having the same format as the lock is generated and simultaneously output to all the switch elements, each switch element is a reset cell detection means for detecting whether the input block is a block storing the control information, An ATM switch comprising: a reset cell detection means, and an initialization means for setting an own switch element to an initial state when a block obtained by dividing the ATM cell storing the control information is detected.