JP2001024702A - Packet multiplexer and multiplexing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a circuit scale, to facilitate packet transfer of switching and to improve packet transfer efficiency of switching by interrupting the transmission of preceding packets and making a following packet interrupt between the preceding packets, so as to execute packet multiplexing. SOLUTION: When a bus is being used, a priority bit is stored in a priority comparing part 113 to decide priority order. When the priority of a following packet is low, transmission is not started until an EOP0 signal 101-4 is disabled, and packet transfer is started after a preceding packet finishes transmission. When the priority of the following packet is high, the transmission of the preceding packet is interrupted, and the following packet is made to interrupt between the preceding packets to transmit. An output control part 114 temporarily disables one output of the FIFOs of the preceding packets and sets enable one output of the FIFO of the following packets.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a packet multiplexing apparatus and a multiplexing method, and particularly to a LAN (Local Area).
The present invention relates to a packet multiplexing apparatus and a multiplexing method for multiplexing variable-length packets in a switching technology for realizing a network switch.

[0002]

2. Description of the Related Art A LAN switch is provided for interconnecting a plurality of LAN segments. The speed of the network in the LAN is increasing, and the backbone of the network and the server with a high load are fast Ethernet (100 Mbps) or Gigabit Ethernet (1G).
bps). At the same time, MAC (Media Access C)
control: Layer 2) switch or IP (Inter)
net Protocol: Layer 3) switch was developed and ATM (Asynchronous Trans)
fer Mode (FR) technology and FR (Frame Rela)
y) It has become possible to realize a high-speed network without using technology.

[0003] In a network using IP for Layer 3, since a packet is variable in length, even if a short packet arrives during transmission of a long packet, the packet is short until transmission of the packet being transmitted is completed. Have to wait.

On the other hand, a prior art switching technique of priority control used in a LAN (hereinafter referred to as prior art 1) will be described with reference to FIG. FIG. 12 is a configuration diagram of an example of a conventional LAN switch. Referring to FIG. 1, a conventional LAN switch includes, for example, two line accommodation units 3.
00 and an upper switch unit 310. Each line accommodating unit 300 includes an internal switch 301, a repacketizing unit 302, and a packet multiplexing unit 303. The packet data from the LAN line is switched by the internal switch 301 and transferred to each port or the upper switch unit 310. The packet data transferred to the upper switch unit 310 is divided into small fixed-length cell units by applying the ATM technology in the repacketizing unit 302 and simple packet multiplexing is performed in the packet multiplexing unit 303. ing. Thus, when a short packet arrives during transmission of a long packet cell group, packet multiplexing for performing priority control can be performed by inserting a short packet cell group between the transmission packet cells. .
Another example of a technique for performing priority control by dividing this type of packet is also disclosed in Japanese Patent Application Laid-Open No. H10-190938 (hereinafter referred to as Prior Art 2). That is, priority processing is performed after a packet is decomposed into segments including both a segment number and a packet number.

[0005]

However, in the above-mentioned conventional switching technologies (prior arts 1 and 2),
There are the following problems in performing the original repacketization of the application of the ATM technology. The first problem is that the circuit scale tends to be large. The reason is that in order to convert an IP packet to another packet, a re-packetizing circuit is required. The second problem is that the switching processing time increases. The reason is that it takes time to re-divide or reassemble the packet. A third problem is that the transmission efficiency of switching is reduced. The reason is that a header is required for each of the subdivided cells, and that padding for making the subdivided cells have a fixed length is required.

SUMMARY OF THE INVENTION An object of the present invention is to provide a packet multiplexing apparatus and a multiplexing method capable of reducing the circuit scale, speeding up the switching packet transfer, and improving the switching packet transfer efficiency. is there.

[0007]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention provides priority comparing means for comparing the priorities of packets, and interrupts the transmission of the preceding packet based on the result of comparison by the priority comparing means. The packet multiplexing apparatus is characterized by comprising a multiplexing means for interrupting a succeeding packet between the preceding packets.

Another invention according to the present invention provides a priority comparing step of comparing the priorities of packets, and interrupting the transmission of the preceding packet based on a result of the comparison in the priority comparing step. And a multiplexing step of interrupting a subsequent packet into the packet multiplexing method.

According to the present invention and another invention according to the present invention, packet multiplexing is performed by interrupting transmission of a preceding packet and interrupting a succeeding packet between the preceding packets, instead of converting the preceding packet. With this configuration, it is possible to reduce the circuit scale, speed up the switching packet transfer, and improve the switching packet transfer efficiency.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First, an outline of the present invention will be described. A packet multiplexing apparatus and a multiplexing method according to the present invention include:
Means for temporarily suspending transmission of a packet being transferred and transferring a high-priority packet first when a packet having a higher priority than a packet being transferred arrives during packet transfer without converting an IP packet. (See FIG. 1). Specifically, it has two FIFOs (First InFirst Out) for normal packet reception and high-priority packet reception, and has means for performing read control on the packet transmission side and write control on the reception side.

The present invention has two FIFOs for normal packet reception and high-priority packet reception, and performs read control on the packet transmission side and write control on the reception side, so that high-priority packets are transferred during packet transfer. To multiplex packets. Therefore, packet multiplexing for priority control can be performed without converting an IP packet to another packet. Further, in the present invention, since the transfer is performed as it is with the IP packet, a function for packet conversion is not required. Therefore, it is possible to reduce the circuit scale and the processing time of the packet conversion.

Further, according to the present invention, two FIs are provided on the receiving side.
It has an FO, and stores high-priority packets and low-priority packets in separate FIFOs. Therefore, even if a packet being transmitted is divided, it is not necessary to add a header and to add padding. For this reason, transfer efficiency can be improved.

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. FIG. 1 is a configuration diagram of a packet multiplexing apparatus according to a preferred embodiment of the present invention. Referring to FIG. 1, the packet multiplexing apparatus includes a plurality of line accommodation units 10.
0 and the upper switch unit 200. In the figure, a line accommodating unit 100 is a LAN line 10B.
base-T or 100Base-Tx accommodates n (n is a positive integer) lines, and determines whether the packet data from the LAN line is a port accommodated in the same internal switch or a port accommodated in another switch. A destination port discriminating unit that allows the packet to pass through to the internal switch 104 if it is destined for a port accommodated in the internal switch, and passes the packet data if it is destined to a port accommodated in another switch to the LAN line. And a transmission unit 1 that receives packet data destined for a port accommodated in another switch from the destination determination unit 103, performs priority control, and transmits the packet data to the upper-level switch unit 200
01, a receiving unit 102 for receiving packet data from the upper switch unit 200, and an internal switch 104.

The upper switch unit 200 includes the line accommodating unit 10.
0, which receives the multiplexed packet data from 0 and simultaneously transfers the packet data based on the transfer destination information received from the line accommodating unit 100, and the packet transferred from the upper receiving unit 201. And an upper transmission unit 202 for transmitting data to the line accommodating unit 100.

The present invention is based on the line accommodating unit 100 shown in FIG.
FIG. 2 shows a detailed configuration of the present invention relating to packet multiplexing between the host and the upper switch unit 200. FIG. 2 is a configuration diagram of a line accommodating unit and a higher-order receiving unit of the packet multiplexing apparatus according to the present invention. Referring to FIG. 2, destination port determination unit 10
Reference numeral 3 denotes a plurality of packet selectors 130 each accommodating each of the LAN lines 100-1 to 100-n.

The packet selector 130 includes a packet header information signal 103-1 and a packet arrival signal 103-2 to 103-5 destined for a port accommodated in another switch.
And packet data signals 103-6 to 103-9 destined for ports accommodated in another switch, and the internal switch 10
Packet data transmission / reception signals 103-10 to 103-3
-13 is connected.

The transmitting unit 101 is provided with a destination port determining unit 10
3, storage units 120 to 12n for temporarily storing packets destined for ports accommodated in another switch, priority control of packets and output control of storage units 120 to 12n,
The transmission control unit 110 exchanges transfer information with the upper-level switch unit 200. The transmission control unit 110
A packet header information signal 103-1 and a packet arrival signal 103-2 destined for a port accommodated in another switch
To 103-5, output control signals 110-1 to 110-4 of the storage units 120 to 12n, transfer information signals 101-2 and 101-3 to the upper switch unit 200, and a transmission enable signal 101 of the transfer information signal. -1, the normal packet transmission enable signal 101-4, and the high priority packet transmission enable signal 101-5 are connected. Storage unit 120-
12n are output control signals 110-1 to 110-, respectively.
4, a packet data signal 103-6 to 103-9 destined for a port accommodated in another switch, and a packet output signal 101-6.

The receiving section 102 comprises a receiving storage section. The receiving storage unit 102 stores the packet data signal 102-1 from the upper switch unit 200 and the internal switch 10
4 to the packet transmission signal 109. The internal switch 104 includes packet data transmission / reception signals 103-10 to 103-13 from the destination port determination unit 103,
It is connected to a packet data reception signal from the reception unit 102.

The high-order receiving section 201 has storage sections 210 and 211 for temporarily storing normal packets and high-priority packets separately.
And the transfer information of the packet,
And a higher-level reception control unit 220 that performs write control and read control of 0 and 211. Storage units 210, 211
Are the packet output signal 101-6, the packet transfer signals 210-1, 211-1 and the write enable signal 22.
0-1, 220-2 and the read control enable signal 22
0-3 and 220-4 are connected.

The upper reception control unit 220
Transmission enable signal 101-1 of transfer information signal from 0
, Transfer information signals 101-2 and 101-3, a normal packet transmission enable signal 101-4, a high priority packet transmission enable signal 101-5, and storage units 210 and 21.
1 write enable signals 220-1 and 220-2
And read control enable signals 220-3 and 220-4.
Are connected.

The upper transmission unit 202 is provided with a reception storage unit 24.
0, 241, 242, and a higher-level transmission control unit 230 that controls transmission to the line accommodating unit 100. The reception storage units 240, 241, 242 store the packet data signals 201-1, 201-2, 20 from the upper reception unit 201.
1-3 and the packet data signals 240-1, 241-1 and 222-1 to the upper transmission control unit 230 are connected.

The upper transmission control unit 230 is provided with the reception storage unit 2
Packet data signal 240 from 40, 241, 242
-1,241-1,242-1 and the packet transmission data signal 102-1 to the line accommodating unit 100 are connected.

FIG. 3 is a configuration diagram of the destination port determining unit 103. Referring to FIG. 3, the destination determining unit 103 includes a plurality of packet selectors 130.
The header information of the packet is read from 0-n to determine whether the port is accommodated in the same internal switch or a port accommodated in another switch. Header information reading unit 131 having a function of notifying that packet data destined for a port accommodated in another switch has arrived, and outputting packet data to either the internal switch 104 or the upper switch unit 200 And a data selector 132 that performs the operations.

Referring further to FIG. 4, there is shown a block diagram of a transmission control unit 110 which performs priority control of packets and output control of the storage units 120 to 12n of the transmission unit 101.
The transmission control unit 110 stores the header information extracted by the destination determination unit 103 (DRAM: Direct)
Random Access Memory) 111
And job queue 1 for queuing the arrival of packets
12 and information necessary for priority control from the storage unit 111, and compares the priorities of subsequent packets with each other, and outputs a result to the output control unit 114.
ty) The comparison unit 113, the output control unit 114 that controls the output of the storage units 120 to 12n, and the information necessary for the upper-level switch unit 200 to perform data transfer.
And a selector 115 for enabling the data to be stored separately in 0 and 211.

FIG. 5 is a block diagram of the higher-level reception control section 220 in the higher-level reception section 201. Referring to FIG. 5, the upper reception control unit 220 includes the reception storage units 210, 2
11 includes a write control unit 221 and a data transfer information read control unit 222. The write control unit 221 is configured by a logic circuit. The read control unit 222 includes storage units 223 and 224 for temporarily storing data transfer information, and a job queue 225.

Next, IPv6 (I
internet Protocolversion
The operation of transmitting packet data from the line accommodating unit 100 to the upper-level switch unit 200 in the LAN using 6) will be described with reference to FIGS. 2, 3, and 4. LAN line 100
-1 to 100-n, the header information is read by the header information reading unit 131 connected to the data bus, and the packet data transferred to the same internal switch or the packet data transferred to another switch. The switching signal of the data selector 132 is switched. At the same time, if the arriving data is packet data to be transferred to another switch, the fact that the packet has arrived on the upper side is passed through 103-2 to 103-5, and the header information is transferred to the transmitting unit 101 through 103-1. I do.

In the data selector 132, the packet data transferred to the same switch is
The internal switch 10 is connected via the data bus 103-13.
4 is transferred. On the other hand, the packet data transferred to another switch is transferred to the transmission unit 101 via the data bus of 103-6 to 103-9. Internal switch 10
The packet switched in the same switch in step 4 is well known to those skilled in the art, and is not directly related to the present invention.

The packet data sent to the transmission unit 101 via any one of the data buses 103-6 to 103-9 is written to the FIFOs of 120 to 12n. The signal transmitted via the packet arrival signals 103-2 to 103-5 is transmitted to the job queue 1 of the transmission control 110.
It is queued at 12. At the same time, header information is written into the DRAM 111. For the read job, the use state of the data bus is determined based on the EOP signal 101-4 generated by the output control unit 114.

Next, the operation will be described separately for a case where the bus is not used, a case where the bus is used, and a case where the bus is full.
FIG. 6 is a flowchart showing the operation of the packet multiplexer.
FIG. 11 is a configuration diagram of the IPv6 header.

First, when the bus is not used, the priority comparison unit 113 stores the priority (Priority) bit 321 of the IPv6 header shown in FIG. 11, and the output control unit 114 sends the FIFO to which the data is to be transmitted.
Enable any one of the outputs 120 to 12n,
Enable the P0 signal 101-4, and
(Direct Memory Access) Enables a 101-1 signal notifying that information is being transferred. During the packet data transfer, information necessary for DMA of the destination port of this packet and the number of transfer bytes is 101-
2 to the upper switch unit 200. (FIG. 6
S1). When the transmission of the information necessary for the DMA is completed, the signal 101-1 is disabled. When the transfer of the packet data ends, the output control unit 114 disables any of the output signals of the enabled FIFOs 120 to 12n and the EOP0 signal 101-4 (see S2 in FIG. 6). FIG. 7 shows the timing of this packet transfer. That is, FIG. 7 shows how packet data is sent to the upper-level switch unit 200 via the FIFO 120.

Next, when the bus is in use, a priority bit is stored in the priority comparing section 113 (FIG. 6).
, And the priority is determined (see S4 in FIG. 6).
If the priority of the succeeding packet is low, the EOP0 signal 10
Wait for transmission until 1-4 becomes disabled (S in FIG. 6).
5), and the packet transfer starts after the preceding packet has finished transmitting (see S2 in FIG. 6). FIG. 8 shows the transfer timing of this packet. That is, FIG. 8 shows a state in which, when packet data arrives from the FIFO 121 during transmission of the packet data of the FIFO 120, the data of the FIFO 121 is transmitted after the transmission of the packet data of the FIFO 120 is completed. On the other hand, if the priority of the succeeding packet is high, the transmission of the preceding packet is interrupted, and the subsequent packet is interrupted and transmitted between the preceding packets (see S6 in FIG. 6). The output control unit 114 temporarily disables the output of any of the FIFOs 120 to 12n of the preceding packet, and
Enable any output of 2n. Also, the high-level switch unit 200 reports that high-priority packet data is being transmitted.
Enable the EOP1 signal 101-5. When the EOP1 signal 101-5 is enabled, the selector 115 automatically sets the write destination of information necessary for DMA from the FIFO 223 of the upper reception control unit 220 to the FI.
It switches to the FO 224 and sends out data on the bus of 101-3. When the transmission of the subsequent packet is completed, output control 1
14 is an EOP1 signal and a FIFO 120 of a subsequent packet.
12n is disabled (see S7 in FIG. 6), and the output of any of the FIFOs 120 to 12n of the preceding packet, which has been temporarily disabled, is enabled (see S2 in FIG. 6). FIG. 9 shows the timing of this packet transfer. That is, FIG. 9 shows that when packet data from the FIFO 121 arrives during transmission of the packet data of the FIFO 120, the transmission of the packet data of the FIFO 120 is interrupted, the packet data of the FIFO 121 is transmitted, and the transmission of the packet data is terminated. FIF again
The figure shows how packet data of O120 is transmitted.

It should be noted that the amount of data required for the DMA is small, and the transfer to the subsequent packet is not performed while the information required for the DMA of the preceding packet is being transferred due to the time required for the switching process of the subsequent packet. After the transfer of the subsequent packet is completed, if there is a job in the job queue 112, this operation is repeated again. Job processing is 2
When a third job exists as shown in the timing of FIG. 10, further when a high-priority packet is transferred, or when the second job has a low priority and the preceding packet is transmitted. If the job is waiting for termination, the next job is not executed.

In FIG. 10, the transmission of the packet data of the FIFO 120 is interrupted, the transmission of the packet data of the FIFO 121 is executed, and the transmission of the packet data of the FIFO 120 is restarted after the transmission of the packet data of the FIFO 121 is completed. The transmission of the packet data in the FIFO 120 is completed,
2 shows a state in which transmission of the second packet data is started.

FIG. 7 shows a case where the bus is not used, a case where the bus is used, and a case where the bus is full. This will be described below. There are two buses, a high-priority dedicated bus and a normal bus, and the first packet data uses the normal bus regardless of the priority. Next, the priority of the second packet data is compared with that of the first packet data. If the priority is higher than that of the first packet data, a high-priority dedicated bus is used (see S6 in FIG. 6).
However, if the priority is low, the process waits until the use of the normal bus ends (see S5 in FIG. 6). On the other hand, when the bus is full,
This means a case where both buses of the system are in use. In this case, the system waits until the use of the bus is completed (see S8 in FIG. 6).

Next, referring to FIG. 2 and FIG.
The reception control of the packet transmitted from to the upper switch unit 200 will be described. The packet transmitted via the data bus 101-6 is a normal reception packet FIFO 21
When the high-priority packet is received, the packet is stored in the reception packet FIFO 211. The data reception FIFOs 223 and 224 required for DMA are also stored separately for normal packets and high-priority packets. Also,
The writing control to the FIFO is performed by 101-1. The write control to the reception FIFOs 210 and 211 is performed by inputting the EOP0 signal 101-4 and the EOP1 signal 101-5 to the write control unit 221.
Generates write enable signals 220-1 and 220-2, and controls the FIFOs 210 and 211 with this. When the EOP0 signal 101-4 and the EOP1 signal 101-5 become disabled,
Information that determines the order of the FIFOs 210 and 211 for performing the DMA transfer process is queued in the job queue 225. FI according to the order stored in the job queue 225
Reads any one of FO 223 and 224 and receives FIFO
The DMA transfer of 210 and 221 is performed. Line accommodating unit 100
EOP0 when a high-priority packet is transferred from
Due to the operation of the signal and the EOP1 signal, the high priority packet is always stored in the JOB queue 225 first, so that the DMA processing is also performed first.

The packets transferred from the DMA transfer source 201 are FIFOs 240, 241, 24 prepared for respective ports in the port 202 for transferring data to the line accommodating section 100.
2 is stored. The upper transmission control unit 230 that performs transfer control to the line side transfers the packets to the line side via the data bus 102-1 in the order in which the packets are stored in the FIFOs 240, 241, and 242. The data stored in the line accommodating unit 100 is switched to each line using the same sequence as the packet data from the other same switch.

In the present embodiment, IPv6 (Internet Protocol v) is used for the layer 3 protocol.
LAN 6 that uses IPv4 (Internet version 6), but IPv4 (Internet)
In the LAN using the protocol version 4), the priority comparison unit 11 shown in FIG.
By preparing a table in which the priority of each destination port is associated with No. 3, the same effect can be obtained depending on the destination port number of the layer 4 header of the packet to be transmitted. Further, in the present embodiment, the case where the upper switch unit has four ports has been described (see FIG. 1), but the number of ports is not limited.

A first effect of the present invention is that packet multiplexing for priority control can be performed without converting an IP packet into another packet. The reason is that there are two types, one for normal packet reception and the other for high priority packet reception.
This is because the multiplexing of packets is performed by having one FIFO and performing read control on the packet transmission side and write control on the reception side to interrupt a high-priority packet during packet transfer.

The second effect is that the circuit size of the LAN switch can be reduced and the processing time can be reduced. This is because IP packets are transferred as they are, no packet conversion circuit is required, and packet disassembly and assembly processing is unnecessary.

The third effect is that the transfer efficiency of LAN switching can be improved. The reason is that header and padding are not required because repacket conversion is not performed.

[0041]

According to the present invention, the priority comparing means for comparing the priorities of the packets, the transmission of the preceding packet is interrupted based on the comparison result by the priority comparing means, and the succeeding packet is interrupted between the preceding packets. Since the packet multiplexing device includes the multiplexing means for interrupting the packet, it is possible to reduce the circuit scale, speed up the switching packet transfer, and improve the switching packet transfer efficiency.

According to another aspect of the present invention, a priority comparing step of comparing the priorities of the packets, and the transmission of the preceding packet is interrupted based on a result of the comparison in the priority comparing step. Since the packet multiplexing method is configured to include a multiplexing step of interrupting a subsequent packet between the above steps, the same effects as those of the present invention described above can be obtained.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a packet multiplexing apparatus according to a preferred embodiment of the present invention.

FIG. 2 is a configuration diagram of a line accommodating unit and a higher-order receiving unit of the packet multiplexing apparatus according to the present invention.

FIG. 3 is a configuration diagram of a destination port determination unit 103.

FIG. 4 is a configuration diagram of a transmission control unit 110.

FIG. 5 is a configuration diagram of an upper reception control unit 220;

FIG. 6 is a flowchart showing an operation of the packet multiplexing device.

FIG. 7 is a timing chart showing the operation of the packet multiplexing device.

FIG. 8 is a timing chart showing the operation of the packet multiplexer.

FIG. 9 is a timing chart showing the operation of the packet multiplexer.

FIG. 10 is a timing chart showing the operation of the packet multiplexing device.

FIG. 11 is a configuration diagram of an IPv6 header.

FIG. 12 is a configuration diagram of an example of a conventional LAN switch.

[Explanation of symbols]

 REFERENCE SIGNS LIST 100 Line accommodating unit 101 Transmitting unit 102 Receiving unit 103 Destination port determining unit 104 Internal switch 200 Upper switch unit 201 Upper receiving unit 202 Upper transmitting unit

Claims (16)

[Claims] 1. A priority comparing means for comparing the priorities of packets, and a multiplexing means for interrupting transmission of a preceding packet based on a result of the comparison by the priority comparing means and interrupting a succeeding packet between the preceding packets. And a packet multiplexing device. 2. The multiplexing means, if the priority comparing means determines that the priority of the subsequent packet is higher than that of the preceding packet, suspends transmission of the preceding packet, 2. The packet multiplexing apparatus according to claim 1, wherein the subsequent packet is interrupted during the period. 3. The storage device according to claim 1, further comprising storage means for separately storing a normal packet multiplexed by said multiplexing means and a high-priority packet having a higher priority than said normal packet. Packet multiplexer. 4. The packet multiplexing apparatus according to claim 3, wherein said storage means stores said normal packet and said high-priority packet separately based on a comparison result of said priority comparison means. 5. The storage means stores the packet determined to be a normal packet by the priority comparison means in a normal packet dedicated storage unit and stores the packet determined to be a high priority packet in a high priority dedicated storage unit. The packet multiplexing device according to claim 3 or 4, wherein 6. The packet multiplexing apparatus according to claim 3, wherein said packets are stored in said storage means in the order of arrival. 7. The packet multiplexing apparatus according to claim 1, wherein said packet is a variable length packet. 8. A LAN switch for accommodating a plurality of LAN lines and for switching a packet to a LAN other than the accommodated LAN line, wherein the multiplexing means multiplexes a packet to be switched to a LAN other than the LAN line. Item 1
8. The packet multiplexing device according to any one of claims 1 to 7. 9. A priority comparing step of comparing packet priorities, and a multiplexing step of interrupting transmission of a preceding packet based on a comparison result in the priority comparing step and interrupting a succeeding packet between the preceding packets. And a packet multiplexing method. 10. In the multiplexing step, when the priority comparing step determines that the succeeding packet has a higher priority than the preceding packet, transmission of the preceding packet is interrupted, and 10. The packet multiplexing method according to claim 9, wherein the subsequent packet is interrupted during the period. 11. The method according to claim 9, further comprising the step of separately storing the normal packet multiplexed in the multiplexing step and a high-priority packet having a higher priority than the normal packet. Packet multiplexing method. 12. The packet multiplexing method according to claim 11, wherein in said storing step, said normal packet and said high-priority packet are stored separately based on a comparison result by said priority comparing means. 13. In the storing step, a packet determined as a normal packet in the priority comparing step is stored in a normal packet dedicated storage unit, and a packet determined as a high priority packet is stored in a high priority dedicated storage unit. 13. The packet multiplexing method according to claim 11, wherein: 14. The packet multiplexing method according to claim 11, wherein said packets are stored in the order of arrival. 15. The packet multiplexing method according to claim 9, wherein said packet is a variable length packet. 16. A LAN switch for accommodating a plurality of LAN lines and for switching a packet to a LAN other than the accommodated LAN line, wherein a packet for switching to a LAN other than the LAN line is multiplexed in the multiplexing step. The packet multiplexing method according to any one of claims 9 to 15, wherein