JPS63287294A - Line packet composite switch system - Google Patents

Abstract

PURPOSE:To compensate instantly the increase/decrease in the capacity of a line exchange network by the increase/decrease in the capacity of a packet exchange network by providing separately a line exchange switch circuit network and a packet exchange switch circuit network so as to use a suitable switch circuit network. CONSTITUTION:A composite switch is constituted by separating a line slot and a packet slot by a separation circuit 3 through the use of a principle that the slot location in a synchronizing frame for line exchange is confirmed in advance, switching suitable switch networks 7, 8 to an output path 1-2 and inserting a packet slot to an idle slot between line slots. In inserting a packet slot to an idle slot of the line slot, it is possible to assign instantly the transmission capacity of packet exchange against the fluctuated line exchange traffic. Since the switch suited to each mode of line/packet is used, a large capacity of line packet composite switch network is realized simply.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a line/packet composite switching system, and in particular, the present invention relates to a line/packet composite switching system, and in particular, by configuring a transmission processing node switch that integrates a line switching network and a packet switching network, line switching The present invention relates to a switching system that allows an increase or decrease in the capacity of a network to be immediately compensated for by an increase or decrease in the capacity of a packet-switched network.

[Conventional technology]

BACKGROUND ART Conventionally, a method of constructing a packet switching network and a circuit switching network using the same transmission path has been known.

In the conventional method, a single circuit switching path and a packet switching path are fixedly set in a synchronous terminal equipment using a circuit-based switch. It was not possible to immediately allocate transmission capacity from packet-switched paths.

FIG. 2 is a block diagram of a conventional line/packet switching network coupling system.

As shown in Fig. 2, conventional synchronous terminal equipment with a switch for five circuits has a circuit switch C5 and a packet switch P.
A method of connecting S is used. In Figure 2, the circuit-switched switch of the synchronous terminal equipment sets a single circuit-switched path and a packet-switched path in the same transmission path in a semi-fixed manner using synchronous multiplexing, so the circuit-switched traffic is reduced. Even if the traffic of circuit switching increases, it is not possible to use a vacant path for packet switching, and even if the traffic of circuit switching decreases by 1, it is not possible for packet switching to utilize a vacant path for circuit switching. Ta.

[Problem that the invention seeks to solve]

In this way, in the conventional method, the circuit-switched network and the packet-switched network are integrated using a synchronous terminal station based on single-circuit switching technology, and it is difficult to deal with fluctuations in single-circuit switching traffic.
Since it was not possible to immediately allocate transmission capacity from packet-switched paths, it was necessary to anticipate fluctuations in the traffic ratio between circuit-switched and packet-switched traffic and set up paths with some margin for both circuits and packets, which resulted in lower transmission efficiency. It was declining.

On the other hand, a method is conceivable in which the path settings are changed by the control device of the synchronous end single station device shown in FIG. 2, but this requires major modification in both hardware and software. That is, the synchronous terminal control device is connected to the circuit switch CS and the packet switch PS, and the circuit switch C8 and the packet switch PS are connected to each other.
If the control device controls the path setting of the synchronous terminal device based on the traffic information obtained from the synchronous terminal device, and changes the path appropriately according to the traffic ratio, the path can be set efficiently.

However, there are problems in that it is troublesome to change the connection between the control device and each exchange, and the control from the control device is also complicated.

In addition, it is possible to use a packet/line hybrid switch to integrate two switching networks without using a synchronous terminal device, but there is no hybrid switch suitable for the one-car switching system, and a hybrid network is inevitably required. , the switch becomes a switch suitable for either packets or lines. There is a problem in that if a switch suitable for one is used, the throughput for the other will decrease.

The purpose of the present invention is to improve these problems, to be able to immediately compensate for increases and decreases in the capacity of circuit-switched networks by increases and decreases in the capacity of packet-switched networks, and to simplify control so as not to reduce transmission path usage efficiency. The purpose is to provide a combined line/packet switching system.

[Means for solving problems]

In order to achieve the above object, the line/packet composite switch system of the present invention includes a frame synchronization circuit that synchronizes the phase of bits, slots, and frames, and a separation circuit that is connected to the frame synchronization circuit and separates line slots and packet slots. a circuit, a circuit switching switch or switch network and a packet switch or switch network connected to the separation circuit, and a multiplexing circuit connected to the switch or switch network for multiplexing line slots and packet slots; The separating circuit separates a line slot whose use slot is determined in advance from among the time-division multiplexed signal slots, inputs it to the line switching switch or switch network, and inputs the line slot from the remaining slots to the line switching switch or switch network. A packet slot is extracted and inputted to the packet switch or switch network, and the line switching switch or switch network performs a switching operation of a single circuit switching network to insert a line slot into a predetermined slot of the desired output route. The packet switching switch or switch network performs the switching operation of the packet switching network and outputs the packet to the intended output route, and the multiplexing circuit outputs the packet from the circuit switching switch or switch network. The feature is that the packet slot outputted from the packet switching switch is inserted into a vacant slot of the outputted line slot, and the line slot and packet slot are time-division multiplexed.

[For production]

In the present invention, by utilizing the fact that the slot position in the synchronization frame for line switching is determined in advance, line slots and packet slots are separated, and a switch network suitable for each is used to connect the line slots to the intended output route. A composite switch is constructed by performing switching and inserting packet slots into empty slots between line slots. Then, by inserting a packet slot into an empty line slot, it becomes possible to immediately allocate the packet switching transmission capacity in response to fluctuations in the line switching traffic. Furthermore, since switches suitable for each line/packet mode are used, a large-capacity line/packet composite switch network can be easily realized.

〔Example〕

EMBODIMENT OF THE INVENTION Below, one embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 is an overall configuration diagram of a line/packet composite switch system showing a first embodiment of the present invention.

In Figure 1, 1-1 is an incoming transmission line or path;
2 is an output transmission line or path, 2 is a frame synchronization circuit, 3
is a line slot/packet slot separation circuit, 4-1 is an ingress line switching highway, 4-2 is an outgoing line switching highway, 5-1 is an incoming packet highway, 5-2 is an outgoing packet highway, and 6 is a line. A slot/packet slot multiplex circuit, 7 a line switching switch network, and 8 a packet switching switch network.

The signals transmitted in the input transmission line (or path) 1-1 and the output transmission line (or path) 1-2 are both synchronously multiplexed with circuit switching slots and packet switching slots.

First, the signals of the circuit switching slot and the packet switching slot inputted from the input transmission line (or path) 1-1 are synchronized in the frame synchronization circuit 2. Next, each synchronized signal is sent to the line slot/packet slot separation circuit 3, which outputs the slot assigned to line switching to the highway 4-1, extracts packets from other slots, and outputs the slot allocated to the line switching to the highway 4-1. Output to 5-1. The line switching switch network 7 exchanges signals between highways and within a synchronization frame, and outputs the signal to a target slot of a target highway. In addition, the packet switching switch network 8 is
A switch or switch network with a buffer to prevent packet collisions is used to output the packet to the intended highway. The line slot/packet slot multiplexing circuit 6 allows the line slot output from the highway 4-2 to pass through with priority, and inserts the packet signal of the highway 5-2 into an empty slot on the highway 4-2, thereby making the line packet Multiplex both signals.

As is clear from the above operation, when the traffic of one circuit switch decreases and the number of circuit switching slots in a synchronization frame decreases, the circuit slot/packet slot multiplexing circuit 6
The transmission capacity for packet switching can be increased by simple partial control in the line slot/packet slot multiplexing circuit 6, and conversely, when the number of slots for circuit switching increases, simple partial control in the line slot/packet slot multiplexing circuit 6 can increase the transmission capacity for packet switching. Transmission capacity for packet switching can be allocated to circuit switching.

3 to 7 are explanatory diagrams of a second embodiment of the present invention, in which FIG. 3 shows an input transmission line 1-1 and an output transmission line 1-1.
FIG. 2 is a diagram showing a frame configuration in No. 2. FIG.

In the second embodiment, as shown in FIG. 3, the frame structure is set to the size of one packet per slot using packets of a fixed length. A frame synchronization pattern F is added to the beginning of each frame. At this time, each slot in the frame becomes a line slot C, a packet slot P, and an empty slot E.

Further, within one slot, the header H is followed by the information processing. These slots are separated by the line slot/packet slot separation circuit 3 shown in FIG.

FIG. 4 is a detailed configuration diagram of the line slot/packet slot separation circuit in FIG. 1.

In FIG. 4, 91 is a switch of the separation circuit, 92 is a control memory, 93 is a gate, and 94 is an empty pattern detection circuit. The control memory 9 records the usage positions of line slots. By using the line slot usage positions recorded in the control memory 9, a switch is toggled to separate the line slot from other slots. The line slot is sent to highway 4-1, and the other slots (vacant slots and packet slots) are sent to highway 5-1. By putting a unique signal pattern different from the header of the packet slot in the empty slot, the empty slot and the packet slot can be identified by the empty pattern detection circuit 94.

By opening and closing the gate 93, only the packet slot is output to the highway 5-1, and the packet switch 8
Enter.

FIG. 6 is a diagram showing an example of the T-5-T switch used as the circuit switching switch in FIG.
The figure is a diagram showing an example of a packet switch network used as the packet switching switch in FIG. 1.

The time division communication path is concentrator multiplexed and time switch T.

The 0-time switch T is constructed by combining three types of switch functions of the space switch S.

Call memory SPM, control memory CM and counter circuit C○
The 0 call memory SPM is a memory that stores digitally encoded information corresponding to the multiplex coal portion of the highway, and the control memory CM is a memory that specifies the write address (read address) of the call memory SPM. Further, the counter circuit CO is a circuit for sequentially reading (writing) digitally encoded information from the speech memory SPM.

Next, the space switch is composed of a gate matrix using electronic components such as LSI, and by opening and closing these gates in a time-division manner at high speed, the multiplexed information bit string is kept multiplexed and is Replace the highway. The T-8-T switch shown in FIG. 16 has the above-described spatial switch S sandwiched therebetween, and has a primary time switch T connected to the front stage and a secondary time switch T connected to the rear stage.

Next, the Banyan network shown in FIG. 7(b) constituting the packet switch network forms a three-stage routing network using 2×2 13 anyan switches as unit switches.
The 2x2 B anyan switch has two
It consists of two buffer registers, four gates for distribution to two output links, and two synchronization registers. In this way, the Banyan switch network consists of 2×2
Since it is realized using the building block configuration of the switch, it is possible to prevent packet concentration, and even if the switch size is increased, it is difficult to cause major changes or deterioration of characteristics, and it has excellent scalability (Banyan switch For example, L, T, Wu et al, f
Synchronous wideband frequency band network
ronous Wideband Network)
,Proc, IEEE ZurichS emina
r B 1 , (1986)) 6 In addition, the Benes network in FIG. 7(a) is the same as the Banyan network in FIG. 7(b), with a two-stage distributed network connected to the front stage of the same routing network, and The distribution network at the front stage can distribute calls evenly, and the routing network at the rear stage can prevent packet concentration. For reference, the characteristics of the Benes network and the Banyan network are described in the Journal of the Institute of Electronics, Information and Communication Engineers (A), February 1987 Special Issue on Network Issues.
Written by Ota and Yamaguchi.

When the circuit switching network with the T-3-T configuration in FIG. 6 is used as the switch circuit network 7 in FIG. 1, the control memory 9 in FIG. Since it can also be used as the control memory 11 of the T-switch, the amount of hardware can be reduced and control can be simplified.

For the packet switch 8 in FIG. 1, a multi-stage link packet switch network having buffers for collision avoidance in unit switches such as the Benes network in FIG. 7(a) or the Banyan network in FIG. 7(b) is used, and If empty packet patterns are identified by unit switches in the switch network, the empty pattern detection circuit 94 of FIG. Also, the gate 93 can be made unnecessary.

FIG. 5 is a detailed configuration diagram of the line slot/packet slot multiplexing circuit in FIG. 1. In Figure 5,
100 is a control memory, 101 is a selector, 102 is a selector, 103 is a FIFO (First In Fi
rst 0ut), 104 is a free pattern generator. The control memory 100 records the usage positions of line slots. Therefore, by using this record, the selector 101 can use the output transmission line 1 when outputting the line slot.
-2 to the outgoing circuit switched highway 4-2. Also, in other slots, the packet in PIFO 103 is output, but if the packet in FIFO is empty,
The empty slot pattern from the empty pattern generator 104 is output. At this time, when a circuit switching network with a T-8-T configuration shown in FIG. 6 is used as the switch circuit network 7, the control memory 100 in FIG. Since it can also be used as the control memory 12 of the next T-switch, the amount of hardware can be reduced and control can be simplified.

8 and 9 are explanatory diagrams showing a third embodiment of the present invention, in which FIG. 8 is a diagram showing a frame configuration, and FIG. 9 is a detailed configuration diagram of a line slot/packet slot separation circuit. It is.

As shown in FIG. 8, this embodiment differs from the first and second embodiments in that the slot length is set smaller than the packet length and one packet is divided into multiple slots and inserted. are different. The line slot/packet slot separation circuit of FIG. 9 also differs in configuration from the separation circuit of FIG. 4 in the second embodiment described above in that a FIFO memory 96 is used in place of the gate 93. The method of separating line slots from other slots using the control memory 92 is the same as the separation circuit shown in FIG. 4, and when the T-S-T switch shown in FIG. 6 is used for line switching,
Similarly, the control memory 11 and control memory 9 of the primary T-switch can be used in common. The difference is that the FIFO controller 95 detects an empty slot pattern with an empty pattern detection circuit 94, identifies empty slots and packet slots, and includes a FIFO memory 96 and a FIFO controller 95 that controls writing only the packet slots into the FIFO memory 96. ,
This is the point of assembling one packet from multiple packet slots. Further, after the FIFO memory control unit 95 finishes storing one packet, it sends the packet to the packet switch network highway 5-1. The start of packet reception can be detected when a pattern other than an empty pattern arrives at the FIFO memory 96, and the end of packet reception can be detected when an empty pattern arrives at the FIFO memory 96.

In the third embodiment, the single line slot/packet slot multiplexing circuit 6 is similar to the second embodiment described above.
Use the configuration shown in the figure as is. That is, the control memory 10
The method of outputting the line slot preferentially using 0 and inserting the packet signal stored in the FIFO memory 103 where there is no line slot is the same as the second embodiment. Similarly, when the T-3-T switch shown in FIG. 6 is used for a purpose, the control memory 12 of the secondary T-switch can also be used as the control memory 100 shown in FIG. The difference is that the packets read into the FIF○ memory 103 through the output packet highway 5-2 are not read out all at once, but are read out in several parts.
This is the point where the packet is disassembled and output to the slot on the output transmission path 1-2. In this way, in addition to the effects of the second embodiment described above, the slot length can be made shorter than the packet length, the memory of the circuit switching switch can be reduced, and the packet length can be reduced. It has the advantage of being freely available.

〔Effect of the invention〕

As explained above, according to the present invention, by separately providing a switch circuit network for single circuit switching and a switch circuit network for packet switching, and using switch circuit networks suitable for each, both circuit switching and packet switching can be performed. A large-capacity switch can be realized, and by inserting packet slots into empty line slots, increases and decreases in the capacity of the circuit switching network can be immediately compensated for by increases and decreases in the capacity of the packet switching network.

[Brief Description of the Drawings] Figure 1 is a main configuration diagram of a line/packet composite switch system showing the first embodiment of the present invention, and Figure 2 is a diagram accommodating a conventional line/packet switching network on the same transmission path. A diagram showing the method, FIG. 3 is a configuration diagram of a frame showing a second embodiment of the present invention,
FIG. 4 is a block diagram of a line slot/packet slot separation circuit showing a second embodiment of the present invention, and FIG. 5 is a line slot/packet slot multiplexing circuit showing a second or third embodiment of the present invention. Fig. 6 is a diagram showing an example of a T-3-T switch used as a circuit switching switch;
The figure shows an example of a packet switch used as a packet switching switch, FIG. 8 is a frame configuration diagram showing a third embodiment of the present invention, and FIG. 9 shows a third embodiment of the present invention. FIG. 2 is a configuration diagram of a line slot/packet slot separation circuit shown in FIG. 1-1 = Input transmission line or path, 1-2: Output transmission line or path, 2: Frame synchronization circuit, 3: Line slot
Packet slot separation circuit, 4-1: switch highway for ingress circuit switching, 4-2 = highway for egress circuit switching, 5-1: switch highway for ingress packet switching, 5
-2=Output packet switching switch highway, 6: Line slot/packet slot multiplexing circuit, 7: Line switching switch or switch network, 8: Packet switching switch or switch network, 11, 12: Time switch control memory, 91: switch of separation circuit, 92: control memory of separation circuit, 93: gate, 94: empty pattern detection circuit, 95: FIFO control section, 96: FIFO memory, 101, 102 = selector of multiplexing circuit , 103
: FIFO memory of multiplexing circuit, 104: Free pattern generator. Figure 2 Figure 4 Figure 5 Figure 6 Figure S, CHS: Channel memory CM system sub-memory COz counter Figure 7 (a) Benes network (b) Banyan network L--J Figure 8 Figure 9 Figure q]

Claims (5)

[Claims] (1) a frame synchronization circuit that synchronizes the phase of bits, slots, and frames; and a separation circuit that is connected to the frame synchronization circuit and separates line slots and packet slots;
A line switching switch or switch network and a packet switch or switch network are respectively connected to the separation circuit, and a multiplexing circuit is connected to the switch or switch network and multiplexes line slots and packet slots. , the separation circuit separates line slots whose usage slots are determined in advance from among the time-division multiplexed signal slots, inputs them to the line switching switch or switch network, and extracts packet slots from the remaining slots. The extracted packet is input to the packet switch or switch network, and the line switching switch or switch network performs a switching operation of the line switching network to output the line slot to a predetermined slot of the intended output route; The packet switching switch or switch network performs the switching operation of the packet switching network and outputs the packet to the intended output route, and the multiplexing circuit performs the switching operation of the packet switching network and outputs the packet to the intended output route. A line/packet composite switch system characterized in that a packet slot output from the packet switching switch is inserted into a vacant line slot to time-division multiplex the line slot and packet slot. (2) In the line/packet composite switching system according to claim 1, the slot length and the packet length are made equal to each other for time-division multiplexed frames input to the switch or switch network, and A line/packet composite switch system characterized by inserting one packet. (3) In the line/packet composite switching system according to claim 1, the slot length is made shorter than the packet length for time-division multiplexed frames input to the switch or switch network, and one packet is A line/packet composite switch method that is characterized by dividing and inserting into multiple slots. (4) In the line/packet composite switching system according to claim 1, a T-S-T three-stage switch network is used as the line-switching switch network of the switch network, and the primary switch network of the three-stage switch network is Using the T-switch control memory,
A line/packet composite switch system characterized in that line slots are separated and packet slots are inserted and multiplexed using the control memory of the secondary T-switch of the three-stage switch network. (5) The line/packet composite switching system according to claim 1, characterized in that a multi-stage link type packet switch network is used for the packet switch in the switch network.