JPH05292130A - Semiconductor integrated circuit for communication control - Google Patents

Abstract

PURPOSE:To relieve the load on a host processor. CONSTITUTION:Reception serial data 101 of a synchronization detection circuit 3 are fetched by using a transmission reception clock signal 102, data in succession to a head flag are detected and an OUT terminal reaches a high level. An IN terminal of a counter 2 reaches a high level and a CT#1 terminal reaches a high level. A communication controller 1 fetches data from a received frame and sets a reception data fetch request signal 103 to a high level and sends the signal to AND circuits 5-8 of a DMA controller and ANDs the signal with an output level at a CT#1 terminal to make a DMA transfer request at a 1st frame. The OUT terminal of a synchronization circuit 3 is restored to a low level by the reception of an end flag of an FCS. Similarly, a transfer request of a 2nd frame is implemented by setting a high level to a #2 terminal and that of a 3rd frame and a 4th frame is implemented by setting a high level to a #3 terminal and a #4 terminal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit for communication control.

[0002]

2. Description of the Related Art A conventional semiconductor integrated circuit for communication control has one DMA request terminal for requesting transmission data transfer and one DMA request terminal for requesting reception data transfer. Has one host processor
It is customary to check the information each time a frame is received.

[0003]

In the conventional semiconductor integrated circuit for communication control described above, since the frame error information is checked for each frame, the transfer request signal for the transmission data and the reception data to the DMA controller is transmitted. Even if a plurality of transfer request signals are provided, the merit of increasing the transfer request signals cannot be seen in terms of the system. In the case of a receiving operation, after receiving one frame, the host system checks whether or not there is an FCS error, and in order to enable the re-generation of the DMA transfer request signal by the next frame reception, Is required to be issued to the semiconductor integrated circuit for communication control. Therefore, there is a disadvantage that the host processor becomes more burdened as the communication speed increases.

Regarding the transmission operation, in the host processor, the processing of setting the address of the transmission buffer in the DMA controller and issuing the command of the DMA transfer start every time one frame is transmitted, The drawback is that the host processor is overloaded.

[0005]

The semiconductor integrated circuit for communication control of the present invention is a semiconductor integrated circuit for communication control applied to a communication system using the HDLC protocol, and is received via a communication line of the communication system. A plurality of receive DMA request output terminals per communication channel and a plurality of HD
A register for holding error information generated in response to LC frame reception, and a plurality of HDLs for executing processing in a host processor corresponding to the communication system.
The feature is that it is performed every time the transmission and reception of the C frame is completed.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention. As shown in FIG. 1, this embodiment includes a communication control unit 1, a counter 2, a synchronization detection circuit 3, a register 4, and AND circuits 10 to 13. The communication control unit 1 is a block of a communication control circuit according to the related art, and in the counter 2, after the power is turned on,
When the CT # 1 to CT # 4 terminals shown in FIG. 1 are set to a low level and the IN terminal changes from a low level to a high level, the CT # 1 terminal changes to a high level and the IN terminal changes from a low level to a high level. Then, the CT # 1 terminal changes to the low level and the CT # 2 terminal changes to the high level. Similarly, every time the IN terminal changes from the low level to the high level, the levels of the CT # 1 to CT # 4 terminals change. In the synchronization detection circuit 3, the OUT terminal is set to the low level immediately after the power is turned on.
While this OUT terminal is low level, CLK
When the signal input to the terminal changes from the low level to the high level, the state of the IN terminal is latched, and when the latched pattern is a pattern in which six or more "1" s are not continuous after "011111100", The OUT terminal is set to high level. Then, when the OUT terminal is at the high level, the IN terminal reads "0111111".
When the pattern of "0" is input, the OUT terminal is returned to the low level. After that, the synchronization detecting circuit 3 repeats this series of operations.

In the register 4, while any one of the terminals A, B, C and D is at the high level, I
When the frame error signal input to the N terminal becomes high level, this state is latched by the corresponding D _{0 to} D ₄ terminals. At the terminals D _{0 to} D ₄ , if the inputs to the CS terminal and the RD terminal are all at the low level, the above latched state is output, and otherwise, it is held at the high level state. Also, AND circuits 5-8
In, if the two input terminals are both in the high level state, a high level signal is output to the output terminal, and in the other cases, the low level signal is output.

Next, the block diagram of FIG. 1 and FIG.
(B), (c), (d), (e), (f), (g),
FIGS. 3 (a), 3 (b), and (h), (i) and (j) are timing charts of the operation signals in this embodiment.
(C), (d), (e), (f), (g), (h),
The operation of this embodiment will be described with reference to the timing charts of the operation signals in the register 4 shown in (i), (j) and (k).

Regarding the receiving operation, received serial data 101 and a transmission / reception clock 102 using the HDLC frame format are sent via a communication line. In the synchronization detection circuit 3, the reception serial data 101 input to the IN terminal is sampled by the transmission / reception clock 102 input to the CLK terminal and taken in as data, and the head flag of the HDLC frame and the data following it are detected. Then, the OUT terminal becomes high level.
As a result, in the counter 2, the IN terminal becomes high level, and the level of the CT # 1 terminal also changes to high level. In the communication control unit 1, the received HDL
Received data is fetched from the C frame, and the DMA controller requests the DMA controller to set the received data take-up request signal 103 to high level for each data. The received data takeover request signal 103 is sent to the AND circuits 10 to 13, but in the AND circuit 10,
The logical product of the output level of the CT # 1 terminal in the counter 2 and the received data takeover request signal 103 is calculated, and the DMA is performed.
A DMA transfer request for the received data of the first frame is issued to the controller by setting the transmission DMA request # 1 terminal 51 to the high level. Upon reception of the next termination flag of the FCS, the OUT terminal is returned to the low level in the synchronization detection circuit 3, and the preparation for reception of the second frame is performed. After that, if two frames are received in the same manner,
The DMA transfer request for the received data of the frame is the received DM
The A request # 2 terminal is set to a high level, and regarding the DMA transfer request of the reception data of the third frame and the fourth frame, the reception DMA request # 3 terminal and the reception DMA request # 4 terminal are set to the high level, respectively. Is set to.

Next, a frame error (overrun FC
The operation of S error and abort reception) will be described.

First, when there is an error during the reception of the first frame, the communication control unit 1 outputs a high level pulse corresponding to the time of one byte length of the received data from the FCSE terminal. .. In register 4,
When the IN terminal receives this high level pulse and the A terminal is at the high level, "1" indicating the error state is D _0.
Latch to bit. Similarly, the level state of the IN terminal is monitored while each of the B, C, and D terminals is at the high level, and the D ₁ bit, D ₂ bit, and D ₃ bit corresponding to the respective terminals are monitored. If there is an error, its state is latched and held in each bit. After receiving four frames, the host processor (not shown) sets the select signal 104 and the read control signal 105 to low level to read and analyze in which frame the error occurred.
In the register 4, the select signal 104 and the read control signal 105 are supplied to the CS terminal and the RD, respectively.
When the CS terminal returns from the low level to the high level in response to the terminal, the internal D _{0 to} D ₃ bits are cleared and the state is returned to "0".

Further, at the time of transmission, in the communication control section 1, the parallel data written in the state where the transmission data write signal is at the high level is converted into serial data, which is output from the TxD terminal as the transmission serial data 108, and the TxBE terminal. More specifically, the high level transmission data write request signal 106 is output to the DMA controller.

Next, a second embodiment of the present invention will be described. FIG. 4 is a block diagram showing a second embodiment of the present invention. As shown in FIG. 4, this embodiment comprises a communication control unit 1, counters 2 and 5, a synchronization detection circuit 3, a register 4, and AND circuits 6 to 13. Among these constituent blocks, the communication control unit 1, the counter 2, the synchronization detection circuit 3, the register 4 and the AND circuit 1
0 to 13 and the like operate similarly to the case of the first embodiment described above. The operation of the counter 5 is substantially the same as the operation of the counter 2, but the difference is that immediately after the power is turned on, the CT
Whenever the # 1 terminal goes high and a state change from low level to high level is input to the IN terminal, CT #
That is, the signal changes to a high level in the order of 2 → CT # 3 → CT # 4 → CT # 1. After that, when one terminal becomes high level, the operation in which the terminal which was at high level until then returns to low level is similar to the case of the counter 2.

Hereinafter, the block diagram of FIG. 4 and FIG.
(B), (c), (d), (e), (f), (g),
The operation of this embodiment will be described with reference to the timing diagrams of the operation signals in this embodiment shown in (h) and (i).

At the time of transmission, in the communication control unit 1, when the transmission is enabled, the transmission data write request signal 10 is sent.
6 is set to high level. The transmission data write request signal 106 is sent to the AND circuits 6 to 9, but AN
In the D circuit 6, this transmission data write request signal 1
06 and a signal input from the counter 5CT # 1 terminal are ANDed, and the output is sent to a DMA controller (not shown) as a signal of the transmission DMA request # 1 terminal 55. In the DMA controller,
When the DMA transfer is performed for the set number of bytes, it does not respond to further DMA requests. Therefore, the communication control unit 1 automatically enters the transmission underrun state and is input to the IN terminal of the counter 5. The transmitted underrun signal 107 thus set becomes high level. Through this operation,
The transmission serial data 108 is output from the TxD terminal, and the transmission of the first frame is completed. In response to the level change of the transmission underrun signal 107, in the counter 5, the level of the CT # 1 terminal is returned to the low level next, and the level of the CT # 2 terminal is set to the high level.
The second frame is transmitted as in the case of the first frame. Thereafter, similarly, for the third frame, the transmission DM
Transmission is performed using the A request # 3, and transmission is performed using the transmission DMA request # 4 for the fourth frame. The transmission underline signal 107 returns to the low level after the FCS of each frame is transmitted.

In the case of this second embodiment, the above-mentioned first embodiment is used.
Compared with the first embodiment, since the transmission DMA request signal is also pluralized, there is an advantage that the load on the host processor can be further reduced as compared with the first embodiment.

The operation at the time of reception including the communication control unit 1, the counter 2, the synchronization detection circuit 3, the register 4 and the AND circuits 10 to 13 is the same as in the case of the above-mentioned first embodiment. The description is omitted.

[0019]

As described above, the present invention provides a DMA for transmitting / receiving data transfer in a semiconductor integrated circuit for communication control.
By providing a register for holding the result of reception of a plurality of frames with a plurality of terminals, as the processing operation in the host processor after reception of the plurality of frames, it is only necessary to perform a process corresponding to the semiconductor integrated circuit for communication control, Since the processing operation performed for each frame is completely eliminated, the load on the host processor is significantly reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a timing diagram of operation signals in the first embodiment.

FIG. 3 is a timing diagram of operation signals in the register of the first embodiment.

FIG. 4 is a block diagram showing a conventional example.

FIG. 5 is a timing diagram of operation signals in a conventional example.

[Explanation of symbols]

 1 Communication Control Unit 2, 5 Counter 3 Synchronization Detection Circuit 4 Register 6-13 AND Circuit

Claims (1)

[Claims] 1. A semiconductor integrated circuit for communication control applied to a communication system using an HDLC protocol, wherein one communication is used as an output terminal for requesting a DMA transfer of data received via a communication line of the communication system. A plurality of reception DMA request output terminals per channel and a register for holding error information generated in response to reception of a plurality of HDLC frames are provided, and execution of processing in a host processor corresponding to the communication system is performed by a plurality of A semiconductor integrated circuit for communication control, which is performed every time transmission / reception of an HDLC frame is completed.