JP2546901B2 - Communication control device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a communication control device, and more particularly to a memory element suitable for increasing the processing speed of the communication control device.

[Prior Art] In a communication control device, transmission processing of transmission data requested by a higher-level computer to a line according to a transmission protocol, analysis of received data from the line according to the protocol, and Performs transfer processing to the host computer.

For this reason, a buffer memory for storing transmitted / received data is provided, but if this memory is configured with only one memory, it is accessed from three sides: access from the upper level, access from the line, and access by protocol processing. Must be a 3-port memory.

However, since it is difficult to make a completely independent three-port memory in terms of performance and cost, a method of realizing by two-port memory is usually used.

For example, in the field of communication, a technique and the like have been devised, in which attention is paid to the fact that a transmission system and a reception system have high independence, a transmission / reception unit is divided, and a protocol header and information data are stored by separate two-port memories. ing.

As such a communication control device, for example, Japanese Patent Laid-Open No. 62-
The technique described in Japanese Patent No. 60044 is known.

In the field of memory, memory for specific applications is also being developed, and as a memory suitable for a communication input / output buffer, for example, Nikkei Electronics 1986.10.6 p.
68, 69 "Large-capacity 32K x 8-bit large-capacity FIFO memory suitable for input / output buffer of data communication device is released".

[Problems to be Solved by the Invention] According to the above-mentioned conventional technique, a different two-port memory is required for each type of data, and there is a problem that the amount of headwear increases.

When a general-purpose FIFO memory for communication is used as the 2-port memory, only sequential access is possible, so it is suitable as an input / output buffer, but it can be used for applications that require random access such as protocol processing. There is a problem in application.

Further, when a memory with two random access ports is used as the two-port memory, there is a problem that the circuit scale increases and the control becomes complicated, resulting in an increase in cost.

On the other hand, DMAC that controls data transfer with 2-port memory
Since the (direct memory access controller) and the control line of the control circuit are shared with the data line of the two-port memory, there is a problem that the control data and the transfer data conflict with each other, which lowers the processing efficiency.

An object of the present invention is to provide a communication control device suitable for high-speed transmission, and also to provide a memory element suitable for the control device.

[Means for Solving the Problems] In order to achieve the above object, the present invention has a random access memory cell and a serial access memory cell, and a random access port and a serial access port (data for sequentially accessing the serial access memory cell. Port), a transmit dual port memory for storing transmit data, a receive dual port memory for storing receive data, and a processor for accessing the receive and transmit dual port memory from a random access port or a serial access port for protocol processing. A contention control means for controlling contention between an access of a processor performing protocol processing and an access of a host device in each port accessed by the processor; and data between the processor and the host device. A register that stores received data in a receive dual-port memory from a port different from the port accessed by the processor,
A transmission control circuit that transmits data stored in a transmission dual-port memory, and a first communication control device.

Further, in order to achieve the above object, the present invention provides a transmission dual port memory having a random access memory cell and a serial access memory cell, a transmission dual port memory having a random access port and a serial access port, and a reception data. Stores the received data in the receive dual-port memory from the random access port according to the receive dual-port memory and the DMA processing instruction, and transmits the data stored in the transmit dual-port memory DM
It can be separated from the communication means having an A controller and the data bus that accesses the dual port memory for reception and transmission from the serial access port for protocol processing, and the communication LSI having a DMA controller accesses the serial access port. A processor that issues a DMA processing instruction through a bus, a contention control unit that controls contention between an access of a processor that performs protocol processing and an access of a host device in each serial port accessed by the processor, and between the processor and the host device. And a register for storing the data of 1., and a second communication control device.

In order to achieve the above object, the present invention provides a random access memory cell accessible from a random access port, a random access memory cell capable of at least read access from a first serial access port, and a bus for data transfer. At least write access is possible from the connected first serial access memory cell and the second serial access port which is the same as or different from the first serial access port. Second connected by bus
And a serial access memory cell for the dual port memory.

Further, in order to achieve the above object, the present invention further comprises: a dual port memory including the two serial access memory cells, a processor for performing protocol processing by accessing the dual port memory from a random port, and a random port A contention control means for controlling contention between an access of a processor performing protocol processing and an access of a host device; a register for storing data between the processor and the host device; and a dual port from the first and second serial ports. Access memory, store received data,
A transmission control circuit for transmitting stored data, and a third communication control device.

In order to achieve the above object, the present invention also provides a transmission dual port memory, a reception dual port memory for storing reception data, a processor for performing protocol processing, a processor for processing a protocol, a transmission dual port memory, and a reception dual port. A register for storing data to and from a host device that accesses the memory, a means for storing the received data in the receiving dual-port memory and transmitting the data stored in the transmitting dual-port memory, a receiving dual-port memory and a transmitting A register for storing access data of the processor to the dual port memory; and a transmission control circuit having means for mediating access to the receiving dual port memory and the transmitting dual port memory of the processor via the register. Special A fourth communication control device is provided.

Furthermore, the present invention further comprises: a dual port memory including the two serial access memory cells; a processor that performs protocol processing; a register that stores data between the processor that processes the protocol and a host device; Accessing the dual port memory from the first and second serial ports, storing the received data, and
A means for transmitting the stored data, a register for storing access data of the processor to the dual port memory, and a means for mediating access to the dual port memory by the processor via the register A transmission control circuit is provided, and a fifth communication control device is provided.

In addition, in addition, the present invention, the communication control device,
There is provided an information processing device having a host device that communicates via the communication control device.

[Operation] According to the first communication control device of the present invention, the processor accesses the reception and transmission dual port memory through the random access port or the serial access port to perform the protocol processing. Controls contention between processor access and host device access.

On the other hand, the transmission / reception of data between the processor and the host device is performed via a register. Further, the transmission control circuit stores the reception data in the reception dual port memory from a port different from the port accessed by the processor and transmits the data stored in the transmission dual port memory.

Further, according to the second communication control device of the present invention, the communication means stores the received data from the random access port in the reception dual port memory according to the DMA processing instruction, and transmits the data stored in the transmission dual port memory. To do. On the other hand, the processor accesses the dual port memory for reception and transmission from the serial access port for protocol processing, and the communication LSI having a DMA controller performs DMA processing through a bus that is separable from the data bus for accessing the serial access port. Issue an order. The contention control means controls contention between the access of the processor performing the protocol processing and the access of the host device in each serial port accessed by the processor. Further, data transmission / reception between the processor and the higher-level device is performed via a register.

Further, according to the dual port memory according to the present invention,
The first serial access memory cell is at least read-accessed from the first serial access port,
The serial access memory cell is subjected to at least write access from the second serial access port which is the same as or different from the first serial access port. Further, data transfer between each serial access memory cell and random access memory cell is performed by the same or different buses.

Further, according to the third communication control device of the present invention, the processor accesses the dual port memory from the random port to perform the protocol processing. At this time, the contention control means controls the access of the processor and the host device. Control access conflicts. On the other hand, data transmission / reception between the processor and the host device is performed through a register. Further, the transmission control circuit accesses the dual port memory through the first and second serial ports, stores the received data, and transmits the stored data.

Further, according to the fourth communication control device of the present invention, the transmission / reception of data between the processor and the host device is performed via the register. Further, the transmission control circuit stores the received data in the reception dual port memory and transmits the data stored in the transmission dual port memory. Further, by storing the access data of the processor to the reception dual port memory and the transmission dual port memory in the register, the access to the reception dual port memory and the transmission dual port memory of the processor is mediated.

Further, according to the fifth communication control device of the present invention, data transmission / reception between the processor and the host device can be performed via the register. On the other hand, the transmission control circuit accesses the dual port memory from the first and second serial ports, stores the received data, and transmits the stored data. Further, by storing access data of the processor to the dual port memory in a register, access of the processor to the dual port memory is mediated.

[Embodiment] Hereinafter, a first embodiment of the communication control apparatus according to the present invention will be described.

 FIG. 1 shows the configuration of the communication control apparatus according to this embodiment.

In the figure, 1 is a communication control device, 2 is a host computer that requests the communication control device 1 to send and receive data, 3 is a protocol processor, 4 is a dual port memory for transmission data, 5 is a dual port memory for reception data, 6a Is a DMA control circuit for the dual port memory 4 for transmission data, 6
b is a DMA control circuit for the received data dual port memory 5, 7 is an access conflict control circuit for the transmitted data dual port memory 4, 8 is an access conflict control circuit for the received data dual port memory 5, and 9 is a transmission Control circuit,
Reference numeral 10 is a reception control circuit, and 11 is an interface register.

 Hereinafter, the operation of the communication control device 1 will be described.

 First, the operation when transmitting data will be described.

The host computer 2 accesses the transmission data dual-port memory 4 via the competition control circuit 7 and stores the transmission data. Then, after that, the host computer 2
Issues a transmission request to the protocol processor 3 via the interface register 11.

The protocol processor 3 receives the transmission request, accesses the dual port memory 4 for transmission data via the competition control circuit 7, and adds header information and the like according to the protocol to the transmission data. Then, the DMA control circuit 6a is activated to start transmission.

The DMA control circuit 6a performs a DMA operation for serial port access, and causes the serial port of the dual port memory 4 for transmission data to output the transmission data. The serial port of the dual port memory is a port that sequentially inputs or outputs data.

The transmission data output from the serial port is converted by the transmission control circuit 9 into serial data based on the control signal of the DMA control circuit 6a, and the data is transmitted to the transmission line.

 Next, the operation when receiving data will be described.

The reception data input from the reception line is received by the reception control circuit.
Converted to parallel data by 10.

When the presence of received data is recognized, the DMA control circuit 6b controls the received data dual port memory 5 to receive data dual port memory 5 via the serial port of the received data dual port memory 5.
The received data converted into parallel data is stored.

On the other hand, when the reception control circuit 10 finishes the reception,
The protocol processor 3 is notified via the DMA control circuit 6b. The protocol processor 3 notifies the higher-level computer 2 of the completion of reception in response to this. Upon receiving the reception completion, the host computer 2 reads the reception data of the reception data dual-port memory 5 via the competition control circuit 8 and completes the reception operation.

As described above, according to the present embodiment, by utilizing the independent accessibility of each port of the dual port memory, the dual port memory of the host computer 2 can be configured with a simple configuration even during transmission of the transmission control circuit 9. The transmission data can be stored in the storage without hindering the access.
Therefore, the speed can be increased. For the same reason, the reception can be speeded up.

Next, the DMA control circuits 6a and 6b used in this embodiment will be described.

 The structure is shown in FIG.

64 is a data buffer that receives data on the processor bus, 62 is an address decoder that creates an internal register selection signal from the address of the processor bus, 63 is a CPU I / F circuit that interfaces control signals of the processor bus, and 64 is a DM
A DMA I / F circuit that generates A control signal, 65 is an address register that generates a DMA address signal, 66 is a byte counter that counts the number of DMA data transfers, 67 is an address that separates the processor bus from the DMA bus It is a buffer.

In order to realize DMA operation, the processor sets the address register 65 and byte counter 66 via the bus,
Set the operation mode in AI / F circuit 64 and activate DMA.
When activated, the DMA address is output from the address buffer 67 and the DMA operation is started.

As described above, since the processor bus and the DMA bus are separately configured, it is not necessary to connect the processor and the data buffer to the same bus in order to realize the DMA operation. It is not necessary to connect the dual port memory 5 for received data to the bus of the protocol processor 3.

As a result, the independence of the random port and the serial port of the dual port memory 4 for transmitting data and the dual port memory 5 for receiving data can be effectively used.

 Next, a second embodiment of the present invention will be described.

 FIG. 3 shows the configuration of the communication control apparatus according to this embodiment.

In the figure, 12a is an access control circuit of the dual port memory 4 for transmission data, 12b is an access control circuit of the dual port memory 5 for reception data, 13 is a transmission control circuit with a DMA function, and 14 is a reception control circuit with a DMA function. . Since the other parts are the same code parts and the same function parts of the communication control device according to the first embodiment, the description thereof is omitted.

The difference between the configuration of the communication control device according to the present embodiment and the configuration of the communication control device according to the first embodiment is that the serial port and random port of the dual port memory 4 for transmission and the dual port memory 5 for reception are connected to the line side. And that is the opposite on the processor side.

The operation of the communication control device 1 according to this embodiment will be described below.

First, the operation when the host computer 2 transmits data will be described. The host computer 2 is the competition control circuit 7
The dual port memory 4 for transmission data is accessed through the access control circuit 12a. At this time, the access control circuit 12a converts the access format of the host computer 2 into the serial port access format of the dual port memory 4 for transmission data, The transmission data from the computer 2 can be stored in the transmission data dual port memory 4.

After that, the host computer 2 issues a transmission request to the protocol processor 3 via the interface register 11.

In response to a transmission request, the protocol processor 3 converts the access format via the conflict control circuit 7 and the access control circuit 12a to access the dual port memory 4 for transmission data, and to send data to the header according to the protocol. Add information etc. Then, after that, the transmission control circuit 13 is activated for transmission.

The transmission control circuit 13 outputs the transmission data from the random port of the dual port memory 4 for transmission data by the DMA operation.

The output transmission data is converted into serial data by the transmission control circuit 13, and the data is transmitted to the transmission line.

Next, the operation when receiving data will be described. The reception data input from the reception line is converted into parallel data by the reception control circuit 14 and stored in the reception data dual port memory 5 via the random port by the access control circuit 12b.

After that, the reception control circuit 14 notifies the protocol processor 3 of the reception end, and the protocol processor 3
Notifies the higher-level computer 2 of the completion of reception.

Upon receipt of the reception completion, the host computer 2 first instructs the access control circuit 12b to transfer the reception data from the RAM cell (described later) in the reception data dual port memory to the SAM cell. Access control circuit 12b uses SAM rather than RAM cell
Performs the transfer of received data to the cell.

Next, the host computer 2 accesses the received data dual port memory 5 via the contention control circuit 8. At this time, the access control circuit 12b monitors the access address of the host computer 2, and while the addresses continue. , Sequentially outputs one received data from the serial port. By repeating this, the reading of the reception data of the host computer 2 is completed, and the reception operation is completed.

As described above, according to this embodiment, similarly to the first embodiment, the computer 2 can store the transmission data without disturbing the access even while the transmission control circuit 13 is transmitting, Higher speed is possible. For the same reason, the reception can be speeded up.

Furthermore, according to the present embodiment, the communication line side of the dual port memory is a random access port, so that the transmission and reception control circuits 12a and 12b are commercially available,
There is also an effect that it can be configured by a DMA device (LSI) or a transceiver device (LSI) with a DMA function.

In the present embodiment, since the host computer 2 and the protocol processor 3 side are serial access ports, when the host computer 2 and the protocol processor 3 access data that is not a continuous address, the overhead of address setting occurs. growing. However, most of the communication data is data that is continuously treated, so its influence is small.

 The third embodiment of the present invention will be described below.

 FIG. 4 shows the configuration of the communication control apparatus according to this embodiment.

In the figure, reference numeral 15 is a transceiver LSI with a DMA function. Since the other parts are the same code parts and the same function parts of the communication control device according to the second embodiment, the description thereof will be omitted.

This embodiment considers application in the case where communication is not so fast, and accordingly, the configuration of the communication control device according to the present embodiment and the configuration of the communication control device according to the second embodiment are Between them, there is a difference in that the transmission control circuit 13 and the reception control circuit 14 according to the second embodiment are replaced with a single transceiver LSI 15 with a DMA function in the present embodiment.

The operation of the communication control device 1 according to this embodiment is the same as that of the second embodiment, but in this embodiment, the dual port memory 5 for receiving data and the dual port memory 4 for transmitting data and the communication line are connected. Data transfer in a batch
A commercially available transmitter / receiver LSI 15 with a DMA function and the like performs half-duplex using the DMA function.

As described above, according to this embodiment, one transmission / reception LS for data transfer between the reception data dual-port memory 5 and the transmission data dual-port memory 4 and the communication line is performed.
There is an effect that I can do.

Next, the communication control device 1 according to the first, second and third embodiments
The circuit diagram of the dual port memory used in the above will be explained.

 The structure is shown in FIG.

This memory has a random access memory cell (RA
M cell) 41 and serial access cell (SAM cell) 42, and RAM cell and SAM cell have a wide internal data bus (usually, all stored words of SAM cells can be transferred in one cycle) 4
These data buses are used for data transfer between the RAM cell and the SAM cell 42, which are connected to each other. Therefore, except for this transfer cycle, random port access and serial port access can be performed independently. Memory control circuit 43
Read and write access to RAM cell 41, SAM cell
42 read and write access as well as RAM cell 41 and SAM
Controls data transfer with cell 42.

As described above, according to the present dual port memory, random port access and serial port access can be performed independently.

By the way, since this memory has only one SAM cell, it cannot be used for serial output when used for serial input. In the first, second and third embodiments, dual port memories are provided for each of the transmission system and the reception system. There remains a circuit that must be.

Therefore, we present a dual-port memory that can eliminate this redundancy.

FIG. 6 shows the configuration of the dual port memory 16.

In this configuration, two SAM cells for input and output (161, 162) are provided in the dual port memory, and
The cell 163 and each SAM cell 161, 162 are connected by different data buses. The memory control circuit 164 performs read and write access to the RAM cell 163, read of the SAM cell 161, and write access of the SAM cell 162, as well as the RAM cell 163 and each SA.
Controls data transfer with the M cells 161, 162.

That is, this enables both serial input and serial output with one memory including the RAM cell 163.

Next, as a fourth embodiment, a communication control device 1 using a dual port memory 16 provided with two SAM cells will be described.

 The configuration of the communication control device according to the present embodiment is shown in FIG.

In the figure, 16 is a dual port memory provided with two SAM cells, 17 is a DMA control circuit, and 18 is a transmission / reception control circuit. Since the other parts are the same code parts and the same function parts of the communication control device according to the first embodiment, the description thereof will be omitted.

In this embodiment, the dual port memory 16 provided with two one SAM cells of the communication control device according to the first embodiment described above.
It consists of.

The operation is similar to that of the communication control device according to the first embodiment, but the number of transmission / reception memories is one, so the circuit is simplified. Only one DMA control circuit 17, transmission / reception control circuit 18, and competition control circuit 7 are required, and the configuration is simplified.

Even in this method, since the random port and the serial port are independent, the speed can be increased.

 Next, a fifth embodiment will be described.

In this embodiment, the protocol processor 2 in the communication control device according to the first embodiment described above is configured to access the transmission and reception dual port memories from the line side.

 FIG. 8 shows the configuration of the communication control device according to the present embodiment.

In the figure, 80 is a dual-port memory for transmission, 81 is a dual-port memory for reception, and there are two dual-port memories provided with the two SAM cells or two random access ports.
It uses dual port memory. Reference numeral 82 is a transmission control circuit, and 83 is a reception control circuit, which mediates access to the dual port memories 80 and 81 of the protocol processor. Since the other parts are the same code parts and the same function parts of the communication control device according to the first embodiment, the description thereof will be omitted.

The operation of this embodiment is similar to the operation of the communication control apparatus according to the first embodiment, except that the transmission dual port memory 80
When performing write access to, the protocol processor 3 stores data in a register in the transmission control circuit 82,
The transmission control circuit 82 is instructed to write to the transmission dual port memory 80. The transmission control circuit uses the transmission dual port memory 80 according to the instruction of the protocol processor 3.
Write register data to

Further, when reading the reception data of the protocol processor 3, the reception control circuit 83 first reads the protocol header partial data from the reception dual port memory 81 into a register in the reception control circuit 83 as appropriate. Alternatively, the reception data from the line is directly read into the register in the reception control circuit 83. Then, the protocol processor 3 is notified that there is received data. In response to this, the protocol processor 3 reads this data from the register.

As described above, according to the present embodiment, the access to the dual port memory of the host computer can be performed without contention, and the contention control circuits 7 and 8 in the first embodiment are not necessary.
Since the dual port memory of the protocol processor 3 is accessed through the register, the bus of the protocol processor 3 and the line side bus of the dual port memory can be made independent, and the access efficiency to the DMA control circuit and the dual port memory can be improved. It can be improved as a whole.

As described above, according to this embodiment, transmission / reception data transfer between the upper computer and the protocol processor and the dual port memory and transmission / reception data transfer between the dual port memory and the transmission line can be performed independently, so that high speed data transmission is possible. Is possible.

[Effect of the Invention] As described above, according to the present invention, it is possible to provide a communication control device suitable for high-speed transmission, and it is possible to provide a memory element suitable for this communication control device.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of a communication control apparatus according to the first embodiment of the present invention, FIG. 2 is a block diagram showing the configuration of a DMA control circuit according to the first embodiment, and FIG. Block diagram showing a configuration of a communication control device according to the second embodiment, the fourth
FIG. 6 is a block diagram showing the configuration of a communication control apparatus according to the third embodiment of the present invention, FIG. 5 is a block diagram showing the configuration of a dual port memory used in the first, second and third embodiments, and FIG. FIG. 7 is a block diagram showing the configuration of a dual port memory used in the fourth and fifth embodiments, FIG. 7 is a block diagram showing the configuration of a communication control device according to the fourth embodiment of the present invention, and FIG.
FIG. 9 is a block diagram showing the configuration of the communication control device according to the fifth embodiment of the present invention. 1 ... Communication control device, 2 ... Host computer, 3 ...
Protocol processor, 4 ... Dual port memory for transmission data, 5 ... Dual port memory for reception data, 6a, 6b ... DMA control circuit, 7, 8 ... Access conflict control circuit, 9 ... Transmission control circuit, 10 ... Reception control circuit, 11 ... Interface register, 12a, 12b ... Access control circuit, 13 ... Transmission control circuit, 14 ... Reception control circuit, 15 ... DMA built-in communication LSI, 17 ... Bus switch, 18
...... Transmission / reception control circuit.

 ─────────────────────────────────────────────────── ─── Continuation of front page (56) References JP-A-64-12356 (JP, A) Special table: S62-501454 (JP, A)

Claims (7)

(57) [Claims] 1. A transmission dual-port memory for storing transmission data and a reception dual-port memory for storing reception data, the transmission dual-port memory having random access memory cells and serial access memory cells, and having a random access port and a serial access port. And a processor that performs protocol processing by accessing the dual-port memory from a random access port or a serial access port, and in each port that the processor accesses, control the competition between the access of the processor that performs the protocol processing and the access of the host device Contention control means, a register for storing data between the processor and a higher-level device, receive data from a port different from the port accessed by the processor in a receive dual port memory, and a transmit dual And a transmission control circuit for transmitting the data stored in the report memory, the communication control device. 2. A transmission dual port memory for storing transmission data, a reception dual port memory for storing reception data, comprising a random access memory cell and a serial access memory cell, and having a random access port and a serial access port, and a DMA. Stores the received data from the random access port in the receive dual port memory according to the processing instruction, and transmits the data stored in the transmit dual port memory DMA
Through a communication means having a controller, and a data bus for access to the receiving and transmitting dual port memory through a serial access port for protocol processing, and a communication LSI having a DMA controller for accessing the serial access port A processor that issues a DMA processing instruction, a contention control unit that controls contention between an access of a processor that performs protocol processing and an access of a host device in each serial port accessed by the processor, and data between the processor and the host device. And a register for storing the. 3. A random access memory cell accessible through a random access port, and a first serial access which is at least read accessible through a first serial access port and is connected to the random access memory cell through a data transfer bus. A memory cell and a second serial port that is the same as or different from the first serial access port
The dual-port memory, which has at least write access through the serial access port, and a random access memory cell and a second serial access memory cell connected by a bus for data transfer which is the same as or different from the bus. 4. The dual port memory according to claim 3, a processor for accessing the dual port memory from a random port for protocol processing, and an access for a processor for performing protocol processing and an access for a host device in the random port. Contention control means for controlling contention, a register for storing data between the processor and a host device, a dual port memory is accessed from the first and second serial ports to store received data, and stored. And a transmission control circuit for transmitting the stored data, the communication control device. 5. A transmission dual-port memory, a reception dual-port memory for storing reception data, a processor for protocol processing, a processor for protocol processing, and a host device for accessing the transmission dual-port memory and reception dual-port memory. A register for storing data between, a means for storing the received data in the receiving dual-port memory and transmitting the data stored in the transmitting dual-port memory, and a receiving dual-port memory and a transmitting dual-port memory of the processor. A communication control device comprising: a register for storing access data; and a transmission control circuit having means for mediating access to the reception dual-port memory and the transmission dual-port memory of the processor via the register. . 6. The dual port memory according to claim 3, a processor that performs protocol processing, a register that stores data between the processor that processes the protocol and a host device, and the first and second serial ports. Means for accessing the dual port memory, storing the received data, and transmitting the stored data, a register for storing the access data of the processor to the dual port memory, and the register via the register A communication control device comprising: a transmission control circuit having means for mediating access of the processor to the dual port memory. 7. An information processing apparatus, comprising: the communication control device according to claim 1, 2, 3, 5 or 6, and a host device that communicates via the communication control device.