JPH05241966A - Memory controller - Google Patents

Abstract

PURPOSE:To report the occurrence of abnormality by detecting the fact that write on an area on which the write of a RAM is inhibited is going to be performed due to the occurrence of malfunction, etc., by inhibiting the write in hardware manner and to prevent a program area from being destroyed. CONSTITUTION:This controller is comprised by providing a memory means 2 by which the holding of data stored by receiving power supply setting a built-in battery as a power source 11 is backed up, an identification means 7 to identify the presence/absence of access enable signal for a prescribed block out of plural separated blocks in block unit in the memory means 2, write means 6-1, 6-2, and 6-3 by which the write on the memory means 2 is controlled based on the identification result of the identification means 7, and a means 8 which reports the fact that the write is instructed while the identification means 7 displays access inhibition to a central processing means 1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory control device having memory means for backing up the retention of stored data by receiving power from a built-in battery as a power source.

[0002]

2. Description of the Related Art Conventionally, a handy terminal has been used as a portable electronic device that is connected to a central processing unit (CPU) of a host computer to transmit data and is used for inventory management of products.

FIG. 4 shows an example of a conventional handy terminal. Reference numeral 1 is a central processing unit (CPU), which corresponds to a microprocessor or the like. Reference numeral 2 denotes a RAM (random access memory), which is configured such that the stored contents are held by the backup power supply 11. An address bus 3, a data bus 4, a read control line (RD) 5 and a write control line (W) are provided between the central processing unit 1 and the RAM 2.
T) 6 are connected. The memory 2 is accessed by executing the operation indicated by the read or write control line 5 or 6 via the data bus 4 with respect to the memory area of the address displayed by the address bus 3. In other words, if an instruction to execute writing is output to the write control line 5 due to an abnormal operation caused by a malfunction, not by a normal operation, the contents of the address designated by the address bus at that time will be the contents of the data bus 2. It will be rewritten.

[0004]

As described above, in controlling the memory of a handy terminal or the like, the software control exclusively discriminates between the rewritable area such as the program area and the rewritable area such as the data area. Therefore, writing to the write-protected area has been prohibited. However, such a control method has a drawback in that writing to the program area caused by malfunction of the device due to external noise or the like cannot be prevented. Then, once the program area is rewritten, there is a problem that the normal operation thereafter cannot be obtained unless the program is reloaded.

Some of the external noises described above are caused by, for example, electrostatic discharge, and it is extremely difficult to predict when the noise will occur.

[0006]

SUMMARY OF THE INVENTION According to the present invention, a memory means is configured to backup stored data by receiving power from an internal battery as a power source. Is divided into blocks.

Then, for each size of the divided blocks,
An identification flip-flop for identifying the write enable bit is provided corresponding to the memory. Then, by comparing the address information of the memory appearing on the address bus with the state of the identification flip-flop by the hardware circuit, it is attempted to write to the area where the writing is prohibited due to the malfunction. At this time, the write control signal to the write prohibited area is prohibited by the gate. In addition to the prohibition, the central processing unit is notified of the occurrence of abnormal operation.

[0008]

According to the present invention, the above-mentioned rewriting of the program area, which cannot be prevented only by the control by software, is not performed by hardware when writing to an area which is originally prohibited. Is detected and the central processing means (CPU) is notified of the occurrence of an abnormality, thereby preventing the destruction of the program area due to the abnormal operation of the device.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows an embodiment of the present invention, and the same reference numerals as those in FIG. 4 are common. In FIG. 1, RAM corresponds to areas A, B and C, respectively 2-
It is divided into three areas like 1, 2, 2 and 2-3,
The address bus 3, the data bus 4, and the read control line 5 are commonly connected. The reason why the presence / absence of access permission is not reflected in the read control line 5 is that it does not affect the contents of the held memory even if the read is executed.

In this embodiment, a 3-bit flip-flop, an address information decoder and a gate group are provided,
It has an identification unit for identifying permission / prohibition of write access to the memory, and a write control identification circuit 7 as a functional block for performing write control on the memory. This circuit 7
A data bus 4 is connected as an input for setting the state of the flip-flop. An address bus 3 is connected as a decoder input for detecting which address of the memory area is about to be accessed. As another input, the clock signal line 9 from the central processing unit 1 and the control line 6 for inputting the WT signal for write control are connected. Write control identification circuit 7
In the present embodiment, the area A (2-
Write control line 6-1 to 1) and RAM area B
A write control line 6-2 to (2-2) and a write control line 6-3 to the area C (2-3) of the RAM are provided. An abnormal operation notification signal line 8 is connected to output an INT signal for notifying the abnormal operation to the central processing unit 1.

FIG. 2 is a block diagram showing a specific structure of the write control identification circuit 7 shown in FIG. In FIG. 2, reference numerals 71, 72 and 73 are 3-bit flip-flops, which receive inputs from the data bus 4 connected to the central processing unit 1 and the clock signal line 9 and which are arbitrary according to instructions from the central processing unit 1. Set to state.

Input D of the data bus 4 from the central processing unit 1
"1" _0, "1" to the input D _1, when a signal of "0" to the input D ₂ are given, respectively, when the clock input from the clock signal line 9 is provided, the flip-flop 71
A state "1" is set to the output Q of the flip flops 72 and 72, and a state "0" is set to the output Q of the flip-flop 73. The outputs Q of the flip-flops 71, 72, 73 are connected to one input ends of AND gates 74, 75, 76, respectively, and the write control line 6 is connected to the other input end of the AND gates 74, 75, 76. It is connected. The outputs of the AND gates 74 to 76 correspond to the write control lines 6-1 to 6-3, and are the divided memory blocks R.
The write control signals are configured to correspond to the areas A to C (2-1 to 2-3) of AM. Therefore, the output Q of the flip-flop is "1".
In this state, the write enable control signal is transmitted only to the connected memory block. That is, in the above-mentioned state, the area A (2-1) of the RAM in FIG.
Thus, only area B (2-2) is allowed to write. Since the write control line (6-3) in the area C (2-3) of the RAM is prohibited by the AND gate 76 in FIG. 2, a state where data is written to the address due to a malfunction is shown in FIG. Even if given from the central processing unit 1, the data is protected from writing. The logic circuit composed of the inverters 77 and 78 and AND gates 79, 80 and 81 shown in FIG. 2 is designed to match the output Q of the flip-flop which is a signal indicating a block unit of the memory divided from the address decoder. belongs to. In this example, the output Q of the flip-flop 73
Only the state is "1", and the output from the AND gate 81 becomes "1" when writing is performed to the RAM area C (2-3) due to a malfunction, and the INT signal becomes abnormal via the OR gate 82 and the AND gate 83. It is output from the operation notification signal line 8 to notify the central processing unit 1 of FIG. 1 that an abnormal operation has occurred.

FIG. 3 shows a divided memory block (RAM).
Area A, B, C) and address information (A _n , A _n-1 ) are shown.

[0014]

As described above, in the memory control device of the present invention, the memory is divided into blocks, and the means for distinguishing between the write-allowed portion and the write-inhibited portion is provided, whereby the area prohibited due to the occurrence of malfunction occurs. It is possible to realize a memory control device capable of protecting the memory when a write operation to the memory occurs and notifying the central processing unit of the fact that the abnormal operation has occurred.

[Brief description of drawings]

FIG. 1 is a circuit block diagram of a memory control device of the present invention.

2 is a block diagram of a write control identification circuit shown in FIG. 1. FIG.

FIG. 3 is a diagram showing a correlation with a real address in which a memory is a block unit.

FIG. 4 is a circuit block diagram of a conventional memory control device.

[Explanation of symbols]

 1 Central Processing Unit 2 RAM (Memory) 3 Data Bus 4 Address Bus 5 Read Control Line 6 Write Control Line 7 Write Control Identification Circuit 8 Abnormal Operation Notification Signal Line

Claims (1)

[Claims] 1. A memory means for backing up the retention of stored data by receiving power supply from a built-in battery as a power source, and access permission to a predetermined block in block units divided into a plurality of the memory means. Identification means for identifying the presence / absence, writing means for controlling writing to the memory means based on the identification result of the identification means, and a case where writing is instructed while the identification means displays access prohibition And a means for notifying the central processing means of the fact.