JP2002215458A - Operating method and configuration for controlling access attribute of memory storage page - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a general purpose protection function for a system by preventing information such as a program to be loaded to a memory to be executed and a password for contrast from receiving the intrusions of an illegal intruder and a virus. SOLUTION: The method is provided for executing control of read, write, etc., from/to a part of section of a memory by means of a low level driver or a system chip set, section setting is carried out to the memory mainly by register setting operation, the operation mode of the section is also confirmed by actual operation work, and the section is made to have a function such as read only, write only, read once and write once.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a work method for controlling an access attribute of a memory storage page and a structure thereof. Alternatively, all the information from the hard disk is not received, and the information flow is monitored and controlled to provide a versatility protection function for system safety.

[0002]

BACKGROUND OF THE INVENTION Dynamic random access memories (DRAMs) appear in the form of stored pages (Paged Memory), i.e., DRAMs are constituted by continuous storage pages or continuity storage grids, e.g. If the size of the page is 4K bytes, the 16M DRAM is 4,000 storage pages of 4K size (000
Or FFF).

A CPU controls reading and writing of information from and to a DRAM via a chipset. Information to be executed in a hard disk is first written to the DRAM, and the CPU reads information from the DRAM to perform processing. Executing or processing the information by the CPU, then write the processed information to the DRAM, and then the hard disk reads the information from the DRAM,
AM operates sequentially on a storage page basis. In other words, in the operation of a general computer system, the DRAM simply stores and reads information.
Provides only one basic task.

[0004] Around the world, already in the stage of computer practicalization and digitization, many commercial activities have already been converted to the operation of information science and technology, enjoying the high efficiency, convenience and commercial opportunities brought by the Internet and intranet. At the same time, the security of computers and networks is becoming increasingly important. On the other hand,
Computer crime occurs as a phenomenon in which the level of technology, the level of rewriting means, and the number of crimes all increase as technology improves. As a result, many users will employ confidential systems to protect their important information. However, in any confidential system, the generated public key, confidential key, system body, or an extraly set password are first loaded into the DRAM after the confidential system is started, and then the confirmation is performed. . Therefore, DRAM is a device that always passes through the information flow of the system, and cannot receive all information from the CPU or hard disk and cannot execute selection. Information can be easily obtained or fixed. To give an example, an unauthorized intruder can get into the DRAM and obtain information such as the system's public key, secret key, and password, and certain software (for example, software ICE) can pass or stop the inspection work. And can easily get into the system.

After a virus on a magnetic disk or an optical disk is loaded into a DRAM, the CPU executes the virus to destroy or rewrite important parameters in the system. It affects the partition of the device and the authority to use the user system, etc.
The system is shut down or damaged, making it impossible to work normally, or causing it to operate abnormally. A typical virus protection program checks the virus code on a magnetic disk or optical disk, and if the user does not update it, some unknown virus can still enter the DRAM, run the CPU and destroy the system, and the virus DRAM Writing cannot be prevented, and an effective prevention method cannot be provided.

[0006]

DISCLOSURE OF THE INVENTION In order to solve the above-mentioned problems, the present invention provides a low-level driver or a system chipset for performing writing and reading to and from a memory area by register setting. To set the work area in the memory, and confirm the operation mode of the area by the actual operation, and read only (Read Only) or write only (Write Onl) in the area.
y) and write once (Read Once) and read once (Rea
d Once> and other operations and load them into memory (Load)
A memory that is equipped with versatile security protection means, so that programs such as programs waiting to be executed and passwords for confirmation are protected from intrusion of illegal intruders and viruses. It is a primary object of the present invention to provide a working method and structure for controlling the access attribute of a storage page.

Hereinafter, the design and technical principle of the structure of the present invention will be described in detail, and the features of the present invention will be described in more detail with reference to the accompanying drawings.

[0008]

FIG. 1 is a diagram showing a configuration of a DRAM according to the present invention. The DRAM has at least one
DRAM module 10 and memory controller 20
Each of the DRAM modules 10 has a plurality of DRAMs 11, and these DRAMs 11 have a plurality of storage pages 12 (only one DRA in FIG. 1).
M11). Further, the memory controller 20 has a controller 21 which controls access to each storage page 12, and a memory 22 (in this embodiment, a flash memory is used) is arranged therein. Saves the result of the setting operation (the operation method will be described later in detail). It also has a static random access memory 23 (hereinafter referred to as SRAM3), thereby storing a page quick look-up table, and having indication bits corresponding to a plurality of storage pages 12, whereby the storage pages 12 It stores whether it is executed by the normal access mode or the page working mode (the working method will be described in detail later).

The SRAM 23 is provided with a register (no sign).
May be replaced. The disadvantage of the register is that it has a large number of logic gates, occupies a large area in the IC, and cannot be used for a large capacity.
During design, the choice can be made according to the actual needs of the system.

The present invention provides a low-level driver or system chip 30 for controlling the DRAM 11 (see FIG. 3).
The read / write control is performed for the area of the DRAM 11 by the register setting operation A.
The register setting operation A first sets a section of the storage page 12 of the DRAM 11 to be controlled before processing the attribute of the storage page 12 of the DRAM 11, and After the system is switched on, first, the BIOS is executed, and the register setting operation A executes the setting at this time. Since the control right has not yet been issued to the operation system and the CPU 40 in this time zone, the register setting operation is completed. If
You will never be able to fix it again. The register setting operation A includes the following steps: Step A1: The attribute of the storage page 12 is defined by setting the area of the DRAM 11, the start position and the end position of the section, the number of storage pages, and the storage page size. And the like, and sets the area of the DRAM 11 that is directly controlled by the low-level driver. Step A2: The attribute of the storage page 12 is determined, and the correspondence buffer table (Table Of) is set according to the result of the setting.
By setting the Look-Aside Buffer (TLB), the attribute table of the single storage page 12 (003 shown in Table 1;
008) or a storage page section (see A02 to A08 shown in Table 1) and the DRAM 11
Is stored in the flash memory 22 set by the user. Step A3: A Fast Page Lookup Table (FPLT) is established according to the result of the setting, and is stored in the SRAM 23 of the DRAM 11 or a register. The page quick survey table FPLT specifies whether the storage page 12 is executed in the normal access mode or the page attribute work mode.

[Table 1]

Further, the actual operation work B has the following steps: Step B1: The page rapid check table FPLT stored in the SRAM 23 is checked and the storage page 12 is set to the normal work mode or attribute. Check if performed by page work mode. Step B2: The work attribute set in the storage page 12 is confirmed by checking the correspondence buffer table TLB stored in the flash memory 22. Step B3:
Perform attribute work.

In the case of a 16M DRAM module as an example, it can be partitioned into 4000 storage pages of 4K size (000 to FFF). The SRAM 23 also has 4000 bits corresponding to the storage pages 12 of the respective DRAMs 11, whereby the storage pages 12
Is performed in normal access mode or page work mode. If the bit of the SRAM 23 corresponding to a certain storage page 12 indicates “1”, it means that the storage page 12 belongs to the page attribute work mode, and the system checks the corresponding buffer table (TLB) to check the corresponding buffer page (TLB). The attributes of the page are checked (see Table 2).

For example, when the page rapid survey table FPLT of page 008 is "1", the work attribute of page 008 is checked by checking the corresponding buffer table TLB. Since the attribute of the storage page 12 is set to read only from Table 1, the storage page 008
Simply provides read service and prevents write operations from being performed.

[Table 2]

The low level driver is mainly a DRAM
To perform functions such as read only, write only, and write once. The setting and function of each attribute are shown below.

"A" Read Only: To set this area to read only, shut off the information bus or shut off the write enable. In other words, the write cycle signal is changed to the read cycle signal so that no information can be written in this area. However, CPU4
The write command with the value of 0 still operates normally, but even if the information bus is interrupted or the write enable is interrupted, an invalid write operation is performed.
40 will not interfere with the normal work. Alternatively, in the case of a write cycle, a preliminary signal is fed back from the system chip to the CPU 40 to notify that the write operation has already been completed, and the CPU 40 is in an inoperative state in the write cycle to specify the write. Do not let it run.

This read-only function can be used for security protection of the system. Since the position where the password is read from the DRAM 11 of the CPU 40 is set to read only, an intruder can rewrite or change the computer system by rewriting or changing it. You will not be able to enter.

In the case of using a virus as an example, when a program is to be stored in a set area in the DRAM 11 and is to be executed, this area is already set to a read-only function. Will no longer be written, preventing virus infection of executable files. In other words, the present invention prevents the intrusion of virus code at the entrance of the execution of the program, so that the program is not executed forever irrespective of whether or not the virus code exists in the computer system.

Only "B" writing: As shown in FIG.
The information terminal of the DRAM 11 is connected to the input terminal of the exchange switch 50, and the random number generator 60 is connected to the other input terminal of the exchange switch 50. The exchange switch 50 is controlled by a write-only control signal wo.ctl. When the write only control signal wo.ctl is “0”, the exchange switch 50 connects to the CPU 40 and transmits information to the DRAM 11. On the other hand,
When the write only control signal wo.ctl is “1”,
An exchange switch 50 connects to a random number generator 60;
The generated random number information is transmitted to the DRAM 11.

If this area is set for writing only,
The write only control signal wo.ctl is set to “1”,
At this time, the writing operation is the same as that of a general DRAM. If information is to be read from this area, the exchange switch 50 transmits random numeral information to the CPU 40 and reads invalid information. That is, the CPU 40
All reading commands below still work normally, but since the information to be read is random numeric information,
Since the reading operation is invalid, the normal operation of the CPU 40 is not affected.

"C" Read once: When this area is set to read once, the exchange switch 50 is controlled by a counter 70 as shown in FIG. When the first reading operation is performed, a normal normal reading operation is performed, and when the second reading command is issued, the number counter 70 (because the set total value is “1”) does not operate. , The exchange switch 50 is switched to be connected to the random number generator 60. At this time, the read information becomes an invalid random number.

"D" Write once: When setting this area to write once, the low-level driver first checks the start position and end position in this area and informs one of these two positions. If the low-level driver finds that the information has been written, the low-level driver does not allow the information to be written twice.

Alternatively, as shown in FIG. 3, when the number counter 70 records a write operation and finds that the write operation is performed once, the low-level driver prohibits the writing of information. Become like

Also, by setting the number of times by the low-level driver, the allowable number of times of writing in this area can be set, and N (where N is a set value) writing or N-time reading can be achieved.

[D] Corresponding rereading (see FIG. 4): When setting this area as corresponding rereading, first, at least one storage page 12 is set as a protected area (step a) and the use authority is set. And a storage page for storing important information such as a public key and a secret key (hereinafter referred to as a storage area) is copied to the protection area (step b). If it is found that a write operation has been performed in the reserve, the system immediately receives and disables it and first checks whether this change is legal (step c), In the case of writing, the changed storage area is copied to the protected area, and the system reads the information in the protected area and executes the operation (step d). If the system finds that the information to be written is wrong or should not be written, the system rewrites the information in the protected area to the storage area and restores the system to its original state (step e). To disable important information from being changed.

Rewriting corresponding to "E" (see FIG. 5): When setting this area as the corresponding rewriting, first, at least one storage page is set as a protection area (step a), and writing to each DRAM is performed. All the information to be stored is stored in the protected area (step b), and it is determined whether the information to be written is destructive to the system (step c). If it is determined that the information is destructive, the information to be written is located in a protected area so that it does not operate (step e>), and the DRAM is not immediately acted upon by correcting the contents. Provide a route to examine information multiple times.

For example, if the second storage page is used as a storage area for the use authority (or a public key or a secret key), the contents of the use authority to be modified each time are stored in the second area. And thereby release the right to use the appropriate resources to the user according to the new authority set by the system. In general terms, modifying usage rights can be of three types, such as system authorization, virus intrusion, or the entry of a worm by an intruder (Worm). The intrusion by the method of stack (Stack), the corrected position of the stack is a command such as interference or user authority check, and once corrected, copied to the second salt storage system, Will immediately respond and receive new entitlements, making it easy to read any of the resources in the system,
Alternatively, a stop signal for executing an access operation to information on the original card disk is changed to a hard disk information deletion command or a hard disk format command, thereby destroying the entirety of the information on the hard disk and preventing the system from being operated normally.

Therefore, in the case of the corresponding re-read attribute of the present invention, information for recognizing the user authority of the system is placed in a protected area (here, described in the tenth storage page), and after the use authority is corrected, First, save it in the protected area on the tenth storage page and determine that it is a legitimate correction (eg, determine whether the stack push and pop commands are balanced or overflowed). Yes), if legal, first
The information in the protected area in the 0 storage page is moved to a second page, where it is received by the computer and operated according to the modified contents. If not, keep it in a protected area, isolate it from the system, and eliminate the risk of tampering or virus entry.

In the setting of the respective attributes, when the exchange switch 50 is switched to connect to a random number generator, an invalid random number is transmitted to the CPU, and the CPU sets the attribute setting value to the DRAM. Prevents execution of various opposing functions (for example, the CPU cannot execute writing to the DRAM in the read-only attribute). In other words, at this time, the CP
Although U and DRAM are isolated, other control units in the system can still access normally.

The techniques, drawings, programs, and control methods disclosed above are merely examples of preferred embodiments of the present invention, and may be modified or changed without departing from the scope of the claims of the present invention. Improvements and diversions are possible,
All of these are included within the scope of the present invention.

[0030]

As described above, the working method for controlling the access attribute of the memory storage page and the structure thereof according to the present invention are as follows.
Attribute setting can be performed for storage pages, and DRAM
Can improve the work function, not receive any information from the CPU or hard disk, monitor and control the information flow, provide general protection function of system security,
There is an effect that a solution and a measure can be provided for a problem that the conventional safety system cannot protect all of the DRAM.

[Brief description of the drawings]

FIG. 1 is a diagram showing an embodiment of a working method for controlling an access attribute of a memory storage page and a configuration of the working method according to the present invention;
FIG. 3 is a diagram showing a configuration of M.

FIG. 2 is a flowchart of the method of the present invention.

FIG. 3 is a diagram showing hardware for setting attributes according to the present invention.

FIG. 4 is a flowchart illustrating steps of a corresponding reread attribute according to the present invention.

FIG. 5 is a flowchart showing steps of a corresponding rewrite attribute according to the present invention.

[Explanation of symbols]

 Reference Signs List 10 DRAM module 11 DRAM 12 Storage page 20 Memory controller 21 Controller 22 Memory (flash memory) 23 SRAM 30 System chip 40 CPU 50 Exchange switch 60 Random number generator 70 Number counter

Claims (16)

[Claims] The present invention has a register setting process and a work process. The register setting process is performed by setting a start position, an end position, a storage page number, and a storage page size of a corresponding section. Specifying the area of the DRAM which is directly controlled by the level driver, defining the attributes of the storage page by setting the DRAM area, and setting the corresponding buffer table based on the result of the setting. Specifying the attribute table or storage page section of a single storage page, and determining the attribute of the storage page, and setting the corresponding page by setting the page quick survey table based on the result of the register setting process. Specifying whether the page should be run in normal access mode or page attribute work mode. The actual work process checks the page rapid survey table and the correspondence buffer table, and reads / writes only or reads / writes the DRAM based on the stored page attribute records of these two tables, or reads / writes or responds to the DRAM. A work method for controlling an access attribute of a memory storage page, wherein the work attribute is set for work such as repair. 2. The read-only function shuts off an information bus or shuts off a write enable, and disables writing of information to a corresponding area by changing a write cycle signal to a read cycle signal. 2. The method according to claim 1, wherein the access attribute of the memory storage page is controlled. 3. When the read-only function encounters a write cycle, a signal is fed back from the system chip to the CPU, and the write command is disabled by not operating the CPU. 2. A method for controlling an access attribute of a memory storage page according to claim 1. 4. The setting of the attribute of the corresponding re-reading includes a step a of setting at least one storage page as a protected area, and saving important information such as a use right, a public key, and a secret key. (B) copying the storage page to the protected area; determining whether the operation of the storage page for writing and storing important information is legal; if the operation is legal, copying the stored page to the protected area, and Operate by reading information in the protected area, but in case of illegal writing, wrong written information or operation that can not be written, the system saves information in the protected area with important information Recovering to refer to the contents in the storage page and returning the system to its original state so as not to be changed. C. Working method of controlling access attribute memory storage page according to Motomeko 1. 5. The setting of the attribute of the corresponding rewrite includes a step a of setting at least one storage page as a protected area, and a step b of storing information to be written in the protected area.
If the information to be written determines the possibility of damaging the system, and if it is not destructive, move this information to a storage page specified by the system and save it.
2. A method according to claim 1, further comprising the step of: (c) preventing the DRAM from being acted upon immediately by changing the contents so as to prevent the operation from being continued in the protected area and providing a path for checking the information twice. 3. A method for controlling access attributes of a memory storage page according to claim 1. 6. The attribute of the write-only function is controlled to switch an exchange switch to a random number generator by a write-only control signal, generates random number information, and transmits it to a CPU, thereby invalidating information to be read. 2. The method according to claim 1, wherein the access attribute of the memory storage page is controlled. 7. The attribute of the first reading function is controlled by a number counter, and at the time of the first reading operation,
Assuming this is a normal normal read operation, when issuing another read command, do not allow the counter to allow this operation to occur, switch the exchange switch to a random digit generator, and perform another read command. 2. The operation as an invalid random number.
3. A method for controlling access attributes of a memory storage page according to claim 1. 8. The one-time writing function is performed by detecting a start address of a zone and an end address of a zone by a low-level driver, so that information is written to one of the two. 2. The work method for controlling an access attribute of a memory storage page according to claim 1, wherein the writing twice is prohibited. 9. The one-time writing function is executed by counting the number of times of the writing operation by a number counter, and when it is found that the data is already written once, the low-level driver can write the information. 2. The work method for controlling an access attribute of a memory storage page according to claim 1, wherein the writing twice is prohibited. 10. A controller including at least one DRAM having a plurality of storage pages, a controller capable of controlling access to each storage page, and internally storing a result of the setting process disclosed in claim 1, and a storage. An SRAM having indicator bits corresponding to a plurality of memory pages for indicating whether a page is executing in a normal access mode or a page operation mode; an input terminal connected to an information terminal of the DRAM; A memory controller having an exchange switch connected to the random number generator and controlling the switching of the switch by a number counter or a write-only control signal, wherein the access attribute of the memory storage page is controlled. Constitution. 11. The configuration for controlling the access attribute of a memory storage page according to claim 10, wherein the page quick survey table is stored in a register. 12. The attribute of the write-only function is such that an exchange switch is switched to a random number generator by a write-only control signal, random number information is generated, and information to be read by transmitting to a CPU is invalid information. 11. The configuration for controlling an access attribute of a memory storage page according to claim 10, wherein: 13. The attribute of the one-time reading function is controlled by a number counter. When the first-time reading operation is performed, the attribute is regarded as a general normal reading operation, and when the second-time reading command is issued, 11. The method according to claim 10, wherein the counter does not allow this operation to occur, the exchange switch is switched to a random number generator, and the operation of reading once again becomes an invalid random number. A configuration for controlling an access attribute of the memory storage page described. 14. The one-time writing function is performed by detecting a start address of a zone and an end address of a zone by a low-level driver, so that information is written to one of the two. 11. The configuration for controlling an access attribute of a memory storage page according to claim 10, wherein writing twice is prohibited. 15. The one-time writing function is performed by counting the number of times of the writing operation by the number counter, and when it is found that the data is already written once, the low-level driver can write the information. 11. The configuration for controlling an access attribute of a memory storage page according to claim 10, wherein double writing is prohibited. 16. The number counter may be set by a low-level driver, and may have an attribute setting function that can determine a writable or readable number and can set the number of times of reading or writing to a predetermined number. The configuration for controlling an access attribute of a memory storage page according to claim 10, wherein: