JPH04160583A - Single-chip microcomputer - Google Patents

Abstract

PURPOSE:To prevent illegal access to a secret zone by comparing the address value of one of passwords with a value stored in a shift register and allowing access to a PROM only when they match each other. CONSTITUTION:Plural passwords are stored in the secret zone 5a of the PROM (Programmable Rom) 5 used as a data memory before ad a password read out of the PROM 5 corresponding to the frequency of input of a password which is inputted from outside is selected; and the value of the password is operated and compared with data inputted to the shift register 20 and only when they match each other, a test mode is allowed by a test circuit 17. Consequently, illegal data access which is caused when data access to the conventional secret zone is freely performed since the test mode is realized is inhibited and high-level security is realized.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a single-chip microcomputer,
In particular, the present invention relates to a single-chip microcomputer that integrates memory functions and computer functions on a single semiconductor substrate.

[Conventional technology]

Due to recent advances in LSI manufacturing technology, the field of single-chip microcomputers (hereinafter referred to as single-chip microcomputers) has become highly integrated, and the cost per unit function has been significantly reduced.

Traditionally, magnetic cards have been mainly used in financial institutions such as banks, but magnetic cards have a small storage capacity and are problematic in terms of security, so they have recently become more susceptible to unauthorized use.
Many crimes such as forgery occur frequently and have become a major social problem. Therefore, as an alternative to this magnetic card, an IC card equipped with a single-chip microcomputer has appeared, and large-scale experiments are underway to put it into practical use both domestically and internationally.

This IC card has a much larger storage capacity than a magnetic card, and since it has a built-in computer function, it is extremely reliable in terms of security.

Generally speaking, an IC card equipped with a single-chip microcontroller has UVEP ROM (UVEP ROM) in most of the data memory.
Ult, ra-Violet Erasable Pr
ogrammable ROM) or EEP R
OM (Electrical Erasable Pr
(UVEPROM and EEPROM will be collectively referred to as PROM hereinafter), and its child memory is divided into several areas and access to them is managed.

When using an IC cart as a cash cart or credit card issued by a financial institution such as a bank, some of this divided seek memory is stored in a secret zone (
Secret Zone), bank account number, I
It is used to store highly confidential data such as D numbers and secret numbers.

This secret zone is an important part of preventing unauthorized use and counterfeiting of IC cards, and during use, access to this area is controlled by software, and access to this area is made possible in special cases. There is.

FIG. 6 shows a block diagram of a conventional single-chip microcomputer. In the figure, a memory unit 3 is a read-only or read-write memory used for storing user programs and data. The internal bus 4 transfers addresses and data in a time-division manner, and the internal bus 8 is a time-division bus used to transfer addresses and seek to the internal bus 4 via the external terminal 10 during test mode.

A central processing unit (hereinafter referred to as CPU) 2 performs a seek process according to a program stored in a memory unit 3. The peripheral section 6 is composed of a boat and the like for communicating with the outside of the chip, and transmits data via the internal bus 4 to an external terminal 6.
It has the function of inputting and outputting to a.

PROM5 consists of UVEPROM or EEPROM as a data memory, and a secret memory is stored in the memory.
It has a zone 5a, which stores cart ID numbers, secret numbers, account numbers, etc., and reads and writes them according to instructions from the CPU 2. Access management to this secret seek 5a is performed by the user using software.

Terminal] 5 has a level of “1” in test mode.
Since the output of the inverter 7 becomes '0'' at this time, only the PROM 5 is connected to the internal bus 4, and access to the PROM 5 can be made directly from outside the chip.

The terminal 10 is a terminal for inputting and outputting addresses and data to the outside via the internal bus 8, and is connected to the internal bus 4.

The terminal]2 is a terminal that outputs the CPU clock1 outputted from the CPU2. Terminal 13 is a terminal that resets CP-5=U2, and when its level is "1"'
At this time, the reset signal 14 becomes '1'' and resets the CPU 2.

Next, the operation during testing will be explained. Keep the level of terminal 13 at "1", set terminal]5 to "']"', and set terminal 1 to
3 in synchronization with the falling edge of CPU clock]-1.
At this time, the test signal 9 becomes ``1'''' and the output of the inverter 7 becomes ``O'', so the CPU 2
, the memory section 3 and the peripheral section 6 are electrically separated from the internal bus 4. Therefore, the one connected to internal bus 4 is P
Only ROM5 is available.

In this state, an address and a seek are input to the PROM 5 via the external terminal 10 and the internal bus 8 to read and write data. At this time, by inputting the address of the secret seeker 5a, it is possible to easily access the theta in the zone. Therefore, seek read and write operations can be easily performed.

As mentioned above, in conventional single-chip microcomputers, all access control to the secret zone where confidential data is stored is performed by the user's software. When such a single-chip microcomputer is installed on a card, it is possible to illegally access data in the secret zone by using the test mode. Furthermore, if an electrically erasable read-only memory (EEPROM) is used as the data memory, when a write command is executed, the FR
Since the voltage for writing is automatically generated inside the OM,
Illegal writing to the secret zone is easily possible.

[Problem to be solved by the invention]

As mentioned above, in conventional single-chip microcontrollers that manage access to the secret zone, which is an access protection area in data memory, all access management to the built-in PROM is done by software, so test mode is not possible. The disadvantage is that the data in the secret zone can be easily accessed at times, and there is a risk that the data in the secret zone may be misused due to unauthorized access, or that the data may be intentionally rewritten.

An object of the present invention is to provide a single-chip microcomputer that can prevent unauthorized data access to a secret zone.

[Means to solve the problem]

The single-chip microcomputer of the present invention includes a PROM that stores a plurality of passwords, a shift register, a shift register that stores data serially input from the outside, and a first register that counts the number of input bits to the shift register. a counter; a second counter that counts the number of times data is input to the shift register; and an address value of one password among the plurality of passwords that corresponds to the value of the second counter and that is stored in the shift register. The present invention is characterized by comprising a comparing means for comparing the values and permitting access to the PROM only when they match.

〔Example〕

Next, a first embodiment of the present invention will be described using FIG. 1. FIG. 1 is a block diagram of a single-chip microcomputer according to a first embodiment of the present invention. First, the configuration will be explained. The single-chip microcomputer of this embodiment has a configuration in which a test circuit 17 is added to the circuit configuration of the conventional example shown in FIG.

Therefore, the test circuit 17 will be mainly described below.

The test circuit 17 receives a clock signal 11 output from the CPU.
Data is serially inputted from one external terminal in synchronization with , and the above input data is compared with the value of one of the multiple passwords stored in the secret zone 5a in the PROM 5, which is addressed by the address signal 100. It has a function that allows test mode only if the two conditions match.

The detailed configuration and operation of the test circuit 17 will be described below with reference to FIG.

The test circuit 17 includes a shift register 20. Comparison circuit 22.
Counter 24. This block is composed of a counter 101. The shift register 20 receives the reset signal 14 “
0'', and when the shift permission signal 28 is II I II, C
10-bit serial data on the signal line 18 is input in synchronization with the falling edge of the PU clock 11.

The comparison circuit 22 compares the output of the shift register 20 with the value of the password 23, which is one of the plural passwords stored in the secret zone 5a in the PROM 5, which is addressed by the address signal 100 output from the counter 101, and finds a match. The test signal 9 is output only when this happens.

The counter 24 is a circuit that controls the shift operation of the shift register 20, and is synchronized with the rising edge of the basic clock 11.
Only when test mode signal ] 6 is PA 1°', CPU 11
, and outputs a shift permission signal 28 to the shift register 20. Further, the counter 24 is cleared and stops operating when the test mote signal 16 is 0''.

The counter 101 counts the overflow signal in synchronization with the rise of the overflow signal 102 of the counter 24 only when the reset signal]4 is "o", and outputs the stored value as an address signal]00 to the PROM 5a that stores multiple passwords. . This counter 101 is cleared when the reset signal 14 is "1" and stops operating.

The operation of the test circuit 17 will be explained below with reference to the waveform diagram in FIG. First, the test mode signal 16 is set to "o" while the signal 14 to the reset 1 remains ]''°.Next, the test signal mode 16 is set to 1°', and the reset signal 14 is set to the falling edge of the CPU clock]1. 0″
shall be. Then, in synchronization with the rise of the CPU clock 11, eight hit data are serially inputted from one external terminal. At this time, the counter 24 is CPU clock 1
1, the shift permission signal 28 is set to ``]'' and is output to the shift register 20.

The counter 24 receives a shift permission signal 2 after counting nine times.
8 is set to 0'' and stops. Further, the counter 101 counts up once in accordance with the OHA flow signal 102 of the counter 24.

When the shift permission signal 28 is 1'', the shift register 20 performs a shift operation eight times in synchronization with the falling edge of the CPU clock]1, and then transfers the permission signal 28 to shift 1 to 0''.
Therefore, the operation is stopped at shift 1. Further, when the reset signal 14 is at 1°', the stored value is cleared.

After receiving 8-bit serial data, shift register 2
The stored value of 0 is output to the comparison circuit 22. Comparison circuit 22
is the password 2 whose address is specified by the address signal 100 output from the counter 101 among the plurality of passwords stored in the secret zone 5a in the PROM 5.
3 and the input data to the shift register 20, and if the values are the same, a test signal 9 is output.

If the input data from the outside of the chip does not match the password 23, it is necessary to input different data from the outside again to enter the test mode. At this time, the external terminal 15 is connected in synchronization with the falling edge of the CPU clock]1-.
o'', then set to 1''' in synchronization with the falling edge of the CPU clock [1], and then inputting data in synchronization with the rising edge of the PCU clock [1].

When external terminal 15 is set to “O’”, test mode signal 16
becomes 0"°, and the counter 24 is cleared. Then, the shift permission signal 28 becomes 1', and the shift register 2
0 enables external data input.

Further, when the external terminal 15 is set to ``'', the test mode signal 16 becomes ``1'', allowing the counter 24 to operate. In this way, the counter 24 checks whether a seek input from outside the chip is possible again.
In order to output the counter], 01 increases by 1 count I and becomes the stored value 2.

In other words, the counter 101 counts the number of theta input to reset 1 later from outside the chip.

Next, the configuration and operation of the counter 24 will be explained with reference to FIG. The counter 24 includes a 4-hit up counter 3Q, an AND gate 31. It consists of a NAND gate 32.

When the test mode signal 16 is "o", the up counter 30 is cleared and stops operating. When the test mode signal 16 is '1', the counter 30 counts up in synchronization with the rise of the output of the AND gate 31.

That is, when the test) mode signal 16 is 0'', the NAND
Since the output of the gate 32 is 0'', the AND gate 31 outputs the CPU clock 11 as it is, and the counter 30 counts the CPU clock.

When the counter 24 counts the CPU clock 1 nine times, both the third bit and the Oth bit of the counter 24 become 1'.
', so the output of the NAND gate 32 becomes '0' and the shift permission signal 28 becomes 'o'. Therefore,
The output of the AND gate 31 also becomes "0'", and the counter 30 stops counting.

When inputting data again from outside the chip, first set the external terminal 15 to 0'' in synchronization with the falling edge of the CPU clock 11, then set it to 1'' in synchronization with the falling edge of the CPU clock 11.
After that, data is input in synchronization with the rising edge of the CPU clock 11.

When the external terminal 15 is set to low, the test mode signal 16 becomes 0"' and the counter 24 is cleared. Then,
The shift permission signal 28 becomes '1'', and the shift register 2
0 enables external data input. Further, when the external terminal 15 is set to 1'', the test mode signal 16 becomes ``1'', and the counter 24 becomes operable.

In this embodiment, since the address of the password stored in the built-in PROM changes depending on the number of data inputs from outside the chip, it becomes more difficult to detect 8-bit data that can realize the test mode. Therefore, it becomes more difficult for a third party to execute the test mode.

Next, a second embodiment of the present invention will be described using FIG. 3. FIG. 3 is a block diagram of the test circuit. For the test circuit 17 of the first embodiment shown in FIG. The difference is that it includes means for bit-inverting the value and outputting it to the comparator circuit 22. Since there is no difference in other configurations and operations, the differences will be mainly explained.

The latch 51 is a 1-bit flag that inverts the stored value when the overflow signal 102 output from the counter 24 is 1'', outputs the value to the inversion circuit 52, and outputs the value to the reset signal 14.
When is 1, it is cleared to O. This latch 51 can be easily configured with a master-slave configuration latch such as a flip-flop.

The inversion circuit 52 is a circuit that inverts and outputs the value of the password 23 according to the output value of the latch 51, and includes one 3-state buffer and one 3-state buffer corresponding to each bit of the password 23.
It consists of three 3-state inverters.

A 3-state buffer 52a and a 3-state inverter 52b correspond to the seventh bit of the password 23. The 3-state buffer 52a outputs the seventh bit of the password 23 when the output of the latch 51 is 0'',
1", the output becomes high impedance. Also, when the output of the latch 51 is II I II, the 3-state inverter 52b outputs the inverted value of the 7th bit of the password 23, and the output becomes high impedance. When the output is high impedance.

Therefore, the 3-state buffer 52a and the 3-state buffer 52a
Since the output of the inverter 52b is wired,
When the output of the latch 51 is "1", the inversion circuit 22 outputs a value obtained by inverting the output of the password 23. Further, when the output of the latch 51 is II OII, the inversion circuit 22 outputs the output value of the password 23 as is.

Next, the operation will be explained. The test circuit 17a inputs 8-bit data to the shift register 20 and then transfers the data to the comparison circuit 2.
Output for 2. The counter 101 is the counter 24
When the overflow signal 102 outputted by is "O", it counts 1.

Therefore, the counter 101 counts the number of times data is input to the shift register 20 after being reset, and outputs the number of times as an address signal 100 to the PROM 5a. The latch 51 receives an overflow signal 102 output from the counter 24.
When is 0, invert the value. When the content of the counter 24 becomes 9, the overflow signal 102 becomes 'O', so the latch 51 outputs '1°' if the number of data inputs to the shift register 20 is an odd number, and outputs II OII if the number of data inputs to the shift register 20 is an even number. It turns out.

For example, in the case of the first notheta input to the shift register 20, the password 23 is read from address 1 of the PROM 5a, and the value whose bits are inverted by the inversion circuit 52 is compared with the input value of the shift register 20.

Compared to the test circuit of the first embodiment, this embodiment not only changes the password read from the PROM according to the number of inputs to the shift register, but also manipulates the password value according to the number of inputs. Therefore, it is difficult to detect an 8-bit data that can realize the test mode.

Therefore, it is more difficult for a third party to implement the test mode than in the first embodiment.

〔Effect of the invention〕

As explained above, in the present invention, a plurality of passwords are stored in the secret zone of the PROM conventionally used as a data memory, and a password to be read from the PROM is selected depending on the number of passwords input from the outside. , further manipulate the value of the second password,
By adding a test circuit that allows test mote only when the result of comparison with the seek input to the shift register matches, data access to the secret zone was previously freely performed by realizing test mote. This has the effect of prohibiting unauthorized data access and achieving a high level of security.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a single-chip microcomputer in the first and second embodiments of the present invention, FIG. 2 is a block diagram of a test circuit in the first embodiment, and FIG. 3 is a block diagram of a test circuit in the first embodiment.
4 is a block diagram of the counter in the test circuit, FIG. 5 is a waveform diagram showing the operation timing of the test circuit, and FIG. 6 is a block diagram of a conventional single-chip microcomputer. be. 1... Single-chip microcomputer, 2...
・CPU, 3...Memory section, 4.8...Internal bus,
5...PROM, 5a...Secret zone, 6
... peripheral area, 7. '1.03... Inverter, 9 ・
Test signal, 10, 12, 1.3, 15.19, 6.1
...External terminal, 1] - CPU clock, 14... Reset signal, ]6... Test mode signal, 1.7, 1
．． 7a...Test circuit, 18...Signal line, 20...
- Shift register, 22... Comparison circuit, 23... Password 1~. 24...Counter, 28...Shift permission signal, 30...Counter, 31...AND gate,
32...NAND gate, 5]...Latch, 52...
- Inversion circuit, 52a... 3-state buffer, 52
b...3-state inverter, ]00...address signal, 101...counter, 102...overflow signal.

Claims (2)

[Claims] 1. A PROM that stores a plurality of passwords, a shift register, a shift register that stores data serially input from the outside, a first counter that counts the number of bits input to the shift register, and a first counter that counts the number of bits input to the shift register. When a second counter that counts the number of data inputs is compared with the address value of one of the plurality of passwords corresponding to the value of the second counter and the value stored in the shift register, and they match. 1. A single-chip microcomputer, comprising comparison means for permitting access only to the PROM. 2. 2. The single-chip microcomputer according to claim 1, further comprising means for inverting said password in response to input data to said shift register and inputting said password to said comparing means.