JP3205998B2 - Single chip microcomputer - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a single-chip microcomputer having a memory function and a computer function integrated on a single semiconductor substrate, and more particularly, to data corresponding to a password stored in a built-in PROM. The present invention relates to a single-chip microcomputer in which an internal PROM can be directly tested externally only when externally input.

[Conventional technology]

In recent years, due to advances in LSI manufacturing technology, high integration has been progressing in the field of single-chip microcomputers (hereinafter, also referred to as single-chip microcomputers), and the cost per unit function has been significantly reduced.

In the past, magnetic cards were mainly used in financial institutions such as banks, but magnetic cards have a small storage capacity and have security problems, and recently, unauthorized use,
Many crimes, such as counterfeiting, occur frequently and have become a major social problem. Here, an IC card equipped with a single-chip microcomputer has appeared as an alternative to the magnetic card, and large-scale experiments are being carried out in Japan and overseas for practical use. This IC card has a storage capacity several steps larger than that of a magnetic card, and has a built-in computer function in the card, so that it has extremely high reliability in terms of security.

Generally, in an IC card equipped with a single-chip microcomputer, most of the data memory has a UVEPROM (Ultra-
Violet Erasable Programmable ROM) or EEPROM (El
(Electrical Erasable Programmable ROM) is used (hereinafter referred to as PROM when including UVEPROM and EEPROM), and its data memory is divided into several areas to manage access.

When using an IC card as a cash card or a credit card at a financial institution such as a bank, a part of the divided data memory is used as a secret zone (Secret zone).
Zone), which is used to store highly sensitive data such as bank account numbers, ID numbers, and secret numbers.

The secret zone is an important part of preventing unauthorized use and forgery of the IC card.When using this IC card, access to the area is controlled by software, and it is possible to access the area only in special cases. It has become. However, in the test mode,
The entire area of the built-in PROM can be easily accessed directly from the outside, and the value in the secret zone can be read and abused or changed intentionally.

FIG. 14 is a block diagram of an example of a conventional single-chip microcomputer. In this figure, a memory unit 3 is a read-only or read-write memory used for storing user programs and data, an internal bus 4 is a bus for transferring addresses and data in a time-division manner, and an internal bus 8
Is a time division bus used for transferring addresses and data to the internal bus 4 via the external terminals 10 in the test mode.

A central processing unit (hereinafter, referred to as a CPU) 2 performs data processing according to a program stored in a memory unit 3, and fetches and executes a program from outside the chip via an internal bus 8 and an external terminal 10 in a test mode. The peripheral unit 6 includes a port for performing communication with the outside of the chip, and outputs data input through the internal bus 4 to the external terminal 61 and inputs data from the external terminal 61 to the internal bus 4. It has the function to output to.

The PROM 5 is composed of a UVEPROM or an EEPROM as a data memory, has a secret zone 51 in the memory, stores an ID number of the card, a secret number, an account number, etc., and performs reading and writing according to instructions of the CPU 2. . The user manages access to the secret zone 51 by software.

The terminal 15 is an external input terminal which is set to "1" in the test mode. At this time, since the output of the inverter 7 is "0", only the PROM 5 is connected to the internal bus 4 and access to the PROM 5 is performed by the chip. Directly available from outside, terminal 10
Is an input / output terminal for externally inputting addresses and data via the internal bus 8 and is connected to the internal bus 4;
Terminal to output CPU clock 11 output by CPU2, terminal 13
Is a terminal for resetting the CPU2. When this terminal is "1", the reset signal 14 becomes "1" and resets the CPU2.

 The operation of this system during a test will be described.

First, the terminal 13 is changed to the terminal 15 “1” while the terminal 13 is set to “1”.
To “0” in synchronization with the fall of the CPU clock 11.
At this time, the test signal 9 becomes "1" and the output of the inverter 7 becomes "0", so that the CPU 2, the memory section 3, and the peripheral section 6 are electrically disconnected from the internal bus 4. Therefore, internal bus 4
Is connected only to PRO5M.

In this state, an address and data are input to the PROM 5 via the external terminal 10 and the internal bus 8 to read and write data.

At this time, if the address of the secret zone 51 is input, the data in the zone can be easily accessed, so that data reading and writing can be easily performed.

As described above, in the conventional single-chip microcomputer, access control to the secret zone storing secret data is entirely performed by the user's software. When such a single-chip microcomputer is mounted on a card, illegal data access to the secret zone can be performed by using the test mode. Furthermore, if an electrically erasable read-only memory (EEPROM) is used as the data memory, a write voltage is automatically generated inside the PROM when a write instruction is executed. On the other hand, improper writing can be easily performed.

FIG. 15 is a block diagram of another conventional single-chip microcomputer.

This microcomputer IC has a PROM
Instead, an EEPROM 5a is used, and the EEPROM 5a includes a write circuit 52 controlled by a program signal 42.

The PROM 5a is composed of an EEPROM as data memory, has a secret zone 51 in the memory, and has a card ID.
A number, a secret number, an account number, and the like are stored, and are read and written by a command from the CPU 2. At the time of writing, the program signal 42 is output to the write circuit 52 in the PROM 5a. Next, the operation of this microcomputer during a test will be described.

The terminal 15 is set to 1 while the terminal 13 remains 1, and the terminal 13 is set to 0 in synchronization with the fall of the CPU clock 11. At this time, the test signal 9 becomes 1 and the output of the inverter 7 becomes 0, so that the memory section 3 and the peripheral section 6 are electrically disconnected from the internal bus 4. Therefore, the PROM 5a is connected to the internal bus 4.
And only CPU2.

In this state, an instruction and data are input according to the address output from the CPU 2 via the external terminal 10 and the internal bus 8, and the CPU 2
Data is read from and written to the PROM 5a by executing the program. This writing is performed according to a command from the CPU 2, and at this time, the CPU 2 outputs the program signal 42 to the write circuit 52 in the PROM 5a.

[Problems to be solved by the invention]

In the conventional data memory described above, a single-chip microcomputer that manages access to the secret zone, which is an area of access protection, has a built-in PROM or EE.
Since all access control to the PROM is performed by software, it can be easily accessed in the test mode, and there is a risk that unauthorized access will result in misuse of data in the secret zone or intentional rewriting of data. There was a drawback of having sex.

An object of the present invention is to provide a single-chip microcomputer which eliminates such drawbacks and adds a simple test circuit, thereby eliminating unauthorized access in a test mode and easily obtaining more reliable security. Is to provide.

[Means for solving the problem]

The configuration of the present invention comprises a central processing unit on a single semiconductor substrate,
In a single-chip microcomputer in which a storage unit, a peripheral unit, and a PROM are integrated and a test is performed on the PROM by a test circuit, a plurality of passwords are stored in the PROM, and the test circuit is externally provided. A shift register for temporarily storing serially the input data consisting of the two first and second fields, an encryption circuit for encrypting the data of the second field of the output of the shift register, and the shift register Addressed in the first field of the output of the PR
A comparison circuit for comparing one of a plurality of passwords read from the OM and a value encrypted by the encryption circuit, and a test from the outside to the PROM only when the comparison value of the comparison circuit is equal Is made possible.

Another feature of the present invention is that a central processing unit, a memory unit, a peripheral unit and an electrically writable EEPROM are provided on a single semiconductor substrate.
In a single-chip microcomputer in which an OM is integrated and a test is performed on the EEPROM by a test circuit, a password is stored in the EEPROM, and the test circuit temporarily stores data input from the outside in a serial manner. A shift register, a counter for counting the number of bits input to the shift register and controlling the shift register, and a comparison circuit for comparing the value of the password and the value input to the shift register. Only when the comparison values are equal to each other, a test to the EEPROM can be performed from the outside, and the password is updated by writing the value input to the shift register to the EEPROM again.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a single-chip microcomputer according to a first embodiment of the present invention. The components of the single-chip microcomputer of this embodiment other than the newly added test circuit 17 are the same as those of the conventional example shown in FIG. 14, and the test circuit 17 will be mainly described.

In the figure, a test circuit 17 inputs data consisting of two fields (field 1 and field 2) serially from an external terminal 19 in synchronization with a clock signal 11 output from the CPU, and specifies a PROM 5 for addressing in field 1.
Has a function of comparing one value of a plurality of passwords stored in the secret zone 51 in the field 2 with the field 2 and permitting the test mode only when they match.

FIG. 2 is a block diagram showing the configuration of the test circuit 17 of FIG.

The test circuit 17 includes a shift register 20, an encryption circuit 21, a comparison circuit 22, and a counter 24. Shift register 20
When the reset signal 14 is 0 and the shift enable signal 28 is 1,
In synchronization with the falling edge of the CPU clock 11, 10-bit serial data (composed of a 2-bit field 1 and an 8-bit field 2) on a signal line 18 is input. The encryption circuit 21 encrypts the field 2 stored in the shift register 20 and outputs it.

The comparison circuit 22 compares the output of the encryption circuit 21 with the value of the password 23 which is one of a plurality of passwords stored in the secret zone 51 in the PROM 5 addressed by the address signal 40 corresponding to the field 1, The test signal 9 is output only when they match. The counter 24 is a circuit for controlling the shift operation of the shift register 20, and includes a basic clock 11
Only when the test mode signal 16 is 1 and the reset signal 14 is 0, the CPU clock 11 is counted and the shift register 20
Is output.

 Next, the operation of the test circuit 17 will be described.

First, the test mode signal 16 is kept while the reset signal 14 is kept at 1.
Is set to 0. Next, the test signal mode 16 is set to 1 and
Reset signal 14 is set to 0 in synchronization with the fall of CPU clock 11.
And External pin 1 is synchronized with the rising edge of CPU clock 11.
Input 10-bit data serially from 9.

At this time, the counter 24 counts 11 times in synchronization with the CPU clock 11, sets the shift permission signal 28 to 1, and outputs it to the shift register 20. After counting 11 times, the counter 24 sets the shift permission signal 28 to 0 and stops.

When the shift enable signal 28 is 1, the shift register 20
After performing the shift operation ten times in synchronization with the falling of the U clock 11, the shift operation is stopped when the shift permission signal 28 becomes 0. When the reset signal 14 is 1, the stored value is cleared to 0. In the 10-bit input data, the upper 2 bits correspond to field 1 and the remaining 8 bits correspond to field 2. After receiving the 10-bit serial data, the field 2 of the stored value of the shift register 20 is encrypted by the encryption circuit 21 and output to the comparison circuit 22.

The comparison circuit 22 compares the password stored in the secret zone 51 in the PROM 5 with the password 23 addressed by the address signal 40, and outputs the test signal 9 when these values are the same.

The operation timing of the test circuit 17 is shown in FIG.

Next, the configuration and operation of the counter 24 will be described with reference to FIG.

The counter 24 includes a 4-bit up counter 30, an AND gate 31, and a NAND gate 32. When the reset signal 14 is 1, the up counter 30 is cleared and stops operating.

When the reset signal 14 is 0 and the test mode signal 16 is 1,
The counter 30 counts up in synchronization with the rising of the output of the AND gate 31. After counting 11 times, 3rd bit = 1st bit = 0th bit = 0, so the NAND gate
The output of 32 becomes 0. Therefore, the output of the AND gate 31 is also 0
And the counter 30 stops counting.

 Next, the configuration of the encryption circuit 21 will be described with reference to FIG.

The encryption circuit 21 outputs the 8-bit data after performing the following data conversion on the 8-bit input data.

(1) Bits 0 and 7 are interchanged, bit 7 is inverted, and bit 0 is output as it is.

(2) Bit 6 is output as it is after inversion.

(3) Bits 4 and 5 are interchanged and then inverted and output.

(4) Bit 1, bit 2, and bit 3 are output as they are.

 For example, when the input is FFH, the output is 0FH.

Since the password is 8 bits long, 2 ⁸ = 256
There are common patterns. In addition, since the input data is scrambled by the encryption circuit and one of the four passwords is used, it becomes more difficult to detect a 10-bit pattern that can realize the test mode, and a third party performs a test. Mode execution becomes more difficult.

In this embodiment, by adding the test circuit 17 composed of simple hardware, it is not easy to realize the test mode by a third party, and the secret
Unauthorized access to the data in the zone 51 and loss of the data can be prevented, and a high level of fail-safe is realized.

FIG. 6 is a block diagram of a test circuit 17a used in a single-chip microcomputer according to a second embodiment of the present invention.

The test circuit 17a in the single-chip microcomputer of the present embodiment is different from the test circuit 17 of the first embodiment in that after encrypting all 10-bit serial input data, an address signal for designating a plurality of passwords built in the PROM 5 is obtained. The operation after inputting data to the shift register 20 will be described below because there is no difference in the other configuration and operation.

In this test circuit 17a, 1
After inputting 0-bit data, the encryption circuit 25a encrypts
Outputs bit data. Of the output data, the upper 2 bits are assigned to field 1 and the remaining bits are assigned to field 2, and field 1 is used as an address signal 40 for PROM5.
Is used to designate one password 23 among the four passwords built in the secret zone 51. The 8-bit long field 2 is used for comparison with the password 23 in the comparison circuit 22. The test circuit 17a outputs the test signal 9 only when both match, and implements the test mode.

FIG. 7 is a block diagram showing the configuration of the encryption circuit 21a in FIG.

The encryption circuit 21a performs the following data conversion on the 10-bit input data and outputs 10-bit data.

Bit 0 and bit 7 are interchanged, bit 7 is inverted, bit 0 is output as it is, bit 4 is output after inversion, bit 5 and bit 6 are inverted and output after being inverted, bit 8
And bit 9 are exchanged and then inverted and output.
2, bit 3 is output as it is.

 For example, when the input is 3FFH, the output is 00FH. Becomes

Since the password output from the PROM 5 is 8 bits long, there are 2 ⁸ = 256 patterns. In addition, since all the input data is scrambled by the encryption circuit and one of the four passwords is used, it becomes more difficult to detect a 10-bit pattern that can realize the test mode.

The test circuit 17a also encrypts the field 1 which becomes the address signal 40 by the encryption circuit 21a,
The relationship between 3 and 10-bit input data has become increasingly difficult to determine. Therefore, realization of the test mode by a third party is more difficult than in the first embodiment.

FIG. 8 is a block diagram of a single-chip microcomputer according to a third embodiment of the present invention. In this embodiment, PROM5
EEPROM5a is used as the write circuit of this EEPROM5a.
52 can be written by the program 41.

In this embodiment, components other than the test circuit 17b are the same as those of the conventional example shown in FIG. This test circuit 17b inputs data serially from the external terminal 19 in synchronization with the clock signal 11 output from the CPU, and stores the password value and the input data inaccessible from the CPU 2 stored in the EEPROM 5a addressed by the address signal 40. Have a function of permitting the test mode only when they match, and a function of updating the password value in the test mode.

FIG. 9 is a block diagram of the test circuit 17b of FIG.

The test circuit 17b includes a shift register 20, a comparison circuit 2
2, a counter 24, latches 34 and 35, and an AND gate 44.

When the reset signal 14 is 0 and the shift enable signal 28 is 1, the shift register 20 inputs 8-bit serial data on the signal line 18 in synchronization with the fall of the CPU clock 11. The comparing circuit 22 compares the output of the shift register 20 with the value of the password 23 of the EEPROM 5a, outputs a signal only when the values match, and sets the output of the latch 35 to 1. The latch 35 sets the output to 1 according to the output of the comparison circuit 22, outputs a test signal 9, and outputs a reset signal.
The output is set to 0 by 14.

The counter 24 controls the shift operation of the shift register 20, synchronizes with the falling edge of the basic clock 11, counts the CPU clock 11 only when the test mode signal 16 is 1, and sends a shift enable signal to the shift register 20. The test mode signal 16 is cleared to 0 when the test mode signal 16 is 0, and the operation of the latch 34 is stopped.
This is a latch that inverts the output value according to 37.
Set to 1 by 14.

The AND gate 44 is a two-input AND gate that receives the test signal 9 and the output signal 43 of the latch 34 and takes a logical product, and outputs a program signal 41.

 The operation of the test circuit 17b will be described.

First, the test mode signal 16 is kept while the reset signal 14 is kept at 1.
Is set to 0. Next, the test mode 16 is set to 1 and the reset signal 14 is set to 0 in synchronization with the fall of the CPU clock 11.
And In synchronization with the rise of the CPU clock 11, 8-bit data is serially input from the external terminal 19.

At this time, the counter 24 counts eight times in synchronization with the CPU clock 11, and outputs the shift register enable signal 28 to 1
And outputs the result to the shift register 20. Counter 24
After the count operation is performed eight times, the shift permission signal 28 is set to 0 and the operation is stopped. In addition, the latch 34 outputs 0 inverting the value according to the overflow signal 37 of the counter 24.

When the shift enable signal 28 is 1, the shift register 20
After performing the shift operation eight times in synchronization with the falling of the U clock 11, the shift operation is stopped because the shift permission signal 28 becomes 0, and the stored value is cleared to 0 when the reset signal 14 is 1.

After receiving 8-bit serial data, shift register
The stored value of 20 is output to the comparison circuit 22. The comparison circuit 22
Password 23 and shift register 20 stored in EEPROM 5a
Compare the input data to the latch, and if the values are the same, set the latch 35 to 1
And the test signal 9 is output. If the input data from the outside of the chip does not match the password 23, the output of the comparison circuit 9 is 0, so the latch 35 outputs 0 and the test signal 9 is not output.

FIG. 10 is an operation timing chart of the test circuit 17b.

Next, a case where the test of the EEPROM 5a is performed after the test signal 9 is output and the password is updated at the end will be described.

At this time, first, the external terminal 15 is set to 0 at the falling synchronization of the CPU clock 11, then to 1 at the falling synchronization of the CPU clock 11, and then data is input at the rising synchronization of the CPU clock 11. When the external terminal 15 is set to 0, the test mode signal 16 becomes 0 and the counter 24 is cleared to 0. Then, the shift permission signal 28 becomes 1, and the shift register 20 can externally input data.

Assuming that the external terminal 15 is 1, the test mode signal 16 becomes 1 and the operation of the counter 30 becomes possible. In this way, data can be input again from outside the chip. At this time, the counter 24 outputs the overflow signal 37, so that the latch 34 inverts the value and outputs 1. Since the value of the latch 34 after reset is 1 and the password has been received, the latch 34 outputs 0, so that 1 is output by data input.

At this time, since the output of the latch 35 is 1, the AND gate 44
Is 1 and the program signal 101 is output.

Therefore, the write circuit 52 in the EEPROM 5a
The value stored in the shift register 20 is input via the bus 36 via 41 and written to the password storage address.

 FIG. 11 shows an operation timing chart of the test circuit 17.

FIG. 12 is a block diagram showing the configuration of the counter 24 of FIG.

The counter 24 includes a 4-bit up counter 30, an AND gate 31, and an inverter 39 similar to those shown in FIG.

When the test mode signal 16 is 0, the up counter 30 is cleared and stops operating. When the test mode signal 16 is 1, the counter 30 counts up in synchronization with the rising of the output of the AND gate 31. That is, the test mote signal
Since 16 is 0 and the output of inverter 39 is 1, AND gate 31
Outputs the CPU clock 11 as it is, and the counter 30 counts the CPU clock.

When the counter 30 counts the CPU clock 11 nine times,
Since the third bit of the counter 30 = 1, the inverter 39
Becomes zero, and the shift permission signal 28 becomes zero. Therefore, the output of the AND gate 31 also becomes 0, and the counter 30 stops counting.

To input data again from outside the chip, first set the external terminal 15 to 0 at the falling synchronization of the CPU clock 11, and then
Data is input at the rising synchronization of the CPU clock 11 after being set to 1 at the falling synchronization of the clock 11.

When the external terminal 15 is set to low, the test mode signal 16 becomes 0
And the counter 30 is cleared to 0. Then, the shift permission signal 28 becomes 1, and the shift register 20 can input external data. Assuming that the external terminal 15 is 1, the test mode signal 16 becomes 1 and the operation of the counter 30 becomes possible.

In the test circuit of this embodiment, the test mode is permitted only when the data input from the outside of the chip matches the password stored in the built-in EEPROM, so that it becomes more difficult for a third party to execute the test mode. Further, since the password is inaccessible from the CPU and can be updated in the test mode, the security level is increased by frequently changing the password.

FIG. 13 is a block diagram of a test circuit 17c of the single-chip microcomputer according to the fourth embodiment of the present invention.

This test circuit 17c is different from the test circuit 17b in FIG. 9 in that the password stored in the EEPROM 5a and the shift register 20
The data stored in the shift register 20 is compared with the data converted by the encryption circuit 21, and the data input again to the shift register 20 is converted by the encryption circuit 21 and then converted as a new password.
The difference is that a means 52 for writing to the EEPROM 5a is provided.

This encryption circuit 21 uses a circuit that converts 8-bit input data to obtain 8-bit output data, as in the case shown in FIG.

Since this encryption circuit 21 is used, any method
Even if you can know the password stored in EEPROM5a,
Since the value is converted before the comparison, the test mode cannot be realized even if the password value is input from outside the chip. Also, when updating the password, the input value to the shift register is converted and written to the EEPROM 5a, so that even if the new password is known, the test mode cannot be realized. Therefore, the realization of the test mode by a third party is more difficult than in the third embodiment.

〔The invention's effect〕

As described above, the present invention stores a plurality of passwords in a secret zone in a PROM conventionally used as a data memory, and uses data comprising two first and second fields input from the outside. By adding a test circuit that permits a test mode only when one of a plurality of passwords specified in the first field and a value obtained by encrypting the second field match, a conventional test circuit is added. There is an effect that illegal data access that occurs when data access to the secret zone is freely performed in the realization of the test mode is prohibited, and high security can be realized.

[Brief description of the drawings]

FIG. 1 is a block diagram of a single-chip microcomputer according to a first embodiment of the present invention, FIG. 2 is a block diagram of an example of a test circuit 17a of FIG. 1, and FIG. 3 is a block diagram of the test circuit 17 of FIG. FIG. 4 is a block diagram of a counter in the test circuit of FIG. 2, FIG. 5 is a block diagram of an encryption circuit in the test circuit of FIG. 2, and FIG. 6 is a second embodiment of the present invention. Block diagram of an example test circuit 17a,
7 is a block diagram of the encryption circuit of FIG. 6, FIG. 8 is a block diagram of a single-chip microcomputer according to a third embodiment of the present invention, and FIG. 9 is a block diagram of an example of the test circuit of FIG. 10 and 11 are operation timing diagrams of the test circuit, FIG. 12 is a block diagram of a counter in the test circuit, FIG. 13 is a block diagram of a test circuit according to a fourth embodiment of the present invention, and FIG. FIG. 15 is a block diagram showing two examples of a conventional single-chip microcomputer. 1,1a, 1b, 1c …… Single-chip microcomputer,
2 ... CPU, 3 ... Memory, 4,8 ... Internal bus, 5 ...
PROM, 5a …… EEPROM, 51 …… Secret zone, 52…
… Write circuit, 6… Peripheral part, 7,39 …… Inverter, 9
…… Test signal, 10,12,13,15,19,61 …… External terminal, 11
... CPU clock, 14 ... reset signal, 16 ... test mode signal, 17, 17a ... test circuit, 18 ... signal line, 20
... shift register, 21, 21a ... encryption circuit, 22 ... comparison circuit, 23 ... password, 24, 30 ... counter, 28 ...
Shift enable signal, 31, 44 AND gate, 33 AND gate, 34, 35 latch, 36 bus, 37 overflow signal, 40 address signal, 41, 42 program signal.

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G06F 12/14

Claims (4)

(57) [Claims] 1. A single-chip microcomputer in which a central processing unit, a storage unit, a peripheral unit, and a PROM are integrated on a single semiconductor substrate, and a test is performed on the PROM by a test circuit. , A plurality of passwords are stored. The test circuit includes: a shift register for temporarily storing serially stored data consisting of two first and second fields input from the outside; and a second register for outputting the shift register. An encryption circuit for encrypting the data of the field of the PROM, and an address of the PROM addressed by the first field of the output of the shift register.
A comparison circuit for comparing one value of a plurality of passwords read from the password and a value encrypted by the encryption circuit, and performing a test from the outside to the PROM only when the comparison value of the comparison circuit is equal. A single-chip microcomputer characterized by being made possible. 2. The plurality of passwords read from the PROM addressed by the data encrypted in the first field, wherein all data in the two fields input to the shift register are encrypted by an encryption circuit. One of
2. The single-chip microcomputer according to claim 1, wherein the value and the value encrypted in the second field are compared by a comparison circuit. 3. A single chip in which a central processing unit, a storage unit, a peripheral unit, and an electrically writable EEPROM are integrated on a single semiconductor substrate, and a test is executed on the EEPROM by a test circuit. In the microcomputer, a password is stored in the EEPROM, the test circuit controls the shift register that temporarily stores data input from the outside in a serial manner, and counts the number of bits input to the shift register to control the shift register. And a comparison circuit for comparing the value of the password and the value input to the shift register, and the EE is externally provided only when the comparison values of the comparison circuits are equal.
A single-chip microcomputer which enables a test to a PROM and updates the password by writing a value input to the shift register to the EEPROM again. 4. The single-chip microcomputer according to claim 3, wherein input data from the shift register is converted by an encryption circuit, and a value converted by the encryption circuit and a password value are compared by a comparison circuit.