JPH05227052A - Synthesizer receiver - Google Patents

Abstract

PURPOSE:To use only a single crystal oscillator and to prevent the generation of harmonic interruption to a high frequency circuit by allowing a reference signal generating circuit to receive an oscillation output from the oscillator and form a reference signal. CONSTITUTION:This synthesizer receiver is provided with the reference signal generating circuit 14 whose oscillation frequency is controlled by a microcomputer 8. A crystal oscillator 808 on the computer 8 side is shared by the circuit 14 and its oscillation signal is applied to the circuit 14 through an inverter 16. The circuit 14 is constituted so that the oscillation signal can be controlled by the computer 8 and a control output for setting up the frequency of a reference signal is applied from the computer 8 to the circuit 14 based upon a control program and fixed data. Consequently the reference signal required for a PLL-IC 60 can be obtained from the circuit 14. Since only the single crystal oscillator is used and the arrangement of a crystal oscillator on the PLL side can be eliminated, the generation of harmonic interruption to the high frequency circuit can be prevented.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synthesizer receiver using a digital tuning device such as a car radio and a portable radio.

[0002]

2. Description of the Related Art Conventionally, a synthesizer receiver has a tuner circuit as shown in FIG. 2, and the tuner circuit has a high frequency circuit 2 installed in an antenna for receiving a high frequency signal such as a radio wave for broadcasting. .. In this high frequency circuit 2,
A high frequency amplifier circuit, a frequency mixer circuit, etc. are installed, and a voltage controlled oscillator (VC) is used as a local oscillation circuit.
O) 4 is connected. The VCO 4 oscillates a local oscillation signal to be mixed with the high frequency signal and adds it to the high frequency circuit 2. The frequency of the oscillation signal of the VCO 4 is VC
It is selected by a PLL-IC 6 and a microcomputer 8 which form a main circuit for forming a phase locked loop (PLL) together with O4. The PLL-IC 6 is an integrated circuit in which the VCO 4 and the like in the PLL are removed. IF
Is an intermediate frequency output obtained from the high frequency circuit 2.

Next, FIG. 3 shows a concrete configuration of this tuner circuit. The PLL-IC 6 is constructed independently of the microcomputer 8. The PLL-IC 6 has a reference signal generating circuit 602, A phase comparator 604, a programmable divider 606, etc. are installed. The reference signal generation circuit 602 is a means for generating a reference signal that forms a local oscillation signal, and the reference signal generation circuit 602 has a crystal oscillator (Xta) through external terminals 608 and 610.
l) 612 and capacitors 614 and 616 are connected to form a crystal oscillator 618. The reference signal obtained by the reference signal generating circuit 602 and the output of the programmable divider 606 are added to the phase comparator 604, and the phases of both are compared. The comparison output of the phase comparator 604 is taken out through the phase output terminal 620 and the resistor 62
2, inverter 624, capacitor 626 and resistor 62
VCO4 through 8 as a frequency control input. The oscillation output V _O of the VCO 4 is applied to the high frequency circuit 2 side and is also applied to the frequency input terminal 632 of the PLL-IC 6 through the capacitor 630,
Programmable divider 60 through inverter 634
Added to 6. In the programmable divider 606,
The frequency dividing ratio N is set by the microcomputer 8, and the oscillation signal divided by the frequency dividing ratio N is added to the phase comparator 604 to compare the phase with the reference signal. By such a PLL operation, the VCO 4 is synchronized with a constant oscillation frequency and an oscillation output V _O having a constant frequency is obtained.

On the side of the microcomputer 8,
A crystal oscillator 802 and capacitors 804, 806 independent of the PLL-IC 6 side for performing a program operation and the like.
A crystal oscillator 808 including is installed. In the microcomputer 8, the serial data CE, CK, DA are obtained by the program operation, and are added to the control input terminals 636, 638, 640 of the PLL-IC 6 to perform the necessary tuning operation. In addition, the microcomputer 8
A key input circuit 10 and a display circuit 12 are connected to the side, and tuning data is input through the key input circuit 10.
The display circuit 12 displays the tuning frequency and the channel.

[0005]

By the way, in such a tuner circuit, the microcomputer 8 side and the PL
Crystal oscillators 618 and 808 that oscillate their own oscillation frequencies are installed on both sides of the L-IC 6, and each oscillator circuit uses its own crystal oscillator, which is expensive. Further, since the PLL-IC 6 includes a digital circuit, its digital operation also adversely affects the operation of the high frequency circuit 2, but in particular, the crystal oscillator 61 is provided on the PLL-IC 6 side.
8 is installed, the harmonics (10
(About 20 times the frequency) causes a beat failure in the high frequency circuit 2.

It is therefore an object of the present invention to provide a synthesizer receiver which simplifies the structure by unifying a crystal oscillator and prevents harmonic interference to a high frequency circuit.

[0007]

According to the synthesizer receiver of the present invention, an oscillation signal of a voltage controlled oscillator (VCO4) is divided by a programmable divider (606) controlled by a microcomputer (8), and its divided output is obtained. And a reference signal in a phase comparator (604) for comparing the phases, controlling the oscillation output of the voltage controlled oscillator by the comparison output, and mixing the oscillation output with a high frequency signal. A reference signal generating circuit (14) which receives an oscillation output from a crystal oscillator (808) installed in a computer and generates a reference signal by setting an arbitrary frequency by the microcomputer, and cuts off harmonics of the reference signal. A filter (18) as a frequency band is installed, and the reference signal passed through the filter is input to the phase comparator. Characterized in that was.

[0008]

In this synthesizer receiver, the reference signal generating circuit receives the oscillation output of the crystal oscillator on the microcomputer side to form the reference signal, and the conventional crystal oscillator on the microcomputer side is omitted. .. As a result, the crystal oscillator is unified. Then, the reference signal obtained by the reference signal generation circuit is added to the phase comparator through a filter that has the harmonics of the reference signal as the cutoff band, and the harmonics are removed by the filter, beat interference to the high frequency circuit side, unnecessary Radiation etc. can be prevented.

[0009]

The present invention will be described in detail below with reference to the embodiments shown in the drawings.

FIG. 1 shows an embodiment of the synthesizer receiver of the present invention. In this synthesizer receiver, a microcomputer 8 is installed similarly to the tuner circuit shown in FIG. A crystal oscillator 808 is installed in the microcomputer 8 as a reference oscillator, and the crystal oscillator 808 includes a crystal oscillator 802, capacitors 804 and 806, and a resistor 807. Further, although not shown, a key input circuit 10 and a display circuit 12 are connected to the microcomputer 8 for inputting necessary data and frequency display.

A reference signal generation circuit 14 whose oscillation frequency is controlled by the microcomputer 8 is installed in the synthesizer receiver. The reference signal generation circuit 14 is the same as in the synthesizer receiver shown in FIG. P
This corresponds to the reference signal generation circuit 602 installed inside the LL-IC 6. This reference signal generation circuit 1
4 also shares the crystal oscillator 808 on the microcomputer 8 side, and its oscillation signal is added via the inverter 16. Further, this reference signal generation circuit 602
Is configured such that the oscillation signal can be controlled by the microcomputer 8, and a control output for setting the frequency of the reference signal is added from the microcomputer 8 by the control program and fixed data. As a result,
The reference signal generation circuit 14 can obtain a reference signal required on the PLL-IC 60 side.

A filter 18 is installed on the output side of the reference signal generating circuit 14. This filter 18 is for removing unnecessary harmonic components from the output generated by the reference signal generation circuit 14, and cuts off the frequency range of the frequency of the reference signal, for example, the intermediate frequency f _n = 450 kHz.
It is a low-pass filter with the pass band below that.

Further, the PLL-IC 60 is provided with a reference signal input terminal 619 for inputting a reference signal in place of the conventional external terminals 608 and 610. That is, PLL-
In the IC 60, the number of terminals is reduced together with the crystal oscillator 618 as compared with the PLL-IC 6 (FIG. 3). The reference signal applied to the reference signal input terminal 619 is input to the phase comparison reference signal 604 for phase comparison with the output of the programmable divider 606.

The PLL-IC 60 is provided with a shift register and a latch circuit 642 as means for setting the frequency division ratio N in the programmable divider 606. The shift register and latch circuit 642 is provided with a microcomputer 8 as a control input. Serial data CE, C
K, DA are applied through control input terminals 636, 638, 640. Therefore, the programmable divider 606 sets a constant frequency division ratio N, and the frequency division operation for obtaining the frequency corresponding to the reference signal is obtained.

On the output side of the phase comparator 604,
A tri-state buffer 648 including transistors 644 and 646 is installed, and a phase comparison output is taken out from the phase output terminal 620 through the tri-state buffer 648. A low pass filter (LPF) is provided between the phase output terminal 620 and the voltage controlled oscillator (VCO) 4.
20 is installed, and this LPF 20 removes the abrupt fluctuation component contained in the phase comparison output. Therefore, VC
A direct current voltage having a gentle level change is applied to O4 as a frequency control input.

The VCO 4 is applied with a DC voltage as a frequency control input and generates an oscillation output V _O having a frequency corresponding to the level of the DC voltage. When the control input is applied to the current, the current / voltage converting means may be installed on the input side of the VCO 4. The oscillation output V _O is output as a local oscillation signal to the frequency mixer circuit side (not shown) and is also applied to the frequency input terminal 632 of the PLL-IC 60 via the capacitor 630.

The PLL-IC 60 has a frequency input terminal 6
Inverter 6 for inverting the frequency input applied to 32
34 is installed, and a resistor 635 is installed in the inverter 634.
Are connected in parallel. The frequency input through the inverter 634 is applied to the programmable divider 606, frequency-divided by the frequency division ratio N, and then input to the phase comparator 604 for phase comparison.

As described above, in the tuner circuit of this synthesizer receiver, the reference signal generation circuit 602 (FIG. 3) is removed from the PLL-IC 60 and the reference signal generation circuit 14 as an external circuit is installed. The reference signal generating circuit 14 receives a signal from the crystal oscillator 808 on the microcomputer 8 side, and the necessary frequency is set by the microcomputer 8. Then, the reference signal is added to the PLL-IC 60 after removing unnecessary harmonic components through the filter 18.

According to such a configuration, the PLL-IC 6
0 and a single crystal oscillator 80 in the microcomputer 8.
8, the configuration is simplified, and the PLL-I
By removing the crystal oscillator from C60, PLL-IC6
It is possible to drastically reduce beat interference and spurious emission to the high frequency circuit side due to the output of 0. Moreover, by using the reference signal generating circuit 14 as an external circuit, the PLL-IC6
As a result, it is possible to obtain a highly reliable synthesizer receiver in which the adverse effect due to harmonics is suppressed as well as the simplification of the configuration, such as 0 is achieved.

[0020]

As described above, according to the present invention,
The following effects can be obtained. a. The crystal oscillator can be unified, and by omitting the crystal oscillator from the PLL side, the oscillator configuration can be simplified and the expensive crystal oscillator can be reduced, and the device cost can be reduced. b. Since the crystal oscillator is eliminated from the PLL side, it is possible to prevent harmonic interference with the high frequency circuit. c. Since the reference signal generation circuit moves from the PLL side to the microcomputer side, the chip size can be reduced when the PLL side is integrated into an IC, and the current consumption can be reduced and the manufacturing yield can be increased. d. Since the reference signal generation circuit receives the oscillation frequency of the oscillator on the microcomputer side, it is possible to obtain a reference signal with the same precision as the clock signal on the microcomputer side, and since it can be set to an arbitrary frequency by the microcomputer, The frequency of the reference signal can be easily set.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a synthesizer receiver of the present invention.

FIG. 2 is a block diagram showing a tuner circuit of a general synthesizer receiver.

FIG. 3 is a block diagram showing a configuration of a tuner circuit in a conventional synthesizer receiver.

[Explanation of symbols]

 4 Voltage Controlled Oscillator 8 Microcomputer 14 Reference Signal Generation Circuit 18 Filter 604 Phase Comparator 606 Programmable Divider 808 Crystal Oscillator

Claims (1)

[Claims] 1. An oscillation signal of a voltage controlled oscillator is divided by a programmable divider controlled by a microcomputer, the divided output and a reference signal are compared in phase by a phase comparator, and the voltage output is controlled by the comparison output. A synthesizer receiver that controls the oscillation output of an oscillator and mixes the oscillation output with a high-frequency signal.The oscillation output is received from a crystal oscillator installed in a microcomputer, and an arbitrary frequency is set by the microcomputer. It is characterized in that a reference signal generating circuit for generating a reference signal and a filter having a cutoff region of a harmonic of the reference signal are installed, and the reference signal passed through this filter is inputted to the phase comparator. Synthesizer receiver.