JPH09130291A - Clock distributing system for portable dual mode telephone terminal - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an economical miniaturized portable dual mode communication terminal by using only one reference frequency signal required for PHS and PDC synthesizers and distributing this signal to the desired number of stages of frequency division. SOLUTION: A received signal (PHS-RX) is outputted to a regenerative signal line 12 by mixer circuits 5A and 5B and a PHS MODEM 6 while using PHS synthesizers 4A and 4B. Besides, PHS transmission data (TX-DATA) are transmitted while being converted to a frequency for PHS transmission signal by the PHS synthesizers 4B and 4S and mixer circuits 5C and 5D. In the case of PDC, the signal is similarly converted while using PDC synthesizers and mixers as well. In this case, only one VCTCX01 is used as the reference frequency signal required for PHS and PDC synthesizers and this signal is distributed to the desired number of stages of frequency division by frequency dividers 3A-3D so as to generate and distribute the reference clocks of respective communication systems. Thus, the economic miniaturized portable dual mode communication terminal can be provided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a mobile phone for communication, and particularly to a PHS (Parsonal Handy Phone System).
The present invention relates to a mobile communication terminal capable of making a call by both different communication systems such as PDC (Parsonal Digital Cellular).

[0002]

2. Description of the Related Art Conventionally, there has been no terminal capable of performing communication in different communication systems with one mobile terminal.
There is no technology that can achieve both PHS and PDC communication methods. However, as a commonly used method, as shown in FIG.
A voltage-controlled temperature-compensated crystal oscillator (VCT
CXO) is installed and its output signal is supplied as a reference signal for each block in the terminal. Where VCTC
The reason why XO is used is to facilitate the realization of a feedback means that minimizes the frequency deviation from the base station.Therefore, depending on the specifications of the frequency deviation from the base station, the voltage control crystal may be used if temperature compensation is not required. An oscillator (VCXO) may be used in some cases.

As shown in FIG. 4, when a terminal having a different communication method such as PHS and PDC is realized, two VCTCXOs are prepared as a method to be easily realized from an extension of the conventional technology, and the respective communication is performed. By oscillating at the optimum frequency according to the system and dividing them independently, P
A method of generating a necessary reference clock in each circuit block of HS or PDC can be considered. Conventionally used
As a typical frequency of VCTCXO, PDC is 12.6 MH
z and PHS are often 19.2 MHz.

[0004]

As a method of generating a reference clock required in each circuit block, two VCTCXOs are used.
Or when using two reference oscillators according to it, VC
The size and current consumption of the TCXO become a problem for the talk time and size of the mobile phone. The size of the VCTCXO in a commonly used mobile terminal is about 1 cm ² and the current consumption is about 5 mA. The use of these two is large for the size of the communication mobile terminal and the talk time. Bring disadvantages.

The present invention uses PHS and PD in the conventional extension line.
When a dual-mode mobile phone terminal supporting both C communication systems is manufactured, a clock distribution method that can be realized by one TCXO is provided for a problem that requires two VCTCXOs.

[0006]

A frequency component required as a reference clock for PDC and PHS is 42 kHz used for a PDC modulator / demodulator, 25 kHz used for a frequency synthesizer, and 192 kHz required for a PHS modulator / demodulator.
There are four types, Hz and 300 kHz required for the frequency synthesizer.

A clock required for each circuit block is supplied to these circuits by a method such as a counter in which the occurrence of jitter is small.

First, assuming that each clock frequency described above is generated by a frequency divider having an integer frequency division number such as a counter, the minimum oscillation frequency (the least common multiple of the above four frequency components) is calculated. It is 0.6 MHz. If this oscillation frequency is divided by 800, 42 kHz used in a PDC modulator / demodulator can be generated, and by dividing 1344, it can be used in a PDC frequency synthesizer.
kHz is obtained.

On the other hand, 192k required for PHS modulator / demodulator
Hz is obtained by dividing the oscillation frequency by 175, and 300 kHz required for the frequency synthesizer is 112
By dividing the frequency, it is possible to generate similarly.

In the case of a dual-mode communication telephone terminal, only one communication system is used at the same time. Therefore, as in this system, an oscillator having a frequency common to the two communication systems is used to generate the reference clock. Does not matter.

Next, the following three methods are conceivable as methods for generating a common oscillation frequency required for PHS and PDC. (1) 33.6MHz VCTCXO, (2) 11.2MH
A method of obtaining a frequency component of 33.6 MHz by connecting a resonator having a resonance point at a triple frequency to the output of the VCTCXO of z,
(3) The output of the VCTCXO of 11.2 MHz is connected to a 21-multiplication circuit using a PLL, the output signal is used as the intermediate frequency of the superheterodyne receiving circuit, and the intermediate frequency is divided by 7 to obtain the PHS. And a common oscillation frequency required for PDC is obtained.

If the clock distribution method of this system is used, 2
It is possible to generate a reference signal that oscillates at a frequency common to the two systems, and then generate the reference clock required for each communication system. It can be easily generated.

[0013]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of a reference clock distribution system for a dual mode mobile telephone terminal will be described with reference to FIGS.

The dual-mode mobile phone terminal is a terminal in which a transmission / reception circuit compatible with two or more communication systems is built in one mobile phone terminal. Here, a reference clock distribution system will be described by taking a dual-mode mobile phone terminal capable of supporting two communication systems, PDC and PHS, performed in Japan as an example. However, this distribution system is used in countries other than Japan, such as GSM and IN5.
The same can be applied to each method such as No. 4 and the like.

FIG. 1 is a block diagram of a dual mode mobile phone terminal according to an embodiment of the present invention. This device converts a signal (PHS-RX) received from an antenna into a first PHS receiving intermediate frequency by using an output signal of the PHS synthesizer 4A, and an output of the first mixer circuit 5A and the first mixer circuit 5A. To the second intermediate frequency for PHS reception by using the output signal of the PHS synthesizer 4B, and the decoding rule defined by the PHS communication method for the output of the second mixer circuit 5B. The signal line 12 (PHS RX-DAT) is demodulated in accordance with
A) and PHS transmission data signal line 13 (PHS TX-D
ATA) according to the code rule defined in the PHS communication system, and outputs the output of the PHS modulator / demodulator 6 and the PHS modulator / demodulator 6 to the first intermediate frequency for PHS transmission by using the output signal of the PHS synthesizer 4B. A third mixer circuit 5C for conversion, and an output of the third mixer circuit 5C is PHS.
The PHS transmission / reception circuit includes a fourth mixer circuit 5D that converts the PHS transmission signal frequency (PHS-TX) transmitted from the antenna using the output signal of the synthesizer 4A.

Similarly, a signal (PDC-RX) received from the antenna is converted into a first PDC receiving intermediate frequency using the output signal of the PDC synthesizer 4C.
Of the mixer circuit 5E, and the output of the fifth mixer circuit 5E
The second PDC using the output signal of the DC synthesizer 4D
The sixth mixer circuit 5F for converting to an intermediate frequency for reception, the output of the sixth mixer circuit 5F is demodulated according to the decoding rule defined in the communication system of the PDC, and the reproduced signal line 14 (PDC of the received data RX-DATA) and PDC transmission data signal line 15 (PDC TX-DATA) PD
The PDC modulator / demodulator 7 that matches in accordance with the coding rule defined by the C communication method, and outputs the output of the PDC modulator / demodulator 7 to the first PD using the output signal of the PDC synthesizer 4D.
A seventh mixer circuit 5G for converting to an intermediate frequency for C transmission,
The output of the seventh mixer circuit 5G is supplied to the PDC synthesizer 4
The PDC transmission / reception circuit configured by the eighth mixer circuit 5H for converting the PDC transmission signal frequency (PDC-TX) transmitted from the antenna using the output signal of C and the reference clock of the dual mode mobile phone terminal are used. The generated temperature-compensated voltage controlled crystal oscillator (VCTCXO) 1 and the output signal of the VCTCXO1 are used as PHS synthesizer 4A, PHS synthesizer 4B, PDC synthesizer 4C, PDC synthesizer 4
Clock distribution circuit 2 for supplying respective operation reference clocks for D, PHS modulator / demodulator 6 and PDC modulator / demodulator 7.
have.

Here, in the first embodiment shown in FIG. 1, the clock distribution circuit 2 is composed of frequency dividers 3A to 3D, but in the second embodiment shown in FIG. 2, VCTCXO1 and the clock distribution circuit. A multiplier (resonant circuit) 16 including an inductance and a capacitance is inserted between the multiplier 2 and the capacitor 2.
On the other hand, in the third embodiment shown in FIG. 3, the output of VCTCXO1 is input to the PHS synthesizer 4B, and a part of the output of the PHS synthesizer 4B is branched to add a new frequency divider in the clock distributor 2. 3E, and the output of the frequency divider 3E is input to the other frequency dividers 3A to 3D.

Next, the clock distribution system will be described. In the first embodiment shown in FIG. 1, PDC and PHS are used.
Use VCTCXO1 to generate the frequency components required for the reference clock of. The frequency component required as the reference clock for PDC and PHS is used in the PDC modulator / demodulator 7
2kHz, 25kHz used for PDC frequency synthesizer 4C, 4D, 192k required for PHS modulator / demodulator 6
Hz, 3 required for PHS frequency synthesizer 4A, 4B
There are four types of 00 kHz. These circuits supply a required clock to each circuit block by a method such as a counter in which jitter is small.

First, the above-mentioned four clock frequencies are generated by a frequency divider having an integer frequency division number in order to realize low jitter such as a counter. Therefore, the minimum oscillation frequency (least common multiple of the above four frequency components) is 33.6 MHz. By dividing the oscillation frequency by 800, 42 kHz used in the PDC modulator / demodulator 7 can be generated, and by dividing 1344, 25 kHz used in the PDC frequency synthesizers 4A and 4B can be obtained.

On the other hand, 192k required for the PHS modulator / demodulator 6
Hz is obtained by dividing the above oscillation frequency by 175, and is 30 required for the PHS frequency synthesizers 4C and 4D.
Similarly, 0 kHz can be generated by dividing the frequency by 112.

Even in the case of a dual mode communication telephone terminal,
Since only one communication method is used at the same time, there is no problem even if the reference clock is generated using an oscillator having a frequency common to the two communication methods as in this method.

To summarize the above points, the oscillation frequency of the VCTCXO1 is set to 33.6 MHz, and the clock distribution circuit 2 has four oscillation frequencies.
The frequency division number of each of the frequency dividers 3A to 3D may be set as follows.

(1) Frequency divider 3A: 112 (2) Frequency divider 3B: 175 (3) Frequency divider 3C: 800 (4) Frequency divider 3D: 1344 Further, in this case, each frequency divider (3 The output of (-1-3-4) is
A value that is an integer fraction of the frequency division number from (1) to (4) above,
There is no problem even if the PHS or PDC synthesizers 4A to 4D and the modulator / demodulator (6, 7) are further divided to a desired value.

Next, the method shown in FIG. 2 will be described as another embodiment of the clock distribution system.

A modification of the second embodiment shown in FIG. 2 with respect to the first embodiment is that the oscillation frequency of VCTCXO1 is 33.
Lower than 6MHz, for example 1/3 of 11.2MH
It is a point using z. This is a high oscillation frequency VCTCXO1
Is because power consumption is large and it may be difficult to obtain temperature compensation characteristics.

The second embodiment shown in FIG. 2 uses a method in which a multiplier 16 having a resonance point at a triple frequency is connected to the output of VCTCXO1 to obtain a frequency component of 33.6 MHz. The multiplier 16 can be composed of a simple capacitance or inductance. Here, the reason why the oscillation frequency of VCTCXO1 is set to 1/3 of the required oscillation frequency is
Common parts available for current VCTCXO frequency is about 10
Since it is around MHz, selecting a frequency other than one-third will not cause any problems depending on the technological progress and the conditions of the application point as long as the condition that division by an integer is satisfied. .

Finally, as another embodiment of the clock distribution system, the method shown in FIG. 3 will be described.

In the third embodiment shown in FIG. 3, the reference clock required for the dual mode mobile telephone terminal is PDC or P.
This is a system shared with the synthesizers 4B and 4D for generating the first intermediate frequency of HS. In the third embodiment, a method of sharing the PHS synthesizer 4B for generating the reference clock is shown, but of course,
A configuration in which the PDC synthesizer 4D is shared is also applicable.

Further, the frequency values and frequency division values used in the following description are numerical values for the purpose of explaining this embodiment, and may be changed within a range not changing the gist of the present invention in actual application. Absent.

The oscillation frequency of VCTCXO1 was selected to be 11.2 MHz in the third embodiment as in the second embodiment. VCTCX
The output of O1 is input to the PHS synthesizer 4B. P
The HS synthesizer 4B is configured to multiply the input output frequency of VCTCXO1 of 11.2 MHz by 21.
As a method of multiplying by 21, the PL that is usually used is often used.
This can be easily realized by using a frequency synthesizer using L. The output of the PHS synthesizer 4B is 235.2 MHz in this embodiment. The output of the PHS synthesizer 4B is supplied to the PHS receiving mixer circuit 5C, and the second
Of the PHS synthesizer 4b, the output of the PHS synthesizer 4b is input to the fifth frequency divider 3E of the clock distribution circuit 2, and the other frequency dividers 3A to 3A.
Generates a frequency of 33.6 MHz required for 3D. The frequency division number of the frequency divider 3E in this embodiment is 7.

Although three embodiments of the present invention have been described above, the present invention is applicable not only to the super-heterodyne configuration shown in FIGS. 1 to 3 but also to a so-called heterodyne system having one intermediate frequency. . Further, there is no problem even if the four synthesizers used in the present invention are time-shared with each other.

[0032]

EFFECTS OF THE INVENTION By using the present invention, even in the system using only one VCTCXO as the reference frequency signal, the PHS
It becomes possible to realize a dual-mode mobile communication terminal that incorporates a plurality of systems having different reference frequencies, such as PDC and PDC, and it is effective in its economy and miniaturization.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a block diagram showing a second embodiment of the present invention.

FIG. 3 is a block diagram showing a third embodiment of the present invention.

FIG. 4 is a block diagram showing a conventional example.

[Explanation of symbols]

1 ... VCTCXVO, 2 ... Clock distribution circuit, 3A-3E ... Divider, 4A-4D ... PHS synthesizer, 5A-5H ...
Mixer circuit, 6 ... PHS modulator / demodulator, 7 ... PDC modulator / demodulator,
8 ... Signal line (PHS-RX), 9 ... Signal line (PHS-T)
X), 10 ... Signal line (PDC-RX), 11 ... Signal line (P
DC-TX, 12 ... Signal line (PHS RX-DAT)
A), 13 ... Signal line (PHS X-DATA), 14 ... Signal line (PDC RX-DATA), 15 ... Signal line (PDC)
TX-DATA), 16 ... Multiplier.

Claims (5)

[Claims] 1. In a dual-mode mobile phone terminal capable of supporting two or more communication methods, a reference signal generating circuit for generating a reference clock in the terminal has a minimum common multiple of a clock frequency required by each method, or A clock distribution system characterized in that a reference clock corresponding to each communication system is generated and distributed by a frequency divider having a desired frequency division number using a reference clock frequency that is an integral multiple thereof. 2. The communication system according to claim 1, wherein the communication method is PDC (Par
sonal Digital Cellular) and PHS (Parsonal
Handy Phone System) and 3 as a reference clock
A clock distribution method characterized by using a frequency of 3.6 MHz or an integral multiple thereof. 3. The oscillator according to claim 2, wherein an oscillator having an oscillation frequency lower than that of the reference clock is used as a means for generating a reference clock or a frequency that is an integral multiple thereof.
A clock distribution method using a circuit in which a resonance circuit having a resonance point is connected to a frequency of 3.6 MHz or an integral multiple thereof. 4. The oscillator according to claim 2, wherein an oscillator having an oscillation frequency lower than that of the reference clock is used as a means for generating a frequency of the reference clock or an integral multiple thereof.
PLL that oscillates at a frequency of 33.6 MHz or an integral multiple thereof
(Phase Locked Loop) frequency multiplier is used, the frequency is used as an intermediate frequency of the superheterodyne receiver circuit, and a frequency divider for dividing the output of the PLL circuit by a desired frequency division number is connected. A clock distribution method characterized by generating a reference clock having a frequency of 0.6 MHz or an integral multiple thereof. 5. The clock distribution system according to claim 1, wherein the reference clock is a voltage controlled crystal oscillator or a temperature compensation voltage controlled crystal oscillator.