JPH06209216A - Signal generator - Google Patents

Abstract

PURPOSE:To obtain a signal generator in which the frequency of 10MHz, etc., being a standard reference clock frequency can be used as a reference clock. CONSTITUTION:This device is equipped with first and second DDS circuits 5 and 6 having binary type adders, and a PLL circuit is constituted of a phase comparator 2, voltage control oscillator 4, and second DDS circuit 6 having a frequency-divider function. Then, the output of the oscillator 4 is used as the reference clock of the first DDS circuit 5.

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal generator, and more particularly to a DDS (Direct Digital Sythesize) capable of using an existing high precision reference frequency such as 10 MHz as a reference clock.
r) The present invention relates to a signal generator using circuit technology. [0002] As a signal generator for generating a specific signal waveform such as a sine wave or a rectangular wave at an arbitrary frequency, the specific signal waveform information is stored as digital data in a memory such as a ROM. A DDS circuit that changes a read clock for reading data from the memory is widely used as a digital signal generator. In a conventional signal generator of this type, as shown in FIG. 2, N-bit frequency data is input to the input of a digital adder 21, and the output of the digital adder 21 is latched by a latch 22. It The latch output is output from the latch 22 in response to the clock CLK and the adder 21
It is supplied as the other input and also as the address data of the ROM 23. The waveform data read from the ROM 23 is converted into an analog signal by the D / A converter 24, and then a low-pass component (LPF) 25 extracts low-frequency components and is output. A binary adder is used as the adder 21 because of its simple structure and high-speed operation. Here, the output frequency Fout of the signal generator
Is expressed as Fout = Fclk · (frequency data) / (digital adder capacity), where Fclk is the clock frequency of the latch 22, and for example, Fclk = 2 ³⁶ × 10 ⁻⁴ = 6.871
94 ... MHz, digital adder capacity is 2 ³⁶ , when frequency data is 1, FOUT is 0.1mMHz
Is obtained. When the frequency data is 1234567, 123.4567 MHz is obtained as FOUT. Therefore, according to such a signal generator, the output frequency can be set with extremely high resolution. As described above, the DDS
A conventional signal generator using a circuit obtains high frequency resolution by using a binary adder. However,
Since the frequency resolution and the reference clock have the relationship shown in the above equation, the frequency resolution has a good value (for example, 1H).
A value such as z or 0.1 Hz, or 0.1 in the above example.
In order to obtain (mHz), the frequency of the reference clock becomes a value with a great number of digits, which is very bad as in the above example. That is, if the adder used in the above signal generator is a binary type with a capacity of 2 ⁿ and the frequency resolution is dF (Hz), the reference clock Fclk is Fclk (Hz) = 2 ⁿ × dF Becomes A crystal oscillator is generally used as a reference clock source, but it is difficult to manufacture such a high-precision crystal oscillator with a poor frequency. Generally, the high-precision reference frequency of a high-frequency measuring instrument is 10 MHz,
Or the frequency division frequency of 5MHz, 2MHz, 1
It is set to a value like MHz. Therefore, the DDS circuit as described above has a problem that a highly accurate reference clock cannot be used. This also means that it cannot be synchronized with other measuring instruments that use a highly accurate reference frequency. Therefore, an object of the present invention is to provide a signal generator capable of using a standard reference clock frequency such as 10 MHz as a reference clock. In order to solve the above-mentioned problems, a signal generator according to the present invention comprises a first DDS circuit having a binary adder and a frequency divider for dividing a reference frequency. A phase comparator having the output of the frequency divider as an input, and the oscillation frequency of the first DD depending on the output of the phase comparator.
An oscillator that changes in the vicinity of a reference clock required by the S circuit and supplies the first DDS circuit and a binary adder, and receives an output of the oscillator as a reference clock;
A second DDS circuit provided with frequency data such that the output frequency becomes equal to the output frequency of the frequency divider. In the present invention, the PLL circuit is provided with the first and second DDS circuits having the binary type adder, and the phase comparator, the voltage controlled oscillator and the second DDS circuit having the frequency dividing function. And the output of the oscillator is used as the reference clock of the first DDS circuit. Embodiments of the present invention will now be described with reference to the drawings. FIG. 1 is a configuration block diagram showing an embodiment of a signal generator according to the present invention. In this embodiment,
The DDS circuit 5 has a binary adder, its capacity is 2 ²³ , its frequency resolution is 1 Hz, and the required reference clock frequency Fclk is 2 ²³ [Hz], which corresponds to the standard frequency. Frequency of 10 MHz Fref.
2 ²³ = as Fclk using the configuration described below.
Converted to 8.388608 [MHz] and set D
It is supplied to the DS circuit 5. In FIG. 1, reference frequency Fref (10M
(Hz) is divided into 1/1000 by the frequency divider 1 and supplied to the-input terminal of the phase comparator 2. A low-pass filter (LPF) 3 extracts a desired low-frequency component from the output of the phase comparator 2 and inputs it to the voltage-controlled oscillator 4. As the voltage controlled oscillator 4, a voltage controlled frequency variable crystal oscillator (VCXO) whose oscillation center frequency is Fclk, that is, in the vicinity of 2 ²³ [Hz] is used. The 2 ²³ Hz oscillation output from the voltage controlled oscillator 4 is supplied as a reference clock Fclk for the DDS circuit 5 and also as a reference clock for the DDS circuit 6. The DDS circuit 6 has the same configuration as the DDS circuit 5. The frequency data of the DDS circuit 6 in which the capacity of the adder is 2 ²³ and the frequency resolution is 1 Hz is the fixed data 100
00, the reference clock frequency is 2 ²³ [Hz]
When the output frequency is 10kHz, the phase comparator 2
Is input to the other input terminal of, and a phase-locked loop is formed. At this time, the DDS 6 operates as a frequency divider having a frequency division ratio of 10k / 2 ²³ , and the output frequency of the voltage controlled oscillator 4 is 10 kHz, that is, 2 ²³ [Hz] synchronized with the reference frequency 10 MHz. . As described above, by using the DDS circuit 6 as a frequency divider, the change of the frequency division ratio is much more free in design than the use of a normal frequency divider that involves hardware changes. The frequency will also increase. In the above embodiment, the reference frequency is 10M.
When the frequency is other than Hz, it can be easily dealt with by changing the frequency data of the frequency divider 1 or the DDS circuit 6 so that the two input frequencies to the phase comparator 2 become equal. Further, it is needless to say that the DDS circuit 5 and the DDS circuit 6 do not have to have the same configuration as long as the configuration can realize the above-mentioned function. As described above, according to the signal generator of the present invention, a high-level clock generally used as a reference clock for a DDS circuit using a binary adder capable of obtaining a desired frequency resolution. Accuracy reference frequency (10 MH
z, 5 MHz, 1 MHz, etc.) can be used.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a configuration block diagram showing an embodiment of a signal generator according to the present invention. FIG. 2 is a block diagram showing an example of a conventional DDS circuit. [Explanation of Codes] 1 Frequency divider 2 Phase comparator 3, 25 Low pass filter 4 Voltage controlled oscillator 5, 6 DDS circuit 21 Binary type adder 22 Latch 23 ROM 24 D / A converter

Claims (1)

A first DDS circuit having a binary adder, a frequency divider for dividing a reference frequency, a phase comparator having an output of the frequency divider as an input, and the phase comparator. The oscillation frequency depends on the output of the first D
An oscillator, which changes in the vicinity of a reference clock required by the DS circuit and is supplied to the first DDS circuit, and a binary type adder, receives the output of the oscillator as a reference clock, and the output frequency is the frequency divider. Second D given the frequency data that is equal to the output frequency of
A signal generator comprising a DS circuit.