JPH05167995A - Transmission device for digital signal - Google Patents

Abstract

PURPOSE:To supply audio data to a system whose input channels are fixed in number. CONSTITUTION:An audio data which are converted into parallel data and discontinuous on the time base are written in a memory 7 at the sampling frequency of a video signal and also read out with a signal corresponding to a detected transmission channel. Then channel identification data are switched to data indicating a non-input channel and the data are switched to mute-level data and outputted in a period wherein the data are read out when it is assumed that the data are read out with the signal corresponding to the non-input channel. Then data of an optional number of channels less than a maximum number of channels are selected and outputted. Therefore, data of the optional number of channels less than the maximum number of transmission channels can be selected and outputted at all times without depending upon the number of the transmission channels, and consequently this device is applicable to the system whose number of channels is fixed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device for superimposing digital data such as digital audio data on digital video data and converting it into serial data for transmission, and is particularly suitable for superimposing digital audio data of a plurality of channels. The present invention relates to a digital signal transmission device.

[0002]

2. Description of the Related Art Conventionally, as a method for converting digital data into 1-bit unit serial data and transmitting it,
For example, the Audio Engineering Society (AES) has proposed a digital audio serial interface standard. According to this standard, a redundant bit is added to a 20-bit digital audio signal to make it 32 bits, and then serial transmission is performed bit by bit from the least significant bit side. As a result, a 2-channel digital audio signal can be transmitted through a single transmission path.

By the way, in recent years, influenced by the development of digital VTR, a serial digital interface standard for converting a digital video signal on which digital audio signals of up to four channels are superimposed into serial data and then transmitting the serial data is social.・ Proposed by Motion Picture and Television Engineers (SMPTE). This is a method in which an audio signal is intermittently inserted in horizontal and vertical sync areas of a video signal, converted into serial data, and then transmitted. As a result, it becomes possible to transmit the digital video signal and the digital audio signals of up to 4 channels through one transmission path.

[0004]

In the serial data transmission method as described above, generally, received serial data is converted into parallel data and only audio data is separated and extracted. Then, the time axis processing is performed so that the audio data that is intermittently output is continuous on the time axis, for example, parallel data, that is, a signal having a sampling frequency of video data, only the audio data is stored in a memory in field or frame units (one field or one frame). The memory address is reset for each period corresponding to (1), and a signal having a frequency corresponding to the number n of channels of the transmitted audio data is read from the memory in units of fields or frames. With such processing, an audio signal of an arbitrary number of channels can be transmitted. However, in a system in which the number of input channels of an audio signal is fixed, and when the number of input channels of the system is different from the number of transmission channels, there is a problem that the audio signal cannot be supplied to the system.

In view of the above-mentioned conventional technique, an object of the present invention is to provide a digital signal transmission apparatus capable of supplying an audio signal to a system having a fixed number of input channels and a different number of transmission channels.

[0006]

In order to achieve the above object, the present invention provides means for time-division multiplexing different digital data of n channels into one continuous digital data string, and a channel for the digital data string. Means for adding identification data, time-axis-compressed, time-axis-multiplexed on a predetermined area of a horizontal or vertical synchronizing signal of the digital video signal, and means for converting the digital video signal into serial data in 1-bit units for transmission. Means for receiving the serial data, converting the serial data into parallel data, and reconstructing the digital video signal; means for separating and extracting the time-division-multiplexed digital data from the reconstructed digital video signal and sequentially writing it in a memory; Means for detecting the number of transmission channels of the digital data separated and extracted; Means for reading from said memory at a signal of a frequency based on the number of transmission channels, not transmitted to the digital data read out from the memory (m-
n) means for inserting digital data of a predetermined level to which channel identification data is added as digital data of the channel.

[0007]

In the transmitting system, the n-channel digital data is time-division multiplexed to form an intermittent time-division multiplexed signal so as to match the digital video signal, and the intermittent time-division multiplexed signal is time-axis multiplexed with the digital video signal. Is transmitted.

In the receiving system, the intermittent time division multiplex signal is separated from the received digital video signal, and the means writes / reads to / from the memory.
At this time, the reading from the memory is performed with a signal having a frequency based on the detected number of transmission channels, and the data of each channel is equal to one sampling period of the digital data before time division multiplexing. Then, the period corresponding to the period in which the data of the (mn) channel that has not been transmitted is read is switched to the mute level data, and the channel identification data corresponding to each data of the (mn) channel is added. Therefore, this is equivalent to the case where digital data of the maximum number m of transmission channels is always transmitted, and does not depend on the number of transmission channels of the serial data,
It is possible to output digital data of an arbitrary number of channels up to m channels.

[0009]

Embodiments of the present invention will be described below with reference to the drawings. 1 is a block diagram showing an embodiment of a receiving circuit of a digital signal transmitting apparatus according to the present invention, FIG. 2 is a block diagram showing an embodiment of a transmitting circuit of a digital signal transmitting apparatus according to the present invention, and FIG. 2 is a waveform diagram of each part for explaining the operation of the block diagram of FIG. 2, FIG. 4 is a waveform diagram of each part of the block diagrams of FIGS. 1 and 2, and FIG. 5 is a specific example of the memory control circuit 4 in the block diagram of FIG. FIG. 6 is a block diagram showing one specific example of the audio data processing circuit 8 in the block diagram of FIG. 1, and FIG. 7 is a waveform diagram for explaining each operation of the block diagrams of FIGS. 5 and 6.

In FIG. 2, the number of bits n ₂ from the terminal 160.
Is supplied to the sync detection circuit 10 and the data selector circuit 12. The sync detection circuit 10 detects a horizontal sync signal and a vertical sync signal on the basis of the input video data, and outputs a frame pulse signal (frame pulse in FIG. 4) of 1 and a frame cycle.
A line pulse signal (line pulse signal in FIG. 4) having a line cycle is output and supplied to the timing generation circuit 11. In the timing generation circuit 11, terminals 170, 180, 19
Channel identification data CHM, CHL of audio data supplied via 0, 200 are output. In this embodiment, the data CHM and CHL are CHM: LOW and CHL: L as shown in FIG.
Channel 1 (CH1) when OW, CHM: LOW, CHL: HIGH
Shows audio data of channel 2 (CH2), CHM: HIGH, CHL: LOW, channel 3 (CH3), CHM: HIGH, CHL: HIGH, channel 4 (CH4). However, in this embodiment, the case of three-channel transmission of channels 1, 2, and 3 will be described. At the same time, in the timing generation circuit 11, based on the frame pulse signal and the line pulse signal from the synchronization detection circuit 10, a reset signal of the memory address (RST-W in FIG. , RST-R) to supply the signal selector SEL (SEL in FIG. 3) indicating the area in the horizontal synchronization period into which the time-axis compressed audio signal is inserted to the data selector circuit 12 and the time-axis processing circuit 15, respectively. In the data selector circuit 13, the audio data of channel 1, channel 2, channel 3, and channel 4 sampled with the signal of frequency FS and supplied via terminals 170, 180, 190, and 200 respectively with the number of bits n ₁ are timing. Of the audio data of channels 1, 2, 3 and 4, selected by the channel identification data signals CHM and CHL from the generation circuit 12, the audio data of the three channels of channels 1, 2, and 3 are time-division multiplexed. Signal is output. Then, the signals CHM and CHL indicating the channels from the timing generation circuit 11 are added, and n ₁ +2 bit data AUD is added.
1 (AUD1 in FIG. 3) is input to the post-division processing circuit 14. In the division processing circuit 14, a redundant bit such as a parity bit is added to the audio data AUD1 of the bit number n ₁ +2 from the data selector circuit 13 and an integer multiple of the bit number n ₂ of the video data supplied via the terminal 160. Audio data AUD1 with redundant bits added
Is divided by the multiple. In this embodiment, the number of bits obtained by adding redundant bits to the audio data AUD1 3 and 3 times the number of bits n ₂ video data, shows a case of dividing the audio data AUD1 the three data There is. Audio data AUD having the same bit number n ₂ as the video data divided into three data by the division processing circuit 14.
2 (AUD2 in FIG. 3) is supplied to the time axis processing circuit 15. The time axis processing circuit 15 is composed of, for example, a memory, starts writing to the memory based on the RST-W signal from the timing generation circuit 11, and starts writing to the memory based on the RST-R signal from the timing generation circuit 11. To start reading from. This RST-W signal is synchronized with the signal of the frequency FS for sampling the audio signal, and the first data of the channel 1 of the audio data AUD2 (Fig. 3 AUD2
The data is written in the memory with a signal having a frequency 12 times the frequency FS from 1-1). Then, the output signal SEL from the timing generation circuit 11 is output based on the RST-R signal (in this embodiment, a delay of about 1 line compared to the RST-W signal) synchronized with the signal of the frequency Vck for sampling the video signal. Only during the HIGH level period, a signal having the same frequency as the above frequency Vck is read from the memory. As a result, the audio data input in the period corresponding to approximately one line is output during the predetermined period of the horizontal synchronization period (the output signal SE from the timing generation circuit 11).
Data AUD3 compressed on the time axis during the period of L HIGH level)
(AUD3 in Fig. 3) is output. The output data AUD3 from the time axis processing circuit 15 is the data selector circuit 12
Is supplied to one terminal of the timing generation circuit 1
A signal DATA (DATA in FIG. 3) in which the video data input via the terminal 160, which is supplied to the other side by the output signal SEL from 1, is selectively output, and the video data and the audio data are time-division multiplexed. Is output. The output signal DATA from the data selector circuit 12 having the bit number n ₂ is supplied to the parallel / serial conversion circuit 16 and has a frequency of n ₂ × Vck, for example, which is output bit by bit from the least significant bit. It is converted into serial data and output via the line driver circuit 17 and the terminal 210.

The 1-bit unit serial data from the transmission circuit shown in FIG. 2 is supplied to the reception circuit shown in FIG.

In FIG. 1, serial data input via a terminal 100 is supplied to a serial / parallel conversion circuit 1, and video data and audio data from the data selector circuit 12 shown in FIG. 2 are time-division multiplexed. Signal DAT corresponding to the signal DATA having the number of bits n ₂ (DATA in FIG. 3)
A'is output. The output signal DATA ′ from the serial / parallel conversion circuit 1 is supplied to the audio / video separation circuit 5 and the synchronization detection circuit 2. Sync detection circuit 2
Then, the output signal DAT from the serial / parallel conversion circuit 1
The horizontal synchronizing signal and the vertical synchronizing signal of A ′ are detected and supplied to the timing generating circuit 3. In the timing generation circuit 3, a signal FS (FS in FIG. 8) having a frequency equal to the sampling frequency of the audio signal is generated based on the horizontal synchronization signal and the vertical synchronization signal from the synchronization detection circuit 2 and the signal FS.
2FS frequency signal 2FS, 4 times frequency signal 4F
S (2FS, 4FS in FIG. 8) and a signal Ac that is an integer multiple of the signal 4FS and is used as a read clock of the memory.
k, and a signal SEL 'corresponding to the signal SEL from the timing generation circuit 11 shown in FIG. 2 for switching between audio data and video data is generated. Of the generated signals, FS, 2FS, 4FS, Ack are sent to the memory control circuit 4 and the audio data processing circuit 8, and
SEL ′ is supplied to the audio / video separation circuit 5. The audio / video separation circuit 5 separates the output signal DATA ′ from the serial / parallel conversion circuit 1 into video data and audio data having the bit number n ₂ . At this time, the video data is output through the terminal 110 by replacing the audio data area of the signal DATA ′ with the original level data, that is, the horizontal sync signal level data. Then, the audio data from the audio / video separation circuit 5 is supplied to the three-sample synthesis circuit 6,
One sample is made up of 3 samples of audio data having the bit number n ₂ , and the original audio data having the bit number n ₁ +2 is output. Since the audio data of the bit number n ₁ +2, which is the output signal from the 3-sample synthesis circuit 6, is discontinuous on the time axis, the time axis processing is performed using the memory 7.
That is, as shown in FIG. 4, based on the frame pulse signal and the line pulse signal from the synchronization detection circuit 2, the sampling signal Vck of the video signal is set to 3 in one frame period.
Writing to the memory is started by the signal RST-W 'synchronized with the divided signal Vck / 3, and in synchronization with the audio data from the 3-sample synthesis circuit 6, that is, the output signal SEL' from the timing generation circuit 3. The audio data from the sample synthesizing circuit 6 is written in the memory with the above-mentioned signal Vck / 3 only during the period when the signal is HIGH level. Then, for example, the memory control circuit 4 configured by the block diagram shown in FIG. 5 reads the audio data. Further, the channel identification data CHM, CHL of the audio data which is the output signal from the three-sample synthesis circuit 6 is simultaneously supplied to the memory control circuit 4 constituted by the block diagram shown in FIG. 5, for example.

In FIG. 5, channel identification data CHM, CHL (CHM, CHL in FIG. 7) supplied via terminals 220 and 230.
Are an inverter circuit 20 and AND circuits 24 and 2, respectively.
5 and the inverter circuit 21, and the AND circuits 23 and 25. The CHM whose level has been inverted by the inverter circuit 20 is sent to the AND circuits 22 and 23 and the inverter circuit 21
The CHL whose level has been inverted at is input to the AND circuits 22 and 24, respectively. Also, AND circuits 22, 23, 2
The output signal SEL ′ (SEL ′ in FIG. 7) from the timing generation circuit 3 is also input to the terminals 4 and 25 via the terminal 240. Therefore, the output signal A1 from the AND circuit 22 is CHM: LOW.
When the level, CHL: LOW level, that is, it is HIGH level while the audio data of channel 1 is written in the memory 7. Similarly, the output signal A from the AND circuit 23
2 is at the CHM: LOW level and CHL: HIGH level, that is, at the HIGH level while the audio data of the channel 2 is written in the memory 7, the output signal A3 from the AND circuit 24 is CHM: HIGH level, CHL: LOW. Level, that is, the audio data of channel 3 is stored in memory 7
Becomes high level during the period of being written to the AND circuit 25
Output signal A4 is at the CHM: HIGH level and at the CHL: HIGH level, that is, at the HIGH level while the audio data of channel 4 is written in the memory 7. Therefore, when the audio data of channel 1, channel 2, channel 3, and channel 4 is transmitted as shown in FIG. 7, the output signals A1, A2, A3, A4 from the AND circuits 22, 23, 24, 25 are output. In the case where the pulse signals having the HIGH level are sequentially output during the period corresponding to one cycle of the signal of Vck / 3, and the audio data of channel 1, channel 2, and channel 3 is transmitted as in the present embodiment, , AND circuits 22, 23, 24 output signals A1,
As A2 and A3, pulse signals that are at the HIGH level for a period corresponding to one cycle of the signal of Vck / 3 are sequentially output, but the output signal A4 from the AND circuit 25 is always
A LOW level signal is output. This AND circuit 22,
Output signals A1, A2, A3, A from 23, 24, 25
4 is an RS flip-flop circuit 26, 27, 28, 29
, And the reset terminal of the RS flip-flop circuits 26, 27, 28, 29 is supplied with the line pulse signal from the synchronization detection circuit 2 via the terminal 250. From the RS flip-flop circuits 26, 27, 28, 29, the output signals A1, A2 from the AND circuits 22, 23, 24, 25 are provided line by line.
Signal B that goes HIGH in synchronization with the rising edges of A3 and A4
1, B2, B3, B4 are output and supplied to the latch circuit 30. In the latch circuit 30, at the rising edge of the line pulse signal supplied to the reset terminals of the RS flip-flop circuits 26, 27, 28, 29 via the terminal 250, the output signal B1, from the RS flip-flop circuits 26, 27, 28, 29 is output. Latch B2, B3 and B4. Therefore, the output signals C1, C2, C3, C4 from the latch circuit 30 indicate whether or not the audio data of each channel is supplied line by line. That is, from the latch circuit 30, as shown in FIG. 7, channel 1, channel 2, channel 3,
When the audio data of channel 4 is transmitted,
As the output signals (C1, C2, C3, C4), all HIGH level signals ((1.1.1.1.1) in FIG. 7) are output,
Channel 1, channel 2, channel 3 as in this embodiment
When the audio data of is transmitted, the output signal C
1, C2 and C3 are high level signals, and only the output signal C4 is a low level signal ((1.
・ 0)) is output. The output signals C1, C2, C3, C4 from the latch circuit 30 are sent to the data selector circuit 38.
Is supplied to. In the data selector circuit 38, the output signals C1, C2, C3, C4 from the latch circuit 30 are input to the terminal 26.
It is selectively output by the signals FS and 2FS from the timing generation circuit 3 supplied via 0 and 270. The output signal CH-SL from this data selector circuit 38 is, for example, FS: L.
When OW level, 2FS: LOW level, C1 is selected,
When FS: LOW level, 2FS: HIGH level, C2 is selected, when FS: HIGH level, 2FS: LOW level, C3 is selected, and when FS: HIGH level, 2FS: HIGH level, C4 is selected. Therefore, the output signal CH-SL from the data selector circuit 38 is ((C1, C2, C3, C4) = (1,1,1) when audio data of channels 1, 2, and 3 are transmitted as shown in FIG. 1,0)) is FS: HIGH level,
2FS: LOW level only during the HIGH level period, and HIGH level signal other than this period. The output signal CH-SL from the data selector circuit 38 is supplied to the audio data processing circuit 8 via the terminal 280 and also to the AND circuit 39. Further, the signal 4FS (4FS in FIG. 8) supplied from the timing generation circuit 3 via the terminal 290 is received by the latch circuits 34 and 35, respectively, and the signal ACK from the timing generation circuit 3 supplied via the terminal 300 is received. The output signal from the latch circuit 34 is supplied to the AND circuit 37, and the output signal from the latch circuit 35 is also supplied to the AND circuit 37 via the inverter circuit 36. Therefore, the signal 4FS is output from the AND circuit 37.
Period corresponding to one cycle of signal ACK in synchronization with the rising edge of
The signal EN that becomes HIGH level is output. And FIG.
As shown in, the signal EN is output from the AND circuit 39 as the memory read signal RE only while the signal CH-SL supplied to the other side of the AND circuit 39 is at the HIGH level.
It is supplied to the memory 7 via the terminal 340.

Then, the audio data including the channel identification data read from the memory 7 is supplied to the audio data processing circuit 9 constructed by the block diagram shown in FIG. 6, for example.

In FIG. 6, the audio data from the memory 7 supplied through the terminal 380 is supplied to one terminal of the data selector circuit 40, and the data of the mute signal level is supplied to the other terminal. ing. At the same time, the identification data CH-M and CH-L from the memory 7 are supplied to one terminal of each of the data selector circuits 41 and 42. The output signals FS and 2FS from the timing generation circuit 3 which are supplied to the other terminals of the data selector circuits 41 and 42 through terminals 360 and 370, respectively, are delayed by the delay circuit 4.
At 4 and 45, signals FS ′ and 2FS ′ delayed by a period corresponding to one cycle of a signal having a frequency of 4FS are supplied. Then, the output signal CH-SL from the memory control circuit supplied via the terminal 350 is delayed by the delay circuit 43.
At the period when the signal CH-SL 'is at the LOW level, the mute signal level and the signals FS', 2F are delayed by the signal CH-SL 'delayed for a period corresponding to one cycle of the signal of 4FS.
When S'is selected and the signal CH-SL 'is at the high level, the audio data and the channel identification data CH-M,
CH-L is selected respectively. As a result, the output signals AUD ', CH-M ", CH- from the data selector circuits 40, 41, 42.
L "is the audio data in which the mute level data including the channel identification data indicating the channel 4 that has not been transmitted is inserted. Therefore, the audio processing circuit 8 always outputs the maximum number of transmission channels of 4 channels. The data is output and supplied to the audio channel separation / selection circuit 9. Then, the signal AUD 'in which the audio data of four channels is time division multiplexed by the audio channel separation / selection circuit 9 is the channel identification data CH-M ", CH-L "
Is divided into each channel by, and each channel data is converted into audio data of sampling frequency FS, and then data of an arbitrary channel is selected and terminals 120, 130,
It is output via 140 and 150.

In the above-mentioned embodiments, the case where the maximum number of transmission channels is 4 audio data has been described, but the present invention is not limited to this, and the present invention is applied even in the case of an arbitrary maximum number of transmission channels. It goes without saying that it is possible.

Further, in the above-described embodiment, the case where the audio data of the non-input channel is switched to the mute level data and output is described, but the present invention is not limited to this, and the memory control circuit described in the present embodiment. Even when the audio processing circuit 8 only adds the channel identification data of the non-input channel to the audio data read from the memory in step 4, the audio data of the non-input channel is the same as the audio data of other channels. It does not deviate from the purpose of.

In the above-mentioned embodiment, the case where the maximum number of transmission channels is 4 and the audio data of 3 channels is transmitted has been described, but the present invention is not limited to this, and even in the case of 1 or 2 channel transmission. It is applicable and generally applicable when transmitting an arbitrary number of channels that does not exceed the maximum number of transmission channels.

In the above-mentioned embodiment, the case of 4-channel audio data as the data to be time-axis multiplexed with the video data has been described, but the present invention is not limited to this, and other digital data other than audio data can be used. Is also available.

In the above-described embodiment, the case where the reset signal for resetting the memory address is output in the unit of the frame period of the video signal has been described, but the present invention is not limited to this. It is obvious that the present invention can be applied to the case where the reset signal is output in the unit of the period equal to the integral multiple of the field period.

[0021]

As described above, according to the present invention, when converting serial data into parallel data at the time of reception in a device that converts parallel data into serial data and transmits the converted audio data, A channel is detected, and a signal corresponding to the channel is read from the memory. Then, assuming that the audio data of the maximum number of transmission channels has been transmitted, when reading from the memory with a signal according to the non-input channel, the channel identification data indicates the non-input channel during the period when the audio data is read. Switch to data and output. This makes it equivalent to the case where audio data of the maximum number of transmission channels is always transmitted regardless of the number of transmission channels, and audio data of any number of channels less than the maximum number of transmission channels can be selected and output. This has the effect of enabling the supply of audio signals to a fixed number of systems.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a receiving circuit of a digital signal transmission device according to the present invention.

FIG. 2 is a block diagram showing an embodiment of a transmission circuit of a digital signal transmission device according to the present invention.

FIG. 3 is a waveform diagram of each part for explaining the operation of the transmission circuit according to the first embodiment of the present invention.

FIG. 4 is a waveform diagram for explaining the operation of the receiving circuit and the transmitting circuit according to an embodiment of the present invention.

FIG. 5 is a block diagram showing a specific example of a memory control circuit in a receiving circuit according to an embodiment of the present invention.

FIG. 6 is a block diagram showing a specific example of an audio data processing circuit according to an embodiment of the present invention.

FIG. 7 is a waveform chart for explaining the operation of the memory control circuit in the receiving circuit according to the first embodiment of the present invention.

FIG. 8 is a waveform chart for explaining the operation of the memory control circuit and the audio data processing circuit according to the first embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Serial / parallel conversion circuit, 4 ... Memory control circuit, 5 ... Audio / video division circuit, 7 ... Memory, 8 ... Audio data processing circuit, 9 ... Audio channel division selection circuit, 11 ... Timing generation circuit, 12, 13 ... data selector circuit, 14 ... division processing circuit, 15 ... time axis processing circuit, 16 ... parallel / serial conversion circuit, 26, 27, 28, 29 ... RS flip-flop circuit, 30 ... latch circuit, 38, 40, 41, 42 ... Data selector circuit, 43, 44, 45 ... Delay circuit.

Claims (6)

[Claims] 1. A first digital data string of a maximum number of transmission channels m (≧ 2), wherein n channels (n ≧ 1) different digital data to be transmitted are time-division multiplexed into one continuous digital data string. Means for dividing the digital data sequence for each period of the horizontal or vertical synchronizing signal of the digital video signal, adding channel identification data to the digital data of each division, and time-axis compression to make an intermittent time division multiplexed signal, Second means for inserting the intermittent time division multiplexed signal into the digital video signal in the time axis by inserting it into at least one of the predetermined areas of the horizontal or vertical synchronizing signals of the digital video signal, and the intermittent time division multiplexed signal in the time axis Third means for converting the multiplexed digital video signal into 1-bit unit serial data and transmitting the serial data; Fourth means for receiving, fifth means for converting the received serial data into parallel data to reconstruct the digital video signal, and the intermittent time division multiplexed signal from the reconstructed digital video signal. A sixth means for separating and extracting only the intermittent time division multiplex signal into the memory sequentially, and a seventh means for detecting the number of transmission channels of the intermittent time division multiplex signal to be sequentially written into the memory from the channel identification data, Eighth means for reading the digital data from the memory with a signal having a frequency based on the number of transmission channels detected by the seventh means, and the digital data read by the eighth means are not transmitted (m- n) Insert digital data of a predetermined level with channel identification data added as digital data of the channel A digital signal transmission device, characterized in that it is configured to output digital data of a predetermined number of channels out of m channels of digital data. 2. The seventh and eighth means detect from the channel identification data for each predetermined time t ₁ whether or not digital data of the intermittent time division multiplexed signal is transmitted for each channel. Means for generating m signals having a frequency equal to the sampling frequency F of the digital data and different in phase from each other, and a tenth means of the m signals by the eleventh means. 12. The digital signal transmission device according to claim 1, further comprising: a twelfth means for reading out from the memory based on the signal of the number n of transmission channels resulting from the means of 10. 3. The ninth means is not used for the twelfth means among the m number of signals by the eleventh means when the digital data of m channels is transmitted (mn). ) Thirteenth means for detecting a period to be read from the memory based on the number of signals, and fourteenth means for switching the digital data in the detection period by the thirteenth means to mute level data for output. -N) 15th means for adding channel identification data corresponding to each of the signals to the mute level data by said 14th means. Digital signal transmission equipment. 4. The ninth means is not used for the twelfth means among the m number of signals by the eleventh means when the digital data of m channels is transmitted (mn). ) Thirteenth means for detecting a period for reading from the memory based on the signals, and channel identification data added to the digital data read from the memory by the twelfth means,
4. The digital signal transmission device according to claim 1 or 2, further comprising: -n) fourteenth means for switching and outputting channel identification data corresponding to each of the n signals. 5. The sixth and seventh means, wherein a reset signal for resetting a write address and a read address to the memory is L of a field period of the video data.
5. The digital signal transmission device according to claim 1, 2, 3 or 4, further comprising means for making a signal having a doubled period (L = 1, 2, 3, ...). 6. In the means for time-multiplexing the AUX data string, the AUX data is audio data having a bit number M (M> m, m: the bit number of the video data), and the audio data has redundant bits. Means for dividing the data into J (J = 2, 3, ...) Bit number m data, and the divided bit number m data in at least one of the horizontal or vertical sync area of the video data. 6. A digital signal transmission device according to claim 1, 2, 3, 4, or 5, further comprising: means for axial multiplexing.