JPH051671B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a video signal A/D conversion circuit in a television receiver using a panel type display section.

[Prior art and its problems] In recent years, small portable television receivers that use liquid crystal display panels in their display sections have been put into practical use. This kind of television receiver using a conventional liquid crystal display panel converts a video signal amplified by a video amplification circuit into a digital signal by an A/D conversion circuit, and drives the liquid crystal display panel with this digital signal. I have to. However, due to its characteristics, the liquid crystal display panel has a narrow gradation range from the white level to the black level, making it difficult to obtain images with good contrast. In order to solve this problem, conventional methods detect the average value of the television video signal and set the reference voltage of the A/D conversion circuit accordingly to obtain good contrast. In other words, the video signal does not always change from the white level to the black level, and there is no need to A/D convert the entire range of the video signal.
The contrast is improved by varying the conversion level of the conversion circuit.

However, in the conventional method, the reference voltage of the A/D conversion circuit is determined based on the average value of the image signal as described above, which has the disadvantage that the gradation near the white level and black level is not uniform. Ta.

[Object of the Invention] The present invention has been made in view of the above points, and provides a video signal A/D conversion that can obtain optimal contrast and make the gradation near the white level and black level clearer. The purpose is to provide circuits.

[Summary of the Invention] The present invention provides A/D conversion of a video signal in accordance with the number of sampling clocks for each of the white level and black level of the digitized video signal in a television receiver using a panel type display section. It was designed to do so.

[Embodiment of the Invention] An embodiment of the present invention will be described below with reference to the drawings. First, the schematic structure of the main parts will be explained with reference to FIG. In FIG. 1, 1 is a video amplification circuit, which amplifies the video signal a sent from a video detection circuit (not shown) and sends it to the sync separation circuit 2 and A/D.
At the same time as outputting to the conversion circuit 3, the audio signal b is outputted to an audio circuit (not shown). The A/D conversion circuit 3 receives a chip enable signal from the control circuit 5.
In addition to inputting CE, an upper limit reference voltage V _H and a lower limit reference voltage V _L are applied via the level shifter 4 . The A/D conversion circuit 3 converts the video signal a sent from the video amplifier circuit 1 into a 4-bit digital signal c according to the upper limit reference voltage _VH and lower limit reference voltage _VL , and controls the signal. Output to circuit 5. Further, the synchronization separation circuit 2 separates a horizontal synchronization signal and a vertical synchronization signal from the input video signal a, and outputs them to the control circuit 5. This control circuit 5 includes the A/D conversion circuit 3 and the synchronous separation circuit 2.
It performs a display control operation according to input signals from the circuit, and provides common side data and a shift clock to the first drive circuit 7 via the shift register 6, and sends segment side data and shift clock to the shift register 8 and the second drive circuit. Give to 9.
Then, the first drive circuit 7 and the second drive circuit 9
The liquid crystal display panel 10 is driven for display. The liquid crystal display panel 10 has a matrix configuration of, for example, 120×160 dots. Further, the control circuit 5 counts the sampling clocks of the white level and black level of the video signal, as will be described in detail later, and outputs control voltages Va and Vb determined by the number of sampling clocks to the level shifter 4. .
The level shifter 4 sets an upper limit reference voltage V _H and a lower limit reference voltage V _L according to the control voltages Va and Vb from the control circuit 5 and outputs them to the A/D conversion circuit 3 .

Next, details of the main parts of the control circuit 5 will be explained in the second section.
This will be explained using figures. 4-bit video signals h to k sent from the A/D conversion circuit 3 are input to a white level detection circuit 11 and a black level detection circuit 12. A sampling clock φ _S of 3.12 MHz, for example, is input to the white level detection circuit 11 and the black level detection circuit 12. This sampling clock φ _S is generated at the output timing of effective video signals excluding the horizontal synchronization signal and the vertical synchronization signal. and,
The white level detection circuit 11 has an upper limit reference voltage V _H
When a higher video signal is input, the sampling clock φ _S is set as the white level sampling clock n and outputted to the frame switching circuit 13. Also,
The black level detection circuit 12 has a lower limit reference voltage V _L
When a lower video signal is input, the sampling clock φ _S is set as the black level sampling clock p and output to the frame switching circuit 13. This frame switching circuit 13 selects the output of the white level detection circuit 11 or the black level detection circuit 12 according to the frame switching signal m, and outputs it to the D/A counter control circuit 14. The frame switching signal m is
The signal level is inverted to "1" or "0" every time the vertical synchronizing signal is applied, and is input to the D/A counter control circuit 14 together with the frame switching circuit 13 described above. This D/A counter control circuit 14 includes a level counter, and alternately counts the white level sampling clock n or the black level sampling clock p inputted via the frame switching circuit 13 in accordance with the frame switching signal m. do. The level counter is set to be able to count 2000 or more, for example, and for each count, the white level D/A counter 15 and the black level D/A counter 15 are set according to the count value.
Counter clocks u, s and count up/down switching signals v, t are output to the counter 16. That is, when counting the white level, if the count value in each frame is "2000" or more, an up command is output to the white level D/A counter 15, and if it is less than "1000", a down command is output to the white level D/A counter 15. Further, when counting the black level, if the count value in each frame is "2000" or more, a down command is output to the black level D/A counter 16, and if it is less than "1000", an up command is output to the black level D/A counter 16. and the white level D/A counter 15,
The count value of the black level D/A counter 16 is subjected to D/A conversion by a white level D/A conversion circuit 17 and a black level D/A conversion circuit 18, respectively, and sent to the level shifter 4. This level shifter 4 is composed of an upper limit reference voltage level shifter 4a and a lower limit reference voltage level shifter 4b, and level-shifts the outputs of the white level D/A conversion circuit 17 and black level D/A conversion circuit 18, so that the upper limit reference voltage _VH , It is output to the A/D conversion circuit 3 as the lower limit reference voltage V _L.

Further, the D/A counter control circuit 14 is configured as shown in FIG. That is, in FIG. 3, 21 is, for example, a 12-bit level counter, which counts clocks n or p supplied from the frame switching circuit 13. A decoder 22 decodes the count value of the level counter 21 and outputs a signal from the output line 22a when the count value is ``1000'' or more, and from the output line 22b when the count value is ``2000'' or more. Reference numeral 23 denotes a 7-bit shift register, for example, which performs timing control within the circuit using an internal basic clock φ. That is, the shift register 23 shifts the frame switching signal m and outputs the one-stage delayed (x1) and two-stage delayed (x2) outputs and the EX OR circuit (exclusive OR circuit) 2.
4 constitutes a one-shot circuit, and its output is input to AND circuits 28 and 30 to create a pulse (s or u) at the time of frame switching. In addition, the shift register 23 has a 4-stage delay (×4) and a 5-stage delay (×
5) and the EX OR circuit 25 set the flip-flops 26 and 27 and the level counter 2.
1 and perform initial settings. Furthermore,
The seven stage delayed (x7) output of the shift register 23 is input to the AND circuit 28 and also to the AND circuit 30 via the inverter 29 to determine which of the pulse signals s and u to output when switching frames. It is used as a signal. Further, the outputs of the flip-flops 26 and 27 are inputted to AND circuits 28 and 30 via an EX NOR circuit 31 to control whether or not to output pulses s and u during frame switching. In addition, flip-flops 26, 27
The output of the decoder 22 is input to a NOR circuit 32, and the output is taken out directly or via an inverter 33, and signals t and v are generated for up-counting or down-counting depending on the output of the decoder 22.
In other words, in a white frame (m = "High"), when the count value of the level counter 21 does not exceed "1000", t = 0, v = 1, and the white level D/
A down command is given to the A counter 15, and on the other hand, since both flip-flops 26 and 27 remain set, the output of the EX NOR circuit 31 becomes "1" and the signal u is output from the AND circuit 28.
Therefore, the white level D/A down counter 15 counts down.

In addition, when the count value of the level counter 21 is "1000" or more [2000] in the white frame, t
= 0, v = 1, and the output of the EX NOR circuit 31 = 0, so neither the signals s nor u are output and there is no change.

Furthermore, when the count value of the level counter 21 is "2000" or more in a white frame, t=1, v=0
Therefore, an up command is issued to the white level D/A counter 15. Then, the output of the EX NOR circuit 31 becomes "1", the signal u is outputted from the AND circuit 28, and the white level D/A counter 15 operates up. On the other hand, even at the black level, the signal t/v,
The operation is the same as in the case of the white level, except that s/u is changed.

Next, the overall operation of the above embodiment will be explained with reference to the timing chart of FIG. In FIG. 1, a video amplification circuit 1 amplifies a video signal a shown in FIG. Output to audio circuit. The synchronization separation circuit 2 separates a horizontal synchronization signal and a vertical synchronization signal from the video signal and outputs them to the control circuit 5. The A/D conversion circuit 3 also receives an upper limit reference voltage _VH and a lower limit reference voltage supplied from the level shifter 4.
The video signal is converted into 4-bit digital data c according to V _L and output to the control circuit 5. This control circuit 5 outputs a vertical scanning timing signal to a shift register 6 in synchronization with a vertical synchronization signal, and also outputs a digital video signal to a shift register 8. The shift register 6 sequentially shifts the data given by the control circuit 5 according to a predetermined timing signal, and according to the shifting operation, the first
The drive circuit 7 scans the liquid crystal display panel 10 in the vertical direction. Further, the data held in the shift register 8 is sent to a second drive circuit 9 in synchronization with a timing signal from the control circuit 5, and the second drive circuit 9 scans the liquid crystal display panel 10 in the horizontal direction. Ru.

On the other hand, when the control circuit 5 receives the video signal from the A/D conversion circuit 3, the white level detection circuit 11 detects the video signal that is higher than the upper limit reference voltage _VH , and as shown in FIG. In addition to outputting a white level sampling clock n, the black level detection circuit 12 detects a video signal below the lower limit reference voltage V _L and outputs a black level sampling clock p. The white level sampling clock n and the black level sampling clock p are alternately selected for each frame by the frame switching circuit 13 and sent to the D/A counter control circuit 14. As shown in FIG. 4, this D/A counter control circuit 14 counts the white level sampling clock n when the frame switching signal m is at a high level, and counts the black level sampling clock p when it is at a low level.
is counted, and a control signal is output in accordance with the count value when the frame switching signal m is switched. now,
When the frame switching signal m switches from low level to high level, the frame switching circuit 13 switches to the white level detection circuit 11 side, and the D/
The level counter of the A counter control circuit 14 is cleared, and the white level sampling clock n is counted in this level counter. If the count value is less than "1000" at the end of the frame, the signal v output from the D/A counter control circuit 14 is held as "1" as shown in FIG. White level D/
A down command is given to the A counter 15. At this time, a counter lock u is output from the D/A counter control circuit 14, and the white level D/A counter 15 counts down. In addition, if there are many white level components included in the video signal and the above count value is "2000" or more, the up-down switching signal v
becomes "0", and the counter clock u is sent from the D/A counter control circuit 14 to the white level D/A counter 15, whereby the white level D/A counter 15 is counted up. The count output of the white level D/A counter 15 is converted into an analog signal in the white level D/A conversion circuit 17, and then level-shifted by the reference voltage level shifter 4a of the level shifter 4, and the output is converted into an analog signal as the upper limit reference voltage _VH . The signal is sent to the D conversion circuit 3. Then, when the frame switching signal m switches to low level, the frame switching circuit 13 switches the black level detection circuit 1
2 side and the D/A counter control circuit 1
The level counter 4 is cleared and the counting operation of the black level sampling clock p is started. In this case, if there are many black level components in the video signal and the count value exceeds "2000" at the end of the frame, the up/down switching is output from the D/A counter control circuit 14 as shown in FIG. The signal t is held as “1”,
A down command is given to the black level D/A counter 16. Also, at this time, the D/A counter control circuit 14
A counter clock s is outputted from the counter clock s, and the black level D/A counter 16 counts down. Also, if the black level component in the video signal is small and the count value becomes less than "1000" at the end of the frame, the up-down switching signal t becomes "0" and the counter clock s changes to the D/A counter control circuit. 14 to black level D/A counter 1
Sent to 6. As a result, the black level D/A counter 16 is counted up. The count output of the black level D/A counter 16 is converted into an analog signal by the black level D/A conversion circuit 18, and then level-shifted by the lower limit reference voltage level shifter 4b of the level shifter 4, and the lower limit reference voltage _VL is set to A. /D conversion circuit 3.
In this A/D conversion circuit 3, the A/D conversion circuit 3 converts the A/D converter according to the upper limit reference voltage _VH and the lower limit reference voltage _VL .
A conversion process is performed. In this case, if the numbers of white level sampling clock n and black level sampling clock p are within the predetermined setting value range as described above, the upper limit reference voltage V _H and the lower limit reference voltage V _L
does not vary, but if clock n and clock p are numbers outside the set value range, upper limit reference voltage V _H and lower limit reference voltage V _L will vary up and down. Therefore, if the lower limit of the above setting values is A1 and the upper limit is A2, then A1, A2
Increasing the value of A1 and A2 will result in a screen with strong contrast, while decreasing the values of A1 and A2 will result in a screen with less contrast.

[Second Embodiment of the Invention] Next, a second embodiment of the invention will be described with reference to FIG. In the first embodiment, as shown in FIG. 2, a frame switching circuit 13 is provided to switch the white level detection circuit 11 and the black level detection circuit 12, so that the level counter in the D/A counter control circuit 14 can be set to white. This second embodiment is designed to be commonly used for counting the level and black level sampling clocks, but in this second embodiment, as shown in FIG. 14a and a black level counter 14b are provided independently. With this configuration, the white level sampling clock n and the black level sampling clock p can be counted in each frame to simultaneously control the setting of the upper limit reference voltage V _H and the lower limit reference voltage V _L.

In the above embodiment, when the count values of the white level sampling clock and the black level sampling clock in the D/A counter control circuit 14 are greater than or equal to "2000" or less than "1000", the upper limit reference voltage V _H and the lower limit reference voltage are Although the value of V _L is changed, the present invention is not limited to the above embodiment, and it goes without saying that it may be set to other values.

[Effects of the Invention] As described in detail above, according to the present invention, in a television receiver using a panel type display unit, a digital video signal is set according to the number of sampling clocks for each of the white level and black level. Since the video signal is A/D-converted by using the converter, the relationship between the range of change in the level of the video signal and each reference voltage can be set favorably.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the overall circuit configuration in the first embodiment of the present invention, FIG. 2 is a block diagram showing main parts of the control circuit in FIG. 1, and FIG. 3 is a D/A circuit diagram in FIG. 2. A circuit configuration diagram showing details of the counter control circuit, FIG. 4 is a timing chart for explaining the operation of the first embodiment, and FIG. 5 is a main part of the D/A counter control circuit in the second embodiment of the present invention. FIG. 1...Video amplification circuit, 2...Synchronization separation circuit, 3
...A/D conversion circuit, 4...Level shifter, 5...
...Control circuit, 6, 8...Shift register, 7...
First drive circuit, 9... Second drive circuit, 10... Liquid crystal display panel, 11... White level detection circuit, 12
...Black level detection circuit, 13...Frame switching circuit, 14...D/A counter control circuit, 15...
White level D/A counter, 16... Black level D/
A counter, 17...white level D/A conversion circuit,
18...Black level D/A conversion circuit, 21...Level counter, 22...Decoder, 23...Shift register, 26, 27...Flip-flop.

Claims (1)

[Claims] 1. In an A/D conversion circuit that A/D converts a video signal according to an upper limit reference voltage and a lower limit reference voltage,
means for sampling the white level and black level of an A/D converted video signal and outputting a sampling clock according to the white level amount and black level amount; and the white level sampling clock and black level outputted by this means. It comprises means for counting level sampling clocks at predetermined intervals, and means for A/D converting the video signal according to the number of white level sampling clocks and the number of black level sampling clocks counted by this means. A video signal A/D conversion circuit characterized by: