JP2006295608A - Video signal processing apparatus and display device provided therewith - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce the manufacturing cost of a video signal processing apparatus and power consumption thereof. <P>SOLUTION: This video signal processing apparatus with a timing controller samples a signal of each horizontal scanning line included in an effective display period having substantial video information in an original video signal synchronously with a horizontal synchronization signal at a predetermined frequency and outputs the sampled signal, and outputs the above signal in the effective display period in a timing thinned per predetermined horizontal synchronization signal as a gate clock indicating a timing of a new line in a display device. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a video signal processing apparatus that generates a video signal to be displayed on a display having discrete pixels. The present invention also relates to a display device including the video signal processing device.

  Currently, video signals such as NTSC or PAL as video signals for TV or the like, or high-definition signals such as 480i, 480p, and 1080i are employed. When displaying an image on a liquid crystal display, plasma display, or the like having discrete pixels based on such a video signal, the video signal is converted from analog to digital and the image size in the vertical direction is matched. Therefore, it is necessary to perform an I / P conversion process for changing from an interlace system to a progressive system and a resolution conversion process in accordance with the resolution of the display (Patent Documents 1 to 3).

  The conventional video signal processing apparatus 100 includes an analog / digital converter (A / D converter) 10, a decoder 12, an image quality correction circuit 14, a conversion processing circuit 16, and a timing generator 18, as shown in FIG. Is done. The timing generator 18 receives a system clock from the outside, generates a clock signal used in each part of the video signal processing apparatus 100, and outputs it to each part. Thereby, each part of the video signal processing apparatus 100 can be synchronized.

  The A / D converter 10 receives an analog video signal to be processed from outside the apparatus, and converts the analog signal into a digital signal at a predetermined sampling frequency. The digitized video signal is output to the decoder 12. The decoder 12 performs various processes on the video signal. For example, Y / C separation processing for separating a video signal into a luminance (Y) signal and a color difference (C) signal is performed. The image quality correction circuit 14 performs various processes for correcting the image quality on the signal processed by the decoder 12. For example, color conversion processing for converting a color difference signal into an RGB signal or Γ correction is performed on the color signal. The conversion processing circuit 16 performs I / P conversion processing and resolution conversion processing on the video signal whose image quality has been corrected. The video signal subjected to the conversion process is output to the external display device 102.

  The display device 102 receives the synchronization signal from the timing generator 18 and displays the video signal processed in synchronization with the synchronization signal by the built-in timing controller.

JP 2004-274124 A JP 2004-247990 A JP 2004235811 A

  In general, the video signal processing apparatus 100 is often mounted on a television receiver or a display device as a dedicated video signal processing chip. However, the configuration of the conventional video signal processing apparatus 100 needs to include a conversion processing circuit 16 for performing I / P conversion processing and resolution conversion processing. Since these conversion processes are complicated, the circuit scale of the video signal processing apparatus 100 becomes large, and an increase in chip size and an increase in manufacturing cost become a problem.

  Further, by providing the I / P conversion processing circuit and the resolution conversion processing circuit, there is a problem that the power consumption in the video signal processing apparatus 100 increases and the power consumption of the entire display apparatus also increases.

  In view of the above-described problems of the prior art, the present invention provides a video signal processing device capable of displaying on a display device having a desired resolution and a reduced circuit scale, and a display device including the video signal processing device. For the purpose.

  The present invention receives an original video signal in which a signal of one horizontal scanning line is divided by a horizontal synchronizing signal, and a signal of a plurality of horizontal scanning lines is divided by a vertical synchronizing signal to form an image of one field or one frame. And a video signal processing device that converts the video signal into a processed video signal corresponding to the display device and outputs the processed video signal, and has an effective display period having substantial video information in the original video signal that is equal to or greater than the period of the horizontal synchronization signal. The display device outputs a gate clock pulse indicating the timing of line feed in the display device at a cycle, and the display device has a cycle shorter than the cycle of the horizontal synchronization signal in an ineffective display period having no substantial video information in the original video signal. And a timing controller that outputs a gate clock pulse indicating the timing of the line feed in. In the invalid display period, a 0 level (black level) signal is output as a video signal. Thereby, when the display format of the video signal is converted, the effective display period, the ineffective display period, and the line feed can be kept synchronized.

  Here, it is preferable that the timing controller outputs a gate clock pulse indicating a line feed timing in the display device at a timing at which the horizontal synchronization signal is thinned out at predetermined intervals in the effective display period.

  Further, the timing controller includes a frame detection circuit for detecting whether the original video signal is an ODD field or an EVEN field, and the horizontal synchronization signal in each of an odd field and an even field. It is preferable to vary the timing of thinning out.

  For example, when a 1080i high-definition video signal is converted into a signal that can be displayed on a VGA display device as an original video signal, the timing controller removes any one of the three consecutive horizontal synchronization signals. The gate clock pulse is output at the timing.

  According to another aspect of the present invention, there is provided a display apparatus comprising the video signal processing apparatus according to the present invention, wherein a horizontal line synchronization process is performed in accordance with the gate clock pulse.

  According to the present invention, it is possible to provide a video signal processing device and a display device that can display a video on a display device having a desired resolution and have a smaller circuit scale than conventional ones. Thereby, manufacturing cost and power consumption can be reduced.

  In this embodiment, a video signal processing device that converts a 1080i high-definition video signal so that it can be displayed in a letterbox format on a VGA display device will be described. However, the applicable range of the present invention is not limited to this.

  As shown in FIG. 1, a video signal processing apparatus 200 according to an embodiment of the present invention includes an analog / digital converter (A / D conversion circuit) 20, a decoder 22, an image quality correction circuit 24, a timing controller 26, and a timing generator 28. It is comprised including. The output from the video signal processing device 200 is input to the external display device 300. In FIG. 1, the video signal processing device 200 and the display device 300 are shown as separate devices, but the video signal processing device 200 may be mounted on the display device 300 to be a single device.

  As illustrated in FIG. 2, the display device 300 includes a source driver 30, a gate driver 32, and a display pixel matrix 34. The source driver 30 includes a shift register 30a, a latch circuit 30a ', a latch circuit 30b, and a digital / analog conversion circuit 30c. The gate driver 32 includes a shift register 32a and an output gate circuit 32b.

  As shown in FIG. 2, the shift register 30 a included in the source driver 30 includes a series of latch circuits (D-flip flops) corresponding to the number of effective display pixels (640 pixels) of one horizontal line of the display device 300. It is configured including a circuit. The shift register 30a shifts the source start pulse and uses it for the latch pulse of the latch circuit 30a '. The latch circuit 30a 'is used to enable the selected latch by shifting the source start pulse, and buffer the sequentially digitized video signal by one horizontal line.

  Each stage of the latch circuit 30a 'can be configured such that D-flip flops corresponding to the number of bits representing a digitized video signal are arranged in parallel. For example, when a video signal for one pixel is expressed by 8 bits, each stage of the latch circuit included in the latch circuit 30a ′ is configured by a circuit in which eight D-flip flops are provided in parallel. A D-flip flop is used to store and save the data value of each bit of the video signal. Data of each bit of the video signal output from the video signal processing device 200 is input to an input (D) terminal of each D-flip flop of each latch circuit. The output (Q) terminal of the D-flip flop of each bit of each stage is connected to the input (D) terminal of the D-flip flop of the corresponding bit of the latch circuit 30b of the next stage. The source clock SCLK is commonly input to clock (C) terminals of all D-flip flops included in the shift register 30a. Thus, each time the source clock SCLK rises, the digitized video signal is held while being sequentially shifted rightward in the latch circuit of the latch circuit 30a '. In FIG. 2, the latch circuit is illustrated as one flip-flop element in order to simplify the drawing.

  The latch circuit 30b includes a number of latch circuits corresponding to the number of effective display pixels (640 pixels) of one horizontal line of the display device 300. The latch circuit 30b is used to further buffer the video signal for one horizontal line buffered in the shift register 30a.

  Each stage of the latch circuit 30b can be configured by arranging in parallel D-flip flops corresponding to the number of bits representing a digitized video signal, as in the shift register 30a. For example, when a video signal for one pixel is expressed by 8 bits, eight D-flip flops are arranged in parallel in each stage of the latch circuit included in the latch circuit 30b, and each D-flip flop is It is used to store and save the data value of each bit of the video signal. The output (Q) terminal of the D-flip flop corresponding to each bit of each stage of the latch circuit 30a ′ is a D-flip flop corresponding to each bit of the latch circuit 30b corresponding to each stage of the latch circuit 30a ′. To the input (D) terminal. In FIG. 2, the latch circuit is illustrated as one flip-flop element in order to simplify the drawing.

  The digital / analog conversion circuit (D / A conversion circuit) 30 c includes a number of D / A converters corresponding to the number of horizontal pixels of the display device 300. Each D / A converter converts the digital video signal output from the latch circuit at each stage of the latch circuit 30 b into analog, and outputs the analog signal to the display pixel matrix 34. For example, when each stage of the latch circuit of the latch circuit 30b is configured by eight D-flip flops, a signal output from each stage is converted into an analog signal as an 8-bit digital signal and output.

  The shift register 32 a included in the gate driver 32 includes a series circuit of latch circuits whose number corresponds to the number of vertical pixels of the display device 300. The shift register 32a is used to sequentially shift and output the gate signal for each horizontal line.

  The gate start pulse VSP output from the video signal processing device 200 is input to the input (D) terminal of the latch circuit (D-flip flop) in the first stage. The output (Q) terminal of the D-flip flop of each bit of each stage is connected to the input (D) terminal of the D-flip flop of the corresponding bit of the latch circuit of the next stage to form a series circuit of latch circuits. Is done. The gate clock VCLK is commonly input to the clock (C) terminals of all the D-flip flops included in the shift register 32a. Thus, every time the gate clock VCLK rises, the gate signal is output while being sequentially shifted from the first stage to the final D-flip flop.

  The output gate circuit 32b controls transmission of the gate signal from the shift register 32a to the display pixel matrix 34. The output gate circuit 32b includes a number of transfer gates corresponding to the number of vertical pixels of the display device 300 connected to the output (Q) terminal of each latch circuit of the shift register 32a. Each transfer gate receives the out enable signal OE (bar) output from the video signal processing apparatus 200, and is output from the output (Q) terminal of each latch circuit when the out enable signal OE (bar) is at a low level. Is transmitted to the gates of the control transistors in the corresponding row of the display pixel matrix 34. When the out enable signal OE (bar) is at a high level, the connection between the shift register 32a and the display pixel matrix 34 is disconnected.

  That is, every time the shift register 32a receives the gate start pulse VSP, the output of any one of the latch circuits is set to the high level in the vertical scanning direction every time the gate clock VCLK is received, and the out enable signal OE (bar) is at the low level. Sometimes, the output of the shift register 32a is transmitted to the display pixel matrix 34 by the output gate circuit 32b. As a result, any row of the display pixel matrix 34 is activated.

  The display pixel matrix 34 includes a plurality of display pixels arranged in a matrix. For example, the VGA type display device 300 includes an active matrix of display pixels of vertical 480 pixels × horizontal 640 pixels without including an ineffective display area. Each display pixel includes a control transistor. The output terminals of the transfer gates of the output gate circuit 32b corresponding to the row are commonly connected to the gates of the transistors of the rows. In addition, the output terminals of the D / A converters of the D / A conversion circuit 30c corresponding to the column are commonly connected to the drains of the transistors in each column. When each row is selected in turn by the shift register 32a, only the control transistor in the selected row is turned on, and the row has the intensity according to the output from the D / A conversion circuit 30c corresponding to each display element in the row. Each display element emits light. Thereby, an image can be displayed for each horizontal line.

  When a color image is a processing target, a set of the source driver 30, the gate driver 32, and the display pixel matrix 34 is provided for each reference color such as red (R), green (G), and blue (B). By providing it, a color image can be displayed.

  Hereinafter, processing in the video signal processing apparatus 200 and the display apparatus 300 will be described with reference to the timing chart of FIG. 4 (FIG. 9). FIG. 4 shows a timing chart for one field of the ODD field. FIG. 9 shows a timing chart for one field of the EVEN field. That is, a timing chart from the rise of the vertical synchronization signal VS included in the analog video signal to the rise of the next vertical synchronization signal VS is shown. One frame includes a blank display period that is a period from the rise of the vertical synchronization signal VS to the start of the effective display period, an effective display period that is a period for actually displaying the video signal on the screen of the display device 300, and an effective display period. It is divided into a blank display period which is a period from the end to the rising edge of the next vertical synchronizing signal VS.

  The A / D conversion circuit 20 receives an analog video signal from the outside, samples the video signal at a predetermined sampling frequency fs in synchronization with the sampling clock DCLK input from the timing generator 28, and converts it into a digital signal. The sampling clock DCLK is generated in the timing generator 28 based on the vertical synchronizing signal VS and horizontal synchronizing signal HS of the input video signal and the system clock CLK which is the basic clock of the system. The digitized video signal is transmitted to the decoder 22.

  As shown in FIG. 3A, the 1080i high-definition video signal is an interlaced signal having 1125 horizontal scanning lines when the number of invalid scanning lines is included and 1080 horizontal scanning lines when the number of effective scanning lines is included. That is, an image of one field (1/2 frame) is expressed by the number of effective scanning lines 1080/2 = 540 lines (1125/2 = 562.5 lines including the number of invalid scanning lines). In addition, the aspect ratio of the video in the high-definition broadcasting is vertical: horizontal = 9: 16. Therefore, the video signal of one horizontal line in the effective display area is represented by 1920 pixels (2200 pixels including the invalid scanning line area).

  In the case of the present embodiment, as shown in FIG. 3B, the display device 300 is a VGA system having an effective display area of 640 pixels in width (non-effective display area 733 pixels). The sampling frequency is set so that a video signal whose line is 1920 pixels is expressed by 640 pixels.

  For example, assuming that the pixel clock frequency is 74.25 MHz with respect to 1920 pixels of the original video signal, the timing generator 28 synchronizes the video signal of one horizontal line with the horizontal synchronization signal HS of the video signal at 24.74 MHz. Are sampled with a sampling clock DCLK having a sampling frequency of. As a result, the number of pixels is converted from 1080i 1920 pixels (2200 pixels in the ineffective display area) to 640 pixels (733 pixels in the ineffective display area) in the horizontal direction. At this time, it is also preferable to perform resolution conversion by appropriately performing interpolation processing between pixels.

  The decoder 22 performs various processes on the video signal digitized by the A / D conversion circuit 20. For example, Y / C separation processing for separating a video signal into a luminance (Y) signal and a color difference (C) signal is performed. Since these processes can apply conventional techniques, a detailed description thereof will be omitted.

  The image quality correction circuit 24 performs various processes for correcting the image quality on the signal processed by the decoder 22. Examples of image quality correction processing include color conversion processing for converting color difference signals into RGB signals, Γ correction processing for color signals, contour correction processing, white balance adjustment processing, and the like. Since conventional techniques can be applied to these processes, detailed description is omitted.

  The timing generator 28 receives a video signal (here, a 1080i high-definition video signal) from the outside of the apparatus, and separates and extracts the horizontal synchronization signal HS and the vertical synchronization signal VS from the video signal. A conventional signal separation technique using a comparator or the like can be used for separation and extraction of the horizontal synchronization signal HS and the vertical synchronization signal VS. Further, it receives a system clock CLK from the outside and generates a signal used in each part of the video signal processing device 200 such as a sampling clock DCLK. Thereby, each part of the video signal processing apparatus 200 can be controlled in synchronization as appropriate.

  In the present embodiment, the sampling clock DCLK is generated so as to sample the video signal of one horizontal line at the sampling frequency of 24.74 MHz by counting the system clock CLK in synchronization with the horizontal synchronizing signal HS. Specifically, counting of the system clock CLK is started from the timing when the horizontal synchronization signal HS is input, and a pulse of the sampling clock DCLK is output every time the counter value becomes a multiple of a value corresponding to 40.4 ns. The generated sampling clock DCLK is sent to the A / D conversion circuit 20. In addition, the vertical synchronization signal VS and the horizontal synchronization signal HS are also transmitted to the timing controller 26.

  The timing controller 26 receives the horizontal synchronization signal HS and the vertical synchronization signal VS from the timing generator 28, generates various control signals for performing display processing in the display device 300, and outputs them to the external display device 300. A video signal digitized in synchronization with the clock signal is output to the external display device 300.

  When receiving the vertical synchronization signal VS, the timing controller 26 starts counting the number of rises of the horizontal synchronization signal HS. As shown in FIG. 4 (FIG. 9), the data enable signal DE is maintained at a low level during the ineffective display period (blank period) from the rise of the vertical synchronization signal VS to the rise of the horizontal synchronization signal HS 11 times. The video signal output from the timing controller 26 is valid when the data enable signal is at a high level, and the video signal output from the timing controller 26 is disabled when the data enable signal is at a low level. In the effective display period from the 12th rising edge of the horizontal synchronizing signal HS to the 540th rising edge, a pulse having a shorter pulse width than the horizontal scanning period of one horizontal line is synchronized with the rising edge of the horizontal synchronizing signal HS. Launch as DE. While the data enable signal DE rises, a video signal for one horizontal line is transferred to the display device 300. Then, the data enable signal DE is maintained at the low level again during the ineffective display period (blank period) from the 541th rise of the horizontal synchronization signal HS to the next rise of the vertical synchronization signal VS.

  As shown in FIG. 5, the timing controller 26 includes a field detection circuit 60 for detecting the first field (ODD field) and the second field (EVEN field) of the interlace signal. The field detection circuit 60 includes a counter 62, a decoder 64, an edge detection circuit 66, an AND element 68, and a latch element 70.

  The counter 62 receives the horizontal synchronization signal HS and the system clock CLK from the timing generator 28. The counter 62 is reset at the rising timing of the horizontal synchronization signal HS and counts the number of pulses of the system clock CLK input thereafter. The counter 62 outputs the counter value Hf of the system clock CLK to the decoder 64.

  The decoder 64 receives the counter value Hf from the counter 62 and outputs a 1/2 horizontal line detection signal HALF_H based on the register values of the attached registers HALF_H_UP and HALF_H_DOWN (not shown). Note that the initial output of the decoder 64 is at a low level.

  The value of the register HALF_H_UP is preset to a counter value corresponding to 1/4 of the cycle of the horizontal synchronization signal HS, and the value of the register HALF_H_DOWN is preset to a counter value corresponding to 3/4 of the cycle of the horizontal synchronization signal HS. deep. At the timing when the counter value Hf coincides with the value of the register HALF_H_UP, the 1/2 horizontal line detection signal HALF_H is output as a high level. Next, the 1/2 horizontal line detection signal HALF_H is returned to the low level at the timing when the counter value Hf coincides with the value of the register HALF_H_DOWN. As a result, as shown in FIG. 6, a pulse having a width of ¼ period around the half of the period of the horizontal synchronization signal HS is generated as a ½ horizontal line detection signal HALF_H.

  The edge detection circuit 66 receives the vertical synchronization signal VS from the timing generator 28, detects an edge of the vertical synchronization signal VS, and outputs a pulse having a pulse width of one clock width of the system clock CLK as the edge signal VEDGE. Specifically, as shown in FIG. 7, the edge detection circuit 66 can be composed of a flip-flop 66a and an AND element 66b. The vertical synchronizing signal VS is input to the input (D) terminal of the flip-flop 66a, and the system clock CLK is input to the clock (C) terminal. As shown in the timing chart of FIG. 6, when the system clock CLK rises at the timing when the vertical synchronization signal VS rises, the output (Q) terminal of the flip-flop 66a is maintained at a high level. The AND element 66b receives the output from the output (Q) terminal of the flip-flop 66a and the vertical synchronization signal VS, and outputs a high level signal at a timing when both signals are at the high level. Thus, the rising edge of the vertical synchronization signal VS can be detected and the edge signal VEDGE can be generated.

  The AND element 68 of the field detection circuit 60 receives the 1/2 horizontal line detection signal HALF_H and the edge signal VEDGE, and outputs a logical product of these signals. The output of the AND element 68 is held by the latch element 70.

  In the 1080i high-definition video signal, as shown in FIG. 6, the edge position of the vertical synchronizing signal VS and the edge position of the horizontal synchronizing signal HS are horizontal in the first field (ODD field) and the second field (EVEN field). It is shifted by a half cycle of the synchronization signal HS. Therefore, the low level and the high level are alternately switched in the first field (ODD field) and the second field (EVEN field), and are output as the field detection signals ODD / EVEN.

  Further, as shown in FIG. 8, the timing controller 26 includes a first control signal generation circuit 26a, a second control signal generation circuit 26b, and a vertical DE start / end detection circuit 50. The first control signal generation circuit 26a includes an H counter 40a, an H decoder 42a, a V counter 44a, a V decoder 46a, and a logic circuit 48. The second control signal generation circuit 26b includes an H counter 40b, an H decoder 42b, a V counter 44b, and a V decoder 46b. The field detection signal ODD / EVEN output from the field detection circuit 60 is input to the logic circuit 48 included in the first control signal generation circuit 26a.

  The first control signal generation circuit 26a and the second control signal generation circuit 26b are used exclusively switched by the vertical DE start / end detection circuit 50. In the vertical effective display period, the first control signal generation circuit 26 a is used, and an output signal from the first control signal generation circuit 26 a is output to the display device 300. In the vertical non-effective display period, the second control signal generation circuit 26 b is used, and an output signal from the second control signal generation circuit 26 b is output to the display device 300. Hereinafter, the first control signal generation circuit 26a will be described first, and then the second control signal generation circuit 26b will be described.

  The H counter 40a receives a data enable signal DE and a sampling clock DCLK. The H counter 40a is reset at the rising edge of the data enable signal DE or at the timing when the counter value set by the register R0 is reached, and then counts the number of pulses of the sampling clock DCLK inputted thereafter. The H counter 40a outputs the counter value Ha to the H decoder 42b. Further, the H counter 40a has a counter value Ha that reaches a value corresponding to the total number of pixels of one horizontal line of the display device 300, 733 in this embodiment, or a counter value set by the register R0. The pulse is output as the carry signal Ca at the determined timing. Carry signal Ca is output to V counter 44a.

  The H decoder 42a receives the counter value Ha from the H counter 40a, and generates and outputs a source start pulse HSP and a source latch signal STRB based on the register values R1, R1 ′, R2, and R2 ′ of the attached registers. . As shown in FIG. 2, these control signals are input to the source driver 30 of the display device 300 during the effective display period. Hereinafter, these signals will be described in detail.

  By setting the register value R1 to 0, the H decoder 42a has a timing when the counter value Ha becomes 0, that is, a timing corresponding to the rising edge of the data enable signal DE, as shown in FIG. 4 (FIG. 9). A high level pulse is output as a source start pulse HSP. The falling edge is set by the register value R1 '. The source start pulse HSP is input to a shift register 30 a included in the source driver 30.

  The source clock pulse SCLK is the same as the sampling clock DCLK, and is commonly input to clock (C) terminals of all the latch circuits (D-flip flops) included in the shift register 30a. Further, the timing controller 26 digitizes the source start pulse HSP to the input (D) terminal of the latch circuit at the first stage of the shift register 30a and the pixel for one pixel to the latch circuit 30a ′ in synchronization with the source clock pulse SCLK. Output video signal. That is, each time the H counter 40a receives the sampling clock DCLK, the timing controller 26 outputs the source start pulse HSP and the video signal for one pixel. As a result, the video signal corresponding to 640 pixels of effective display for one horizontal line is stored and held while being sequentially shifted to the latch circuit of the latch circuit 30a '.

  The H decoder 42a outputs a pulse of the source latch signal STRB at the timing when the counter value Ha coincides with the register value R2. For example, by setting the register value R2 to 734, as shown in FIG. 4 (FIG. 9), a high level pulse is output as the source latch signal STRB when the counter value Ha becomes 734. . The falling edge is set by the register value R2 '.

  As shown in FIG. 2, a source latch signal STRB is commonly input to clock (C) terminals of all latch elements included in the latch circuit 30b. By setting the register value R2 to be larger than the number of effective pixels for horizontal display, after the video signal for one horizontal line is held in the shift register 30a, the source latch signal STRB is held in the shift register 30a in response to the rising edge. The video signals for one horizontal line are transferred all at once to the latch circuit 30b.

  The H decoder 42a outputs a pulse of a logic control signal at a timing when the counter value Ha coincides with the register values R3, R4, R5, and R6. These are the gate start pulse VSP, the gate clock VCLK, the signal that is the source of the output permission OE (bar), and the signal that indicates the change point of the polarity signal POL. By setting the register values R3, R4, R5, and R6 to a value larger than the register value R2, for example, 735, a pulse that goes high after the source latch signal STRB is output is output as a logic control signal. The The falling edge is set by register values R3 ', R4', R5 ', R6'. The logic control signal is output to the logic circuit 48.

  Next, the V counter 44a and the V decoder 46a will be described in detail. The V counter 44a performs processing by receiving a data enable signal DE from the outside and a carry signal Ca from the H counter 40a.

  The V counter 44a detects the start timing of the vertical effective display period in the video signal of one field, and resets the counter value Va. For example, the timing at which the data enable signal DE rises again after the data enable signal DE has been maintained at the low level for longer than a predetermined time can be detected as the start timing of the vertical effective display period. After resetting the counter value Va, the V counter 44a increments the counter value Va by 1 each time the carry signal Ca is received, and outputs the number of times the carry signal Ca is received after the reset to the V decoder 46a as the counter value Va. The counter value Va indicates the number of horizontal lines in one vertical period.

  The V decoder 46a receives the counter value Va and outputs a signal indicating a line for outputting the gate start pulse VSP by the register R7 and a signal TOG for line-toggling the pulse signal whenever the counter value Va increases. A signal indicating a line for outputting the gate start pulse VSP and a signal TOG for line-toggling are input to the logic circuit 48.

  The logic circuit 48 receives a field detection signal ODD / EVEN, a signal indicating a line for outputting a gate start pulse VSP, a signal TOG for line toggle, and a logic control signal from the H decoder 42a, and receives a gate start pulse VSP and a gate clock VCLK. The output permission OE (bar) and the polarity signal POL are generated and output to the gate driver 32 of the display device 300.

  When the field detection signal ODD / EVEN is at a high level, that is, when the first field (ODD field) is being processed, the logic circuit 48, among the pulses of the logic control signal received from the H decoder 42a, as shown in FIG. Except the 3n-1th pulse (n is an integer equal to or greater than 1), it is output as the gate clock VCLK. That is, the first, third, fourth, sixth, seventh,..., 3n-2nd, 3nth,... 540th pulses are output as the gate clock VCLK. Further, in synchronization with the gate clock VCLK, a polarity signal POL that inverts the line between the output permission OE (bar), which is at a low level in the period included in the output period of the gate clock VCLK, is generated and output.

  In this way, by excluding the 3n-1th pulse and outputting it as the gate clock VCLK, as shown in FIG. 10A, the 3n-1 of the effective display area of the original video signal in the 1080i system. The video signal in the row is omitted, and the video compressed to 2/3 in the vertical scanning direction is displayed. That is, 540 effective horizontal lines in a high-definition video signal of one frame are displayed after being compressed to 360 lines. Since one horizontal line is compressed from an effective display pixel number of 1920 pixels to an effective display pixel number of 640 pixels, an image in which an aspect ratio of 9:16 of the high-definition method is maintained is displayed on the display device 300 of the VGA method. .

  On the other hand, when the field detection signal ODD / EVEN is at a low level, that is, when the second field (EVEN field) is being processed, as shown in FIG. 9, the third mth pulse of the logic control signal received from the H decoder 42a. The pulse is output as the gate clock VCLK except for the pulse (m is an integer of 1 or more). That is, the first, second, fourth, fifth, seventh,..., 3m-1th, 3m + 1,... 539th pulses are output as the gate clock VCLK. Further, in synchronization with the gate clock VCLK, an output permission OE (bar) that is at a low level in a period included in the output period of the gate clock VCLK and a polarity signal POL that inverts the line during the synchronization are generated and output.

  In this way, by removing the third m-th pulse and outputting it as the gate clock VCLK, as shown in FIG. 10B, the video in the third m-th row in the effective display area of the original video signal in the 1080i system. The signal is omitted and an image compressed to 2/3 in the vertical scanning direction is displayed. Also in this case, 540 effective horizontal lines in a high-definition video signal of one frame are displayed after being compressed to 360 lines, and an image with a high-definition aspect ratio of 9:16 is displayed on the VGA display device 300. The

  In the present embodiment, the gate clock VCLK is output at the timing when the data enable signal corresponding to the horizontal synchronization signal in the effective display period is thinned out at a predetermined cycle without performing complicated I / P conversion processing and resolution conversion processing. That is, the horizontal scanning lines are thinned out at a predetermined cycle so that the display device 300 displays the image. Therefore, the processing circuit can be simplified and downsized as compared with the conventional circuit.

  Also, as shown in FIGS. 10A and 10B, different lines are omitted and displayed in the ODD field and the EVEN field. As a result, the video displayed on the display device 300 can be averaged and displayed temporally in the vertical display direction, and the image quality of the video can be improved. At this time, an interpolation process assuming vertical line thinning may be performed in advance.

  Next, processing in the ineffective display period by the second control signal generation circuit 26b will be described. In the ineffective display period, a process of displaying a belt-like black level image on the upper and lower portions of the screen of the display device 300 is performed.

  The vertical DE start / end detection circuit 50 receives the data enable signal DE, and switches from the first control signal generation circuit 26a to the second control signal generation circuit 26b at the end of the vertical effective display period. In addition, switching from the second control signal generation circuit 26b to the first control signal generation circuit 26a is performed at the start timing of the vertical effective display period. The start timing of the vertical effective display period can be detected as a timing at which the data enable signal DE becomes high after maintaining the low level for a predetermined time. Further, the end timing of the vertical effective display period can be detected as a timing when the data enable signal DE is changed to the low level after maintaining the high level for a predetermined time.

  The H counter 40b receives a data enable end signal (DE end signal) indicating the end of the data enable signal DE from the vertical DE start / end detection circuit 50 and the sampling clock DCLK. The H counter 40b is reset by the DE end signal, counts the number of pulses of the sampling clock DCLK inputted thereafter, and outputs it as a counter value Hb. Further, the H counter 40b is reset when the counter value Hb becomes a value corresponding to the register R8, counts the number of pulses of the sampling clock DCLK inputted thereafter, and outputs it as the counter value Hb. If the register R8 is set to 1/3 of the total number of horizontal pixels in the vertical effective display period, one horizontal frequency is also 1/3.

  The H counter 40b outputs the counter value Hb to the H decoder 42b. Further, a pulse is output as the carry signal Cb at the timing when the counter value Hb coincides with the register R8. Carry signal Cb is output to V counter 44b.

  The H decoder 42b receives the counter value Hb, generates and outputs a source start pulse HSP and a source latch signal STRB based on the register values R9 and R10 of the attached registers. These control signals are input to the display device 300 during the vertical non-effective display period. Hereinafter, these signals will be described in detail.

  By setting the register value R9 to 0, the H decoder 42b outputs a pulse that becomes a low level at the timing when the counter value Hb becomes 0, as shown in FIG. 4 (FIG. 9), as a source start pulse HSP. To do. The falling edge is set by the register R9 '. The H decoder 42b may generate and output the source start pulse HSP only once immediately after the start of the ineffective display period in which the data enable signal DE becomes low level during the ineffective display period. The source start pulse HSP is output to a shift register 30a included in the source driver 30.

  At the timing when the source start pulse HSP pulse is output from the H decoder 42b, the video signal of 0 level (black level) is output from the timing controller 26. Accordingly, in the shift register 30a, the 0 level (black level) is propagated to all the latch circuits (D-flip flops) by the pulse of the source start pulse HSP from the H decoder 42b.

  Further, the H decoder 42b outputs a pulse that becomes a high level at the timing when the counter value Hb becomes the register value R10, as the source latch signal STRB. By setting the register value R10 to a value larger than the register value R9, for example, 1, the H decoder 42b outputs the source latch signal STRB pulse after the source start pulse HSP pulse is output. The falling edge is set by the register R10 '. The H decoder 42b may output the pulse of the source latch signal STRB only once in the invalid display period.

  As shown in FIG. 2, the source latch signal STRB is commonly input to the clock (C) terminals of all the latch circuits included in the latch circuit 30b. As a result, the latch circuit 30b is also set to 0 level (black level) in response to the output of the shift register 30a set to 0 level (black level). The output of the latch circuit 30b is maintained at 0 level (black level) in the non-effective display period.

  The H decoder 42b outputs a logic control signal pulse at a timing when the counter value Hb coincides with the register values R11, R12, R13, and R14. These are the gate start pulse VSP, the gate clock VCLK, the signal that is the source of the output permission OE (bar), and the signal that indicates the change point of the polarity signal POL. By setting the register values R11, R12, R13, and R14 to a value larger than the register value R10, for example, 2, a pulse that becomes a high level after the source latch signal STRB is output is output as a logic control signal. The The falling edge is set by register values R11 ', R12', R13 ', R14'. The logic control signal is output to the logic circuit 49.

  Next, the V counter 44b and the V decoder 46b will be described in detail. The V counter 44b performs processing upon receiving a data enable signal DE from the outside and a carry signal Cb from the H counter 40b.

  The V counter 44b resets the counter value Vb according to the DE end signal from the vertical DE start / end detection circuit 50. After resetting the counter value Vb, the V counter 44b increases the counter value Vb by 1 every time it receives the carry signal Cb, and outputs the number of times the carry signal Cb is received to the V decoder 46b as the counter value Vb. The counter value Vb indicates the number of horizontal lines output in the vertical ineffective display period of one vertical period.

  The V decoder 46b receives the counter value Vb and outputs a signal indicating a line for outputting the gate start pulse VSP by the register R15 and a signal TOG for line-toggling the pulse signal every time the counter value Vb increases. A signal indicating a line for outputting the gate start pulse VSP and the signal TOG are input to the logic circuit 49.

  The logic circuit 49 receives the gate start pulse VSP, the gate clock VCLK, and the output permission OE (bar) in response to the signal indicating the line for outputting the gate start pulse VSP, the signal TOG for line toggle, and the logic control signal from the H decoder 42b. The polarity signal POL is generated and output to the gate driver 32 of the display apparatus 300.

  The V decoder 46b generates and outputs the gate clock VCLK and the output permission OE (bar) every time the counter value Vb increases based on the register value R16 of the attached register. By setting the register value R16 to the number of horizontal lines in the vertical non-effective display period, here 120, as shown in FIG. 4 (FIG. 9), the counter value Vb remains constant until the counter value Vb reaches the register value R16. Every time the counter value Vb is increased in the period, the gate clock VCLK is output accordingly. Further, in synchronization with the gate clock VCLK, an output permission OE (bar) and a polarity signal POL that are at a low level in a period included in the output period of the gate clock VCLK are generated and output.

  As a result of the above processing, as shown in FIG. 11, after the effective display period, a horizontal line of 0 level (black level) of the number of rows set in the register value R16 is displayed. Thereby, the vertical scanning of one frame is completed. Thereafter, the effective display period starts.

  Here, the output period of the gate clock VCLK in the vertical ineffective display period is made shorter than the output period of the gate clock VCLK in the vertical effective display period. For example, when the gate clock VCLK in the vertical ineffective display period has a frequency three times that of the gate clock VCLK in the vertical ineffective display period, the output period of the gate clock VCLK in the vertical ineffective display period is three times the frequency in the effective display period. Thus, the gate clock VCLK and the output permission OE (bar) are output.

  That is, in the vertical non-effective display period, a horizontal line of 0 level (black level) is displayed while being sequentially scanned in the vertical scanning direction at a higher vertical scanning frequency than in the vertical effective display period. By scanning the vertical non-effective display period at a high frequency, it can be converted into a display device format and displayed in synchronization with sequentially received video signals. Note that it is not always necessary to execute both the vertical effective display period processing by the first control signal generation circuit 26a and the vertical ineffective display period processing by the second control signal generation circuit 26b. You may only run.

  In this embodiment, an example in which a 1080i high-definition video signal is converted into a signal that can be displayed on a VGA display device is shown, but the scope of application of the present invention is not limited to this. The ratio between the number of horizontal line pixels (horizontal scanning frequency) in the conversion source video signal and the number of horizontal line pixels (horizontal scanning frequency) in the conversion destination signal, and the number of vertical scanning lines and conversion in the conversion source video signal By appropriately changing each register value of the timing controller 26 according to the ratio of the previous signal to the number of vertical scanning lines, a change source start pulse HSP, source latch signal STRB, gate start pulse VSP, gate clock VCLK, output The output timing of the permission OE (bar) and the polarity signal POL can be changed. As a result, it is possible to perform mutual conversion between a video signal and a display device of a system different from that of the present embodiment.

  As described above, according to the present embodiment, it is possible to provide a video signal processing device that can display video on a display device having a desired resolution and does not require I / P conversion processing or resolution conversion processing. it can.

It is a block diagram which shows the structure of the video signal processing apparatus in embodiment of this invention. It is a figure which shows the structure of a display apparatus. It is a figure which shows the image structure of the high vision video signal of 1080i system, and the video signal of VGA system. It is a figure which shows the timing chart of the process of the video signal processing apparatus in embodiment of this invention. It is a figure which shows the structure of the flame | frame detection circuit in embodiment of this invention. It is a figure which shows the timing chart of the process of the frame detection circuit in embodiment of this invention. It is a figure which shows the structure of the edge detection circuit in embodiment of this invention. It is a figure which shows the structure of the 1st control signal generation circuit in the embodiment of this invention, a 2nd control signal generation circuit, and the vertical DE start end detection circuit. It is a figure which shows the timing chart of the process of the video signal processing apparatus in embodiment of this invention. It is a figure for demonstrating the horizontal line displayed in the effective display period in embodiment of this invention. It is a figure for demonstrating the horizontal line displayed in the ineffective display period in embodiment of this invention. It is a block diagram which shows the structure of the video signal processing apparatus in background art.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10 Analog / digital converter, 12 decoder, 14 Image quality correction circuit, 16 Conversion processing circuit, 18 Timing generator, 20 Analog / digital conversion circuit, 22 Decoder, 24 Image quality correction circuit, 26 Timing controller, 26a, 26b Control signal generation circuit 28 timing generator, 30 source driver, 30a shift register, 30a ′ latch circuit, 30b latch circuit, 30c analog conversion circuit, 32 gate driver, 32a shift register, 32b output gate circuit, 34 display pixel matrix, 40a, 40b H counter 42a, 42b H decoder, 44a, 44b V counter, 46a, 46b decoder, 48, 49 logic circuit, 50 vertical DE start / end detection circuit, 60 field detection circuit, 2 counter, 64 a decoder, 66 an edge detection circuit, 66a flip-flop, 66b and the element 68 and element 70 the latching element, 100 a video signal processing apparatus, 102 display unit, 200 video signal processing apparatus, 300 a display device.

Claims (5)

Receives and displays an original video signal in which a signal of one horizontal scanning line is divided by a horizontal synchronizing signal and a signal of a plurality of horizontal scanning lines is divided by a vertical synchronizing signal to form an image of one field or one frame. A video signal processing device that converts and outputs a processed video signal corresponding to the device,
In an effective display period having substantial video information in the original video signal, a gate clock pulse indicating a line feed timing in the display device is output at a period equal to or higher than the period of the horizontal synchronization signal,
A timing controller that outputs a gate clock pulse indicating a line feed timing in the display device in a period shorter than a period of the horizontal synchronization signal in an ineffective display period having no substantial video information in the original video signal; A characteristic video signal processing apparatus. The video signal processing device according to claim 1,
The video signal processing device, wherein the timing controller outputs a gate clock pulse indicating a line feed timing in the display device at a timing obtained by thinning out the horizontal synchronization signal at predetermined intervals in the effective display period. The video signal processing apparatus according to claim 2, wherein
The timing controller includes a frame detection circuit that detects whether the original video signal is an ODD field or an EVEN field,
A video signal processing apparatus characterized in that the timing of thinning out the horizontal synchronizing signal is different for each of an odd field and an even field. In the video signal processing device according to claim 2 or 3,
The video signal processing apparatus, wherein the timing controller outputs the gate clock pulse at a timing when any one of the three consecutive horizontal synchronization signals is removed. A video signal processing apparatus according to any one of claims 1 to 4,
A display device, wherein horizontal line synchronization processing is performed in accordance with the gate clock pulse.

Images