JPH1124624A - Matrix display device and driving method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize an elongating function of a vertical scanning line with a low cost by displaying the same lines doubly at prescribed intervals, contriving a timing control of a shift resistor of a gate driver. SOLUTION: Gate pulse clock signals GPCK are outputted to a gate driver 3 with a specific timing by selection signals, which are generated repeatedly by a counter 67 inside a controller 6 and a reset circuit 68 and inputted into a selector terminal S of a selector circuit 63. A vertical scanning line can be elongated as much as 4/3 times by controlling the gate driver 3 with a timing of the gate pulse clock signals GPCK by which the same lines are displayed doubly at prescribed intervals. In order to elongate the vertical scanning line as much as 4/3 times, one gate pulse clock signal GPCK must be increased additionally per three gate pulse clock signals GPCK.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a matrix display device such as a liquid crystal television and a plasma display, and more particularly to a matrix display device having a wide aspect ratio of 16: 9 and a driving method of the matrix display device.

[0002]

2. Description of the Related Art Since the start of black-and-white television broadcasting, display devices such as televisions have been constantly evolving due to the rapid progress of science and technology. At present, the color television broadcasting system widely used in Japan and the United States is NTSC (National Telev.
ision System Committee), but this NTSC
The system was designed on the assumption that black and white television receivers already on the market could be viewed in black and white.

[0003] In recent years, television receivers have been improved in image quality and the screen size has been increased.
TV), MAC (Multiplexed Analogue Component), H
Development of a new high-definition television system replacing the NTSC system such as DTV (High Definition Television) is underway.

[0004] Among these new systems, the EDTV system aims to improve the image quality while maintaining compatibility with the current system based on the NTSC system in Japan. By maintaining the backward compatibility that is emphasized even when the color is changed from black and white, consumers can also receive a new broadcast without replacing the television receiver with a new one.

In the first generation EDTV (EDTV-I) system, the aspect ratio is kept at 4: 3, and it is intended to increase the resolution in producing a video signal. However, as discussed and adopted in HDTV, widening of the television screen is an essential element for reproducing a more powerful image than ever and for giving a sense of realism. Therefore, the second-generation EDTV (EDTV-II) realizes a wide aspect ratio and further higher image quality.

By the way, as described above, the aspect ratio is 4:
3 can also display EDTV-II video, but if all screens are displayed without cutting off the left and right sides of the screen, a portion without video signals at the top and bottom of the screen ( (Usually the black part). Specifically, of the approximately 480 effective horizontal scanning lines, a total of 120 horizontal scanning periods at the top and bottom are vertical non-image portions (periods where there is no signal), and from the interlaced scanning relationship, the vertical main image portion ( Signal period) is half of 360 lines, 18
It becomes zero.

In order to eliminate the vertical non-image area and display the entire screen, the 180 effective horizontal scanning lines are increased to 240
Although it is necessary to make a book, conventionally, the calculation is performed by a decoder inside the television receiver.

[0008]

However, a decoder for increasing the number of horizontal scanning lines performs a complicated operation for image processing, so that it becomes a complicated and large-scale circuit. It was difficult to realize this. These problems also apply to a television receiver or the like using a liquid crystal display panel, a plasma display panel, or the like.

An object of the present invention is to display two identical lines at regular intervals by devising timing control of a shift register of a gate driver without using a complicated decoder as described above. Accordingly, it is an object of the present invention to provide a matrix display device and a matrix display device driving method that realize a vertical scanning line extension function at low cost.

[0010]

According to the first aspect of the present invention,
Arranging a plurality of signal lines and a plurality of scanning lines in a matrix,
A matrix display panel having a display element at each intersection of these signal lines and scanning lines; a sampling signal for setting a timing for sampling a video signal based on a basic clock signal; and a scanning timing signal for setting a scanning timing. A timing setting unit for generating, a scanning unit for sequentially scanning the plurality of scanning lines at a scanning timing according to a scanning timing signal generated by the timing setting unit, and a sampling signal generated by the timing setting unit. A signal line driving unit that samples a video signal, generates a signal line driving signal that drives the plurality of signal lines, and drives each of the display elements.In a matrix display device, the timing setting unit includes: The scanning timing set by the scanning timing signal is Counting means for counting, each time the count value of the scanning timing reaches a predetermined value, generates a scanning timing signal for setting the scanning timing so as to scan by increasing the number of scanning lines by an arbitrary number, and the scanning means The scanning is performed by increasing an arbitrary number of the scanning lines at predetermined scanning timings in accordance with a scanning timing signal generated by the timing setting means.

According to the first aspect of the present invention, a plurality of signal lines and a plurality of scanning lines are arranged in a matrix, and a display element is provided at each intersection of the signal lines and the scanning lines. Matrix display panel; timing setting means for generating a sampling signal for setting a timing for sampling a video signal based on a basic clock signal; and a scanning timing signal for setting a scanning timing; and scanning generated by the timing setting means. Scanning means for sequentially scanning the plurality of scanning lines at a scanning timing according to a timing signal; and a signal for sampling a video signal based on a sampling signal generated by the timing setting means to drive the plurality of signal lines. Signal line driving means for generating a line driving signal to drive each of the display elements. In the matrix display device, said timing setting means includes counting means for counting the scanning timing set by the scanning timing signal,
Each time the count value of the scan timing reaches a predetermined value, a scan timing signal for setting the scan timing is generated so that the scan line is increased by an arbitrary number and the scan is performed. Scanning is performed by increasing the number of the scanning lines by an arbitrary number at predetermined scanning timings according to the scanning timing signal.

According to a second aspect of the present invention, in the matrix display device according to the first aspect, the timing setting means controls the signal line driving means after the count value of the scanning timing by the counting means reaches a predetermined value. Each time a non-signal line driving period in which the signal line is not driven is generated, a scanning timing signal for setting the scanning timing so as to simultaneously scan a plurality of the scanning lines is generated, and the scanning unit is configured by the timing setting unit. A plurality of the scanning lines are simultaneously scanned in each non-signal line driving period according to the generated scanning timing signal.

According to the matrix display device of the present invention, the timing setting means sets the signal line by the signal line driving means after the count value of the scanning timing by the counting means reaches a predetermined value. Every time a non-signal line driving period in which the scanning is not performed is generated, a scanning timing signal for setting the scanning timing so as to simultaneously scan a plurality of the scanning lines is generated, and the scanning unit generates a scanning timing generated by the timing setting unit. A plurality of the scanning lines are simultaneously scanned in each non-signal line driving period according to a timing signal.

According to a third aspect of the present invention, in the matrix display device according to the first aspect, the timing setting means is provided during the signal line driving period after the count value of the scanning timing by the counting means becomes a predetermined value. For each predetermined timing, generating a scanning timing signal for setting the scanning timing to sequentially scan a plurality of the scanning lines,
The scanning unit sequentially scans the plurality of scanning lines at predetermined timings during the signal line driving period according to a scanning timing signal generated by the timing setting unit.

According to the third aspect of the present invention, the timing setting means may include a predetermined timing during a signal line driving period after the count value of the scanning timing by the counting means becomes a predetermined value. Generating a scanning timing signal for setting the scanning timing so as to sequentially scan a plurality of the scanning lines, wherein the scanning unit generates the scanning line according to the scanning timing signal generated by the timing setting unit. A plurality of the scanning lines are sequentially scanned at each predetermined timing during the driving period.

Therefore, the number of scanning timing signals can be increased arbitrarily and the number of scanning lines can be easily increased. Therefore, a decoder which is a complicated and large-scale circuit for performing a complicated operation for image processing is required. The function of extending the vertical scanning lines can be realized by a small-sized and low-cost matrix display device without the need.

According to a fourth aspect of the present invention, in the matrix display device according to any one of the first to third aspects, the video signal is a signal for displaying a video having a predetermined aspect ratio, and the aspect ratio is the matrix signal. Different from the aspect ratio of the display panel, the timing setting means sets the aspect ratio of the video signal to the aspect ratio of the matrix display panel every time the count value of the scanning timing by the counting means becomes a predetermined value. Generating a scan timing signal for setting a scan timing so as to scan by increasing the number of scan lines by a predetermined number, and wherein the scan means responds to the scan timing signal set by the timing set means, The scan lines are increased by a predetermined number so that the aspect ratio becomes the aspect ratio of the matrix display panel. It is characterized by scanning.

According to a fourth aspect of the present invention, in the matrix display device of the first aspect, the video signal is a signal for displaying a video having a predetermined aspect ratio. This aspect ratio is different from the aspect ratio of the matrix display panel, and the timing setting means changes the aspect ratio of the video signal every time the count value of the scanning timing by the counting means becomes a predetermined value. A scanning timing signal for setting a scanning timing so as to scan by increasing the number of the scanning lines by a predetermined number so as to have an aspect ratio of, and the scanning means responds to the scanning timing signal set by the timing setting means. So that the aspect ratio of the video signal becomes the aspect ratio of the matrix display panel. The serial scanning line is increased by a predetermined number scans.

Therefore, even when the aspect ratio of the video signal is different from that of the display panel, the number of scanning lines of the video signal can be increased by a predetermined number. It can be realized with a low-cost matrix display device.

According to a fifth aspect of the present invention, in the matrix display device of the fourth aspect, the aspect ratio of the video signal is 16: 9, and the aspect ratio of the matrix display panel is 4: 3. And

According to a fifth aspect of the present invention, in the matrix display device according to the fourth aspect, the aspect ratio of the video signal is 16: 9.
The aspect ratio of the matrix display panel is 4: 3, which is different, and the timing setting means changes the aspect ratio of the video signal every time the count value of the scanning timing by the counting means reaches a predetermined value. A scan timing signal for setting a scan timing so as to scan by increasing the scan lines by a predetermined number so as to be 4: 3 is generated, and the scanning means responds to the scan timing signal set by the timing setting means. The scanning is performed by increasing the number of the scanning lines by a predetermined number so that the aspect ratio of the video signal is 4: 3.

Therefore, the video signal is a video signal for a so-called wide screen, and the display panel has an aspect ratio of 4: 4.
3, the number of scanning lines of the video signal can be increased by a predetermined number.
The vertical scanning line of the video signal for the wide screen with the aspect ratio of 16: 9 is extended 4/3 times, and the optimal video display for the display panel with the aspect ratio of 4: 3 is realized by a small-sized and low-cost matrix display device. Can be realized.

According to a sixth aspect of the present invention, a plurality of signal lines and a plurality of scanning lines are arranged in a matrix, and a matrix display panel having a display element at each intersection of the signal lines and the scanning lines is driven. At this time, a sampling signal for setting a timing for sampling a video signal and a scanning timing signal for setting a scanning timing are generated based on a basic clock signal, and the plurality of scanning lines are generated at a scanning timing according to the scanning timing signal. In the matrix display device driving method of sequentially scanning and generating a signal line drive signal for driving the plurality of signal lines by sampling a video signal based on the sampling signal and driving each of the display elements. The scan timing set by the timing signal is counted, and the count value of the scan timing becomes a predetermined value. Generating a scan timing signal for setting the scan timing so that the scan line is increased by an arbitrary number, and scans the scan line by increasing the scan line by an arbitrary number at predetermined scan timings according to the scan timing signal. It is characterized by:

According to a sixth aspect of the invention, a plurality of signal lines and a plurality of scanning lines are arranged in a matrix, and a display element is provided at each intersection of the signal lines and the scanning lines. When driving a matrix display panel having the following, a sampling signal for setting a timing for sampling a video signal and a scanning timing signal for setting a scanning timing are generated based on a basic clock signal, and a scanning timing signal is set according to the scanning timing signal. A matrix for sequentially scanning the plurality of scanning lines at a scanning timing, sampling a video signal based on the sampling signal, generating a signal line driving signal for driving the plurality of signal lines, and driving each of the display elements; In the display device driving method,
A scan timing signal for counting the scan timing set by the scan timing signal, and setting a scan timing signal for setting the scan timing so that the scan line is increased by an arbitrary number every time the count value of the scan timing becomes a predetermined value. The scan lines are generated and the number of the scan lines is increased by an arbitrary number at predetermined scan timings according to the scan timing signal, and scanning is performed.

According to a seventh aspect of the present invention, in the method of driving the matrix display device according to the sixth aspect, the non-signal line driving period in which the signal line is not driven after the count value of the scanning timing becomes a predetermined value. Generating a scanning timing signal for setting the scanning timing so as to simultaneously scan the plurality of scanning lines, and scanning the plurality of scanning lines simultaneously for each of the non-signal line driving periods in accordance with the scanning timing signal. It is characterized by doing.

According to a seventh aspect of the invention, in the driving method of the sixth aspect, the signal line is not driven after the count value of the scanning timing reaches a predetermined value. Each time a non-signal line driving period is set, a scanning timing signal for setting the scanning timing so as to simultaneously scan a plurality of the scanning lines is generated, and in accordance with the scanning timing signal, a scanning timing signal is generated for each of the non-signal line driving periods. A plurality of the scanning lines are simultaneously scanned.

According to an eighth aspect of the present invention, in the method of driving a matrix display device according to the sixth aspect, a plurality of the plurality of scanning signals are provided at predetermined timings during a signal line driving period after the count value of the scanning timing becomes a predetermined value. Generating a scanning timing signal that sets the scanning timing so as to sequentially scan the scanning lines, and according to the scanning timing signal, for each predetermined timing during the signal line driving period, a plurality of the scanning lines are generated. It is characterized by sequential scanning.

According to an eighth aspect of the invention, in the method of driving the matrix display device according to the sixth aspect, during the signal line driving period after the count value of the scanning timing becomes a predetermined value. Generating a scanning timing signal for setting the scanning timing so as to sequentially scan the plurality of scanning lines at predetermined timings, and according to the scanning timing signal, for each predetermined timing during the signal line driving period. Then, the plurality of scanning lines are sequentially scanned.

Therefore, by adopting the liquid crystal driving method of the present invention for a matrix display device, a complicated large-scale decoder for performing a complicated operation for image processing is not required. When the function of extending the vertical scanning line is added to the apparatus, it can be realized at a small size and at low cost.

[0030]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an embodiment of a liquid crystal display device according to the present invention will be described in detail with reference to FIGS.

(First Embodiment) As described above, even a conventional television receiver having an aspect ratio of 4: 3 has an EDTV-II.
Can be displayed, but if the left and right sides of the screen are all displayed without being cut off, a portion (usually a black portion) without a video signal will be formed at the top and bottom of the screen. Specifically, of the approximately 480 effective horizontal scanning lines, a total of 120 horizontal scanning periods at the top and bottom are vertical non-image portions (periods where there is no signal), and from the interlaced scanning relationship, the vertical main image portion ( The period during which a signal is present) is 180, which is half of 360 lines.

In order to eliminate the vertical non-image area and display the entire screen, the 180 effective horizontal scanning lines are increased to 240
However, in the liquid crystal display device 1 according to the first embodiment, one scanning line is added for every three scanning lines, and the vertical scanning line is extended 4/3 times. The liquid crystal display device 1 capable of increasing the number of video signals from 180 to 240 will be described in detail with reference to FIGS.

First, the configuration will be described.

FIG. 1 is a schematic circuit configuration diagram of the liquid crystal display device 1. 1, the liquid crystal display device 1 includes a liquid crystal panel 2, a gate driver 3, a source driver 4, a chroma interface 5, a controller 6, and the like.

In FIG. 1, an active matrix type liquid crystal panel 2 is employed. Although not shown, a plurality of scanning lines (gate lines) Xn and signal lines (source lines) Ym are arranged in a matrix on a substrate. And at each intersection of these scanning lines Xn and signal lines Ym
Channel MOS type TFT (Thin Film Transistor)
A large number of pixels are formed by forming a liquid crystal capacitor by connecting a switching element (hereinafter, referred to as a TFT element) including a pixel element and a pixel electrode to a signal line side of the TFT element.

Each TFT element (not shown) has its gate electrode connected to a corresponding scanning line (gate line) Xn, and its source electrode connected to a corresponding signal line (source line) Ym. ing. In each TFT element, a liquid crystal capacitor is connected to its drain electrode, and the other electrode constituting the liquid crystal capacitor has
A common line (not shown) to which a common voltage (common voltage) is supplied is connected.

In the liquid crystal panel 2, a drain voltage (signal line driving voltage) corresponding to image data is stored in a liquid crystal capacitance of each pixel formed in each TFT element sequentially selected by the gate driver 3 and the source driver 4. The image is displayed by being applied and holding the charge.

As shown in FIG. 2, the gate driver 3 includes a shift register, a gate circuit, and the like, and generates a gate voltage (scanning drive voltage) based on a vertical drive control signal input from the controller 6. Then, it is applied to a predetermined scanning line Xn in the liquid crystal panel 2 and is selectively driven.

In FIG. 2 showing a circuit configuration example of the gate driver 3, the gate driver 3 includes an inverting comparator circuit 31, an inverting gate circuit 32, a flip-flop 3
3, n-bit shift register 34, AND gate circuit 3
5 and an output buffer circuit 36.

The inverting comparator circuit 31 uses the gate voltage input to the non-inverting input terminal (+) as a reference voltage.
Gate start signal GSR input to the inverting input terminal
When the input voltage of T, the gate pulse clock signal GPCK, and the gate output reset signal GRES exceeds the reference voltage, an inverted signal is output.

The inverting gate circuit 32 further inverts the signal input from the inverting comparator circuit 31 and outputs a signal having the same phase as the signal input to the inverting comparator circuit 31.

The flip-flop 33 has a clock terminal C
The gate start signal GSRT input to the terminal I is latched based on the scan shift clock inversion signal CKB input to K and the scan shift clock signal CK input to the clock terminal CKB. Output to the bit shift register 34.

The n-bit shift register 34 starts generating a gate electrode drive signal based on the scan start timing of the scan start signal ST input from the flip-flop 33, and outputs the scan shift clock signal CK input from the inversion gate circuit 32. Based on the shift clock timing, the internal shift timing of the generated gate electrode drive signal is controlled and sequentially output to the AND gate circuit 35.

The AND gate circuit 35 is a circuit for calculating the logical sum of the gate electrode drive signal input from the n-bit shift register 34 and the gate output reset signal RES input from the inverting gate circuit 32 and outputting the result. Therefore, the AND gate circuit 35 outputs the gate electrode drive signal to the output buffer circuit 36 when the gate output reset signal RES is a High signal, and outputs the gate electrode drive signal when the gate output reset signal RES is a Low signal. Stop signal output.

The output buffer circuit 36 shapes the waveform of the gate electrode drive signal input from the AND gate circuit 35 and outputs it to the gate electrodes X1 to Xn in the liquid crystal panel 2 to drive the gate electrodes X1 to Xn. .

The source driver 4 sequentially drives a predetermined number of signal electrodes in the liquid crystal panel 2 according to the control timing of the control signal input from the controller 6, and sequentially selects the image data inverted and input from the chroma interface 5. The image signal is transferred to the signal electrode and stored in a liquid crystal display element connected to each TFT in accordance with the image signal to display an image.

The chroma interface 5 separates the composite synchronizing signal CSYNC from the input video signal and outputs it to the controller 6, and at the same time separates the input video signal into R, G and B signals and inverts them. Then, at the timing based on the horizontal synchronization signal input from the controller 6 as image data for video display, the source driver 4
Output to

The controller 6 generates a horizontal synchronizing signal based on the composite synchronizing signal CSYNC input from the chroma interface 5 and
And a gate pulse clock signal G for driving and controlling the gate driver 3 and the source driver 4 based on the composite synchronization signal CSYNC.
Various control signals such as a PCK, a gate output reset signal GRES, and a gate start signal GSRT are generated and output to the gate driver 3 and the source driver 4.

FIG. 3 shows an example of a circuit configuration of a part related to generation of the gate pulse clock signal GPCK, the gate output reset signal GRES, and the gate start signal GSRT in the internal circuit of the controller 6. In FIG.
The controller 6 includes a falling synchronous counter 61, a horizontal decoder 62, a selector circuit 63, a JK flip-flop 64, flip-flops 65 and 66, a counter circuit 67, a reset circuit 68, a JK flip-flop 69,
AND gate 70, flip-flops 71 and 72, OR
It comprises gates 73 and 74, an asynchronous counter 75, a vertical decoder 76, and flip-flops 77 and 78. The gate pulse clock signal GPCK, the gate output reset signal GRES, and the gate start signal G among the internal circuits constituting the controller 6 will be described below.
Each circuit of a part related to the generation of the SRT will be described.

The falling synchronous counter 61 is provided with a clock inversion signal CKB inputted to the clock terminal Clock.
The horizontal decoder 62 is controlled by performing a count operation and outputting the count value to the horizontal decoder 62.

The horizontal decoder 62 outputs various control signals according to the count value input from the falling synchronous counter 61. That is, the horizontal decoder 62
Are GPCK generation signals gpck1s, gpck1r, g for generating a gate pulse clock signal GPCK.
GRES generation signals gres and gres for outputting pck2s and gpck2r to the selector circuit 63 and generating a gate output reset signal GRES.
r is output to the JK flip-flop 64, and GSRT generation signals gsrts and gsrtr for generating the gate start signal GSRT are output to the JK flip-flop 69. Further, the horizontal decoder 62
The pulse signal P100H is supplied to the reset terminal Res of the falling synchronous counter 61 through the flip-flop 65.
, the counter circuit 67, and the OR gate 73, and outputs the pulse signal P25H to the flip-flop 66.
To the reset circuit 68 and the OR gate 74 to output the pulse signal P75H to the flip-flop 7.
1 to the OR gate 74, and outputs the pulse signal P50H to the reset circuit 68, the OR gate 73, and the flip-flop 78 via the flip-flop 72. Here, the pulse signal P100H is a pulse output in synchronization with the timing of the horizontal synchronizing signal, and the pulse signal P25H is 1H (1 horizontal period: about 63.5 μsec) of the pulse signal P100H.
This pulse is output with a delay by the equally divided time (about 15.9 μsec) (see FIG. 5). Pulse signal P50H
Is a pulse that is output about 15.9 μsec later than the pulse signal P25H, and the pulse signal P75H is
This pulse is output with a delay of about 15.9 μsec further from the pulse signal P50H (see FIG. 5).

The selector circuit 63 includes a JK flip-flop 631, a JK flip-flop 632, and a selector 633. The GPCK generation signals gpck1s and gpck1 input from the horizontal decoder 62 are provided.
The gate pulse clock signal GPCK generated based on r, gpck2s, and gpck2r is output to the gate driver 3. The operation of the selector circuit 63 for generating the gate pulse clock signal GPCK is performed by each circuit described below.

The JK flip-flop 631 generates the GPCK generation signal gpck1s input to the terminal J from the horizontal decoder 62 and the GPCK generation signal input to the terminal K under the timing of the inverted clock signal CKB input to the clock terminal CK. Based on the signal gpck1r, GPCK
A generation signal gpck1 (see FIG. 5) is generated and output from the terminal X to the input terminal A of the selector 633.

The JK flip-flop 632 outputs the GPCK generation signal gpck2s input from the horizontal decoder 62 to the terminal J and the GPCK generation signal input to the terminal K under the timing of the inverted clock signal CKB input to the clock terminal CK. Based on the signal gpck2r, GPCK
A generation signal gpck2 (see FIG. 5) is generated and output from the terminal X to the input terminal B of the selector 633.

The selector 633 operates as shown in FIG.
It comprises a D gate 633a, an AND gate 633b, an inversion gate 633c, and an OR gate 633d. When the select signal input from the counter circuit 67 to the select terminal S is a Low signal, the selector 633 inverts the Low signal by an inverting gate 633c, and uses the inverted signal as one input of the AND gate 633a as a High signal. By using the Low signal as the select signal as one input of the AND gate 633b, the GPCK generation signal gpck input to the input terminal A is input.
1 is output from the output terminal X to the gate driver 3 via the OR gate 633d as the gate pulse clock signal GPCK. Further, when the select signal input to the select terminal S from the counter circuit 67 is a High signal, the selector 633 inverts the High signal by an inverting gate 633c and uses the inverted signal as one input of the AND gate 633a as a Low signal. Also, the High signal as the select signal is supplied to an AND gate 633.
b, the GPCK generation signal gpck2 input to the input terminal B is output to the OR gate 633.
The gate pulse clock signal GPCK is output from the output terminal X to the gate driver 3 via d.

The above is a description of each circuit responsible for the gate pulse clock signal GPCK generation operation of the selector circuit 63.

The JK flip-flop 64 receives the G signal input from the horizontal decoder 62 to the terminal J under the timing of the inverted clock signal CKB input to the clock terminal CK.
RES generation signal gres and G input to terminal K
A gate output reset signal GRES (see FIG. 5) is generated based on the RES generation signal gresr, and is output from the terminal X to the gate driver 3.

The flip-flop 65 is connected to the horizontal decoder 6
Latch the pulse signal P100H input from
Clock inverted signal CKB input to clock terminal CK
Is output to the counter circuit 67 at the same timing. The flip-flop 66 latches the pulse signal P25H input from the horizontal decoder 62 and outputs it to the reset circuit 68 in accordance with the timing of the inverted clock signal CKB input to the clock terminal CK.

The counter circuit 67 includes a NOR latch 67
1, a 2-bit binary counter constituted by a NOR latch 672 and an AND gate 673, and a pulse signal P100H input from the flip-flop 65
Is counted, and when the count value becomes “3”, Hig
The h signal is output to the selector circuit 63 and the reset circuit 68. The counting operation of the pulse signal P100H of the counter circuit 67 is performed by each circuit described below.

When the first pulse signal P100H is input from the flip-flop 65, the NOR latch 671 sets the output of the output terminal X to a High signal at the falling edge of the first pulse signal P100H. When the second pulse signal P100H is input, the output terminal X is output at the falling edge of the second pulse signal P100H.
Is a Low signal. This NOR latch 671
Is output from the High signal to L
At the falling edge that becomes the ow signal, the NOR latch 67
2 sets the output of the output terminal X to a High signal. Furthermore,
When the third pulse signal P100H is input from the flip-flop 65 to the NOR latch 671, the NOR latch 671 changes the output of the output terminal X to a High signal again. When the third pulse signal P100H is received,
The signals output from the output terminals X of the NOR latch 671 and the NOR latch 672 are both High signals, and both input terminals of the AND gate 673 receive the High signal. Therefore,
The signal output from the AND gate 673 is such that the pulse signal P100H input from the flip-flop 65 is
When it is counted, it becomes a High signal.

The above is the description of the pulse signal P of the counter circuit 67.
It is an explanation of each circuit responsible for the 100H count operation.

The reset circuit 68 includes a flip-flop 6
81, an inverting gate 682, a flip-flop 683, and an AND gate 684, a High signal input from the counter circuit 67, a pulse signal P25H input from the horizontal decoder 62 via the flip-flop 66, and a flip-flop. A reset signal (High signal) is output to the reset terminal R of the counter circuit 67 based on the pulse signal P50H input from the horizontal decoder 62 via 72. The reset operation of the counter circuit 67 by the reset circuit 68 is based on each circuit described below.

The pulse signal P10 from the counter circuit 67
When the count value of 0H is not "3", A
The signal input from the ND gate 673 to the reset circuit 68 is a Low signal, and the flip-flop 681
The Low signal is internally latched and output to one input terminal of the AND gate 684 at the timing of the pulse signal P25H input to the clock terminal CK. The inversion gate 682 inverts the Low signal, The signal is output to the flip-flop 683 as a High signal, and the flip-flop 683 latches the High signal internally and outputs a pulse signal P50H input to the clock terminal CK.
At the timing of (1) and outputs to the other input terminal of AND gate 684.

The pulse signal P10 from the counter circuit 67
The count value of 0H becomes “3” and the AND gate 67
3 to the reset circuit 68 is High
When a signal is output, the flip-flop 681 operates
The signal is latched internally, and the inverting gate 682
The h signal is inverted and output to the flip-flop 683 as a Low signal, and the flip-flop 683 internally latches the Low signal. At this time, a signal input from the flip-flop 683 to one terminal of the AND gate 684 is a High signal, and a signal input from the flip-flop 681 to the other terminal of the AND gate 684 is a Low signal. So, AN
D gate 684 to reset terminal R of counter circuit 67
Is a Low signal.

When the pulse signal P25H is input from the flip-flop 66 to the clock terminal CK of the flip-flop 681 about 15.9 μsec after the High signal input from the counter circuit 67, the pulse signal P25H rises. On the falling edge, the flip-flop 681 outputs the internally latched High signal from the output terminal X to one input terminal of the AND gate 684. At this time, the AND gate 684 receives the High signal input from the flip-flop 683 and the High signal input from the flip-flop 681.
Upon receiving the signal, a High signal is output to the reset terminal R of the counter circuit 67 as a reset signal, and the count value of the counter circuit 67 is reset.

Further, about 15.9 μm of the pulse signal P25H
After sec, the clock terminal C of the flip-flop 683
When the pulse signal P50H is inputted to K, the flip-flop 68 is output at the falling edge of the pulse signal P50H.
Reference numeral 3 outputs the internally latched Low signal from the output terminal X to one input terminal of the AND gate 684. Upon receiving the Low signal, the AND gate 684 outputs the L signal.
The ow signal is output to the reset terminal R of the counter circuit 67, and the reset of the counter circuit 67 is released.

The above is the description of each circuit of the reset circuit 68 which performs the reset operation of the counter circuit 67.

The JK flip-flop 69 receives the G signal input from the horizontal decoder 62 to the terminal J under the timing of the inverted clock signal CKB input to the clock terminal CK.
SRT generation signal gsrts and G input to terminal K
A GSRT generation signal gsrt (see FIG. 5) is generated based on the SRT generation signal gsrtr, and output from the terminal X to the AND gate 70. AND gate 70 is JK
An AND operation of the GSRT generation signal gsrt input from the flip-flop 69 and the vertical synchronization gate start signal VGSRT input from the flip-flop 78 is performed to generate a gate start signal GSRT, which is output to the gate driver 3.

The flip-flop 71 is connected to the horizontal decoder 6
2 latches the pulse signal P75H input from 2 and outputs it to the OR gate 74 in accordance with the timing of the inverted clock signal CKB input to the clock terminal CK. The flip-flop 72 latches the pulse signal P50H input from the horizontal decoder 62, and adjusts the clock of the reset circuit 68, the OR gate 73, and the flip-flop 78 according to the timing of the inverted clock signal CKB input to the clock terminal CK. Output to terminal CK.

The OR gate 73 is connected to the flip-flop 65
And the pulse signal P50H input through the flip-flop 72.
Is input, an OR operation is performed, and the asynchronous counter 75
Output to The OR gate 74 outputs the pulse signal P25H input via the flip-flop 66 and the pulse signal P7 input via the flip-flop 71.
With 5H as an input, an OR operation is performed, and the result is output to the clock terminal CK of the flip-flop 77.

The asynchronous counter 75 has an OR gate 73
Pulse signal P50 input to the clock terminal through
H and the pulse signal P100H, the count operation is performed, and the count value is output to the vertical decoder 76 to control the vertical decoder 76.

The vertical decoder 76 has an asynchronous counter 7
5 for generating a vertical synchronization gate start signal VGSRT in accordance with the count value inputted from
An RT generation signal vgsrt is output to flip-flop 77.

The flip-flop 77 is connected to the vertical decoder 7
6, the VGSRT generation signal vgsrt is latched inside, and the clock terminal C
The pulse signal P25H and the pulse signal P input to K
The signal is output to the flip-flop 78 according to the timing of 75H. The flip-flop 78 outputs the VGSRT generation signal vgsrt input from the flip-flop 77.
Is internally latched, and the vertical synchronization gate start signal VGSR is input in accordance with the timing of the pulse signal P50H input to the clock terminal CK via the flip-flop 72.
Output to the AND gate 70 as T (see FIG. 5).

The above is a description of the internal circuits constituting the controller 6, the gate pulse clock signal GPCK, the gate output reset signal GRES, and the gate start signal GS.
It is an explanation of each circuit of a part related to the generation of RT. The gate pulse clock signal GPCK is repeatedly generated by the counter circuit 67 and the reset circuit 68 in the controller 6 at the timing shown in the time chart of FIG. Is output to the gate driver 3, and the gate driver 3 is controlled at the timing of the gate pulse clock signal GPCK for displaying two identical lines at a constant interval. It is configured to be able to expand by / 3 times.

The operation of the liquid crystal display device 1 for extending the vertical scanning lines by 4/3 will be described below. First, in order to extend the vertical scanning line by a factor of 4/3, one gate pulse clock signal G is output for every three gate pulse clock signals GPCK.
The operation of the controller 6 for increasing the PCK will be described.

When a video signal is input to the chroma interface 5, a composite synchronizing signal C is obtained from the input video signal.
When the SYNC is separated and output to the controller 6, the input video signal is separated into R, G, and B signals, and the inverted image data for video display is generated by the controller 6. Are output to the source driver 4 at a timing based on the horizontal synchronization signal input from the source driver 4.

When the composite synchronizing signal CSYNC is input to the controller 6, the composite synchronizing signal CSYNC and the falling synchronous counter 61 are supplied to the clock terminal Clock.
The horizontal decoder 62 is controlled by a count value output to the horizontal decoder 62 by performing a count operation with the clock inversion signal CKB input to the horizontal decoder 62.

That is, the horizontal decoder 62 generates a gate pulse clock signal GPCK.
PCK generation signals gpck1s, gpck1r, gpck
2s and gpck2r are output to the selector circuit 63, and GRES generation signals gres and gresr for generating the gate output reset signal GRES are output to the JK flip-flop 64 to generate the gate start signal GSRT. GSRT generation signals gsrts and gsrtr are output to the JK flip-flop 69. The horizontal decoder 62 outputs the pulse signal P100H to the reset terminal Reset of the falling synchronous counter 61, the counter circuit 67, and the OR gate 73 via the flip-flop 65, and outputs the pulse signal P25H to the flip-flop 66. , The reset circuit 68 and the OR gate 7
4, the pulse signal P75H is output to the OR gate 74 via the flip-flop 71, and the pulse signal P50H is output to the reset circuit 68, the OR gate 73, and the flip-flop 78 via the flip-flop 72. Is output to

From the horizontal decoder 62, the selector circuit 63
, Based on the GPCK generation signal gpck1s input to the terminal J of the JK flip-flop 631 and the GPCK generation signal gpck1r input to the terminal K.
A K generation signal gpck1 (see FIG. 5) is generated and the terminal X
To the input terminal A of the selector 633.

From the horizontal decoder 62, the selector circuit 63
, Based on the GPCK generation signal gpck2s input to the terminal J of the JK flip-flop 632 and the GPCK generation signal gpck2r input to the terminal K.
A K generation signal gpck2 (see FIG. 5) is generated and the terminal X
To the input terminal B of the selector 633.

As shown in FIG. 5, the pulse signal P100H
Have the same 1H period as the GPCK generation signals gpck1 and gpck2, and have the GPCK generation signals gpck1 and gpck2.
It is output at a timing slightly earlier than pck2. The pulse signal P100H is supplied from the horizontal decoder 62 via the flip-flop 65 to the counter circuit 67.
Is input to the NOR latch 671 in the internal memory.

When the first pulse signal P100H is input from flip-flop 65, NOR latch 671
Sets the output of the output terminal X to a High signal at the falling edge of the first pulse signal P100H. At this time, since the output of the output terminal X of the NOR latch 672 is a Low signal, the select signal output from the AND gate 673 to the select terminal S of the selector 633 in the selector circuit 63 is a Low signal. . Therefore, the selector 633 is connected to the JK flip-flop 63
A GPCK generation signal gpck1 input from 1 is output to the gate driver 3 as a gate pulse clock signal GPCK. The gate pulse clock signal G
PCK is the first gate pulse clock signal GPCK
It turns out that.

On the other hand, at this time, the Low signal input from the AND gate 673 to the flip-flop 681 in the reset circuit 68 is latched inside the flip-flop 681, and the pulse signal P25H input to the clock terminal CK of the flip-flop 681. Is output to one input terminal of the AND gate 684 at the timing of. On the other hand, the Low signal input to the inversion gate 682 is inverted and output to the flip-flop 683 as a High signal, and the High signal is output to the flip-flop 6.
83, and is output to the other input terminal of the AND gate 684 at the timing of the pulse signal P50H input to the clock terminal CK of the flip-flop 683. Therefore, at this time, the AND gate 68
Since the reset signal input from 4 to the reset terminal R of the counter circuit 67 is a Low signal, the counter circuit 67 is not reset.

When the second pulse signal P100H is input from the flip-flop 65, the NOR latch 6
Reference numeral 71 designates the output of the output terminal X as a Low signal at the falling edge of the second pulse signal P100H. this,
At the falling edge at which the signal output from the output terminal X of the NOR latch 671 changes from a High signal to a Low signal, the NOR latch 672 changes the output of the output terminal X to High.
h signal. At this time, since the output of the output terminal X of the NOR latch 671 is a Low signal, the select signal output from the AND gate 673 to the select terminal S of the selector 633 in the selector circuit 63 is still a Low signal. It is. Therefore, the selector 633
GPC input from the JK flip-flop 631
The K generation signal gpck1 is converted to the gate pulse clock signal G
It is output to the gate driver 3 as PCK.
The gate pulse clock signal GPCK is the second gate pulse clock signal GPCK.

On the other hand, at this time, similar to the operation after the first gate pulse clock signal GPCK is generated,
Since the reset signal input from the AND gate 684 to the reset terminal R of the counter circuit 67 is a low signal, the counter circuit 67 is not reset.

When the third pulse signal P100H is input from the flip-flop 65, the NOR latch 6
Reference numeral 71 designates the output of the output terminal X as a High signal again at the falling edge of the third pulse signal P100H.
When the third pulse signal P100H is received, NO
Output terminal X of R latch 671 and NOR latch 672
Are output as High signals, and both input terminals of the AND gate 673 receive the High signal. At this time, AN
The select signal output from the D gate 673 to the select terminal S of the selector 633 in the selector circuit 63 is a High signal. Therefore, the selector 63
3 outputs the GPCK generation signal gpck2 input from the JK flip-flop 632 to the gate driver 3 as a gate pulse clock signal GPCK. Since the GPCK generation signal gpck2 is a two consecutive pulse signal as shown in FIG. 5, the gate pulse clock signal GPCK is the third and fourth gate pulse clock signal GPCK.

On the other hand, at this time, the High signal input from the AND gate 673 to the flip-flop 681 in the reset circuit 68 is latched inside the flip-flop 681 and the clock terminal CK of the flip-flop 681 is output.
AND at the timing of the pulse signal P25H
The signal is output to one input terminal of the gate 684. Further, at this time, the flip-flop 683 maintains the state after the second generation of the gate pulse clock signal GPCK is generated.
h signal, the AND gate 684 outputs a High signal input from the flip-flop 683,
And Hig input from the flip-flop 681
In response to the h signal, a High signal is output to the reset terminal R of the counter circuit 67 as a reset signal, and the count value of the counter circuit 67 is reset.

On the other hand, Hi input to the inversion gate 682
The gh signal is inverted and output to the flip-flop 683 as a low signal. The low signal is latched inside the flip-flop 683 and the pulse signal P input to the clock terminal CK of the flip-flop 683.
The signal is output to the other input terminal of the AND gate 684 at the timing of 50H. Therefore, at this time, AN
D gate 684 to reset terminal R of counter circuit 67
Is a Low signal, so that
The reset of the counter circuit 67 is released.

That is, the counter circuit 67 changes the pulse signal P100H input from the flip-flop 65 to 3
Counting is performed, and a High signal is input to the select terminal S of the selector 633 in the selector circuit 63 as a select signal, and is output as a gate pulse clock signal GPCK.
A GPCK generation signal gpck2 is output. Thereafter, the counter circuit 67 is reset by the reset circuit 68 at the timing of the pulse signal P25H about 15.9 μsec later, and further resets the pulse signal P5 about 15.9 μsec later.
The reset is released by the reset circuit 68 at the timing of 0H, and the next pulse signal P100H is counted again as the first pulse signal P100H.
The same operation is repeated.

By the operation of the controller 6 repeated as described above, one gate pulse clock signal GPCK is generated for every three gate pulse clock signals GPCK.
And the gate pulse clock signal GPCK is set to 4
/ 3 times.

Next, the operation of the liquid crystal display device 1 in which the vertical scanning line is extended 4/3 times by the gate pulse clock signal GPCK increased 4/3 times by the above-described operation will be described with reference to a time chart shown in FIG. Will be described along the timings of P1 to P15 representing the gate pulse clock signal GPCK.

In FIG. 6, the video signal shown in the top row is
The gate pulse clock signal GPCK shown in the second column, which is a video signal input to the chroma interface 5 in FIG. 1, represents the gate pulse clock signal GPCK generated by the controller 6 and input to the gate driver 3 by the above-described operation. The gate start signal GSRT in the third column indicates the gate start signal GSRT generated by the controller 6 and input to the gate driver 3.

Gate outputs X1, X2, X3,..., X1
2,... (FIG. 6 does not show X12 and thereafter).
Is a buffer circuit 36 of the gate driver 3 shown in FIG.
, Represents an electrode drive signal output to each scanning line (gate line) Xn, and indicates that the scanning line (gate line) is turned ON when a High signal is applied. Also, A shown on the signal line representing each gate output Xn
L, BL, CL, DL, EL, FL, and GL correspond to the codes attached below the waveform representing the uppermost video signal,
This means that the image data corresponding to the video signal at the timing indicated by each code is output from the source driver 4 to the scanning line (gate line). In order to visually explain this, in FIG. 6, the source driver output is expressed in time series below the gate output X12 by using the above-mentioned code such as AL.

Further, below the output of the source driver, a diagram showing the display state of the liquid crystal panel 2 in accordance with the time series of the codes such as AL is shown. That is, which video signal is displayed on each scanning line of the effective display unit of the liquid crystal panel 2 is shown using an image obtained by dividing the liquid crystal panel 2 for each scanning line.

In FIG. 6, first, the gate start signal G
When the SRT is input to the gate driver 3 shown in FIG. 2, the inverting comparator circuit 31 outputs the gate start signal GSRT input to the inverting input terminal to the reference voltage (the gate input to the non-inverting input terminal (+)). Voltage), the inverted signal of the gate start signal GSRT is output to the inverted gate circuit 32, and the inverted gate circuit 32
The signal is further inverted to output a signal having the same phase as the gate start signal GSRT input to the inverting comparator circuit 31 to the flip-flop 33.

When P1 is generated as the gate pulse clock signal GPCK, the inverting comparator circuit 31 outputs the gate pulse clock signal GPC input to the inverting input terminal.
Assuming that K (P1) has exceeded the reference voltage, the inverted gate circuit 32 uses the inverted signal of the gate pulse clock signal GPCK (P1) as the scan shift clock inverted signal CKB,
And outputs the signal to the clock terminal CK of the flip-flop 33, and the inverting gate circuit 32 further inverts the signal to make it a signal having the same phase as the gate pulse clock signal GPCK input to the inverting comparator circuit 31, and performs the scan shift. It outputs to the clock terminal CKB of the flip-flop 33 as the clock signal CK.

The flip-flop 33 has a clock terminal C
The gate start signal GSRT input to the terminal I is latched based on the scan shift clock inversion signal CKB input to K and the scan shift clock signal CK input to the clock terminal CKB. Output to the bit shift register 34, and the flip-flop at the first stage of the n-bit shift register 34 internally latches the scan start signal ST input from the flip-flop 33.

Further, the gate pulse clock signal GPCK
Is generated, the n-bit shift register 34
The first-stage flip-flop outputs the latched scan start signal ST to the AND gate connected to the scan line X1 of the AND gate circuit 35 at the timing of the scan shift clock signal CK input to the clock terminal CK. Is output to the flip-flop of. Further, by the same operation as that when the P1 occurs, the foremost flip-flop of the n-bit shift register 34 latches the scan start signal ST input from the flip-flop 33 internally. Thus, the gate driver 3
Receives the gate start signal GSRT from the gate pulse clock signal GPCK2, the n-bit shift register 34 has two latches n for latching two High signals.
It becomes a bit shift register, and in the subsequent operation, each gate output Xn becomes the gate pulse clock signal GPCK.
Is turned on for a period of receiving two times.

In the period in which P3 and P4 are generated as the gate pulse clock signal GPCK, the gate outputs X1, X2 and X3 corresponding to the gate pulse clock signal GPCK are outside the effective display range of the liquid crystal panel 2. Therefore, there is no output of image data from the source driver 4, and the scanning lines X1 to X3 are non-image portions.

When P5 is generated as the gate pulse clock signal GPCK, the gate output X4 is turned on by the High signal that has shifted the n-bit shift register 34.
And the pulse signal P10 immediately before the occurrence of P5
0H is counted by the counter circuit 67 as the first pulse signal P100H.

The next pulse signal P100H is counted as the second pulse signal P100H by the counter circuit 67, and subsequently, the gate pulse clock signal GPC
When P6 is generated as K, the gate output X5 is turned ON while the gate output X4 is kept ON, and at the same time, the source driver 4 outputs image data AL corresponding to the video signal AL. As shown,
Scanning line Line1 (scanning line X
4) and the second scanning line Line2 (scanning line X5)
Then, an image corresponding to the video signal AL is simultaneously displayed.

The next pulse signal P100H is counted as the third pulse signal P100H by the counter circuit 67, and subsequently, the gate pulse clock signal GPC
When P7 due to the GPCK generation signal gpck2 is generated as K, the gate output X4 is turned off, and the gate output X6 is turned on while the gate output X5 is kept on.

Subsequently, when P8 is generated by the GPCK generation signal gpck2, the gate output X5 is turned off,
While the gate output X6 is kept ON, the gate output X7 is turned ON. At the same time, the image data BL corresponding to the video signal BL is output from the source driver 4, and the scanning line Line3 (scanning) of the third row of the effective display unit is output. Lines X6) and 4
The video signal B is applied to the scanning line Line4 (scanning line X7) of the row.
The image corresponding to L is displayed. However, the video signal BL displayed on the fourth scanning line Line4 (scanning line X7)
Is overwritten by an image corresponding to the video signal CL output at the next timing, as will be described later, and is not shown as a practically effective display image.

The next pulse signal P100H is counted as the first pulse signal P100H by the counter circuit 67 which has been reset by the reset circuit 68 and has a count value of "0", and subsequently the gate pulse clock signal GPCK. , The gate output X6 is turned off, the gate output X8 is turned on while the gate output X7 is kept on, and at the same time, the image data CL corresponding to the video signal CL is output from the source driver 4, As shown in the panel display state, the scanning line Line4 (scanning line X7) in the fourth row of the effective display section,
And an image corresponding to the video signal CL is simultaneously displayed on the fifth scanning line Line5 (scanning line X8). However,
The image corresponding to the video signal CL displayed on the fifth scanning line Line5 (scanning line X8) is overwritten by the image corresponding to the video signal DL output at the next timing, and substantially as a display image. It is not shown because it is not valid.

According to the above operation, the image data AL to CL from the source driver 4 are supplied to the scanning lines Line 1 to Line 4 which are the first to fourth rows of the effective display section of the liquid crystal panel 2 at the timing of the gate pulse clock signal GPCK.
Four (scanning line X4 to scanning line X7) images of four lines are displayed.

Thereafter, the same operation is repeated by P10 to P15 and further thereafter by the gate pulse clock signal GPCK, so that the liquid crystal display device 1 of this embodiment performs one scan for every three scan lines. By increasing the number of lines, the vertical scanning line can be extended 4/3 times, and 180 video signals can be increased to 240 lines.

In FIG. 6, the gate outputs X1 to X1
The waveform of X12 is always represented as a High signal in a period in which two gate pulse clock signals GPCK are received instead of being a Low signal in each retrace period, but actually, the gate driver 3 shown in FIG. As shown in FIG. 5, a gate output reset signal GRES that becomes a low signal is input for each retrace period, and during a period when the gate output reset signal GRES is a low signal, the gate output from the gate driver 3 is output. X1 to Xn
Is turned off by the AND gate circuit 35.

As described above, in the liquid crystal display device 1 of the present embodiment, the select signal repeatedly generated by the counter circuit 67 and the reset circuit 68 in the controller 6 and input to the select terminal S of the selector circuit 63. The gate pulse clock signal GPCK is generated at the timing shown in the time chart of FIG.
Is output to the gate driver 3 and one scanning line is added for every three scanning lines to reduce the number of vertical scanning lines to 4/3.
It is doubled so that 180 video signals can be increased to 240.

Therefore, in order to increase the number of horizontal scanning lines, it is not necessary to provide a complicated and large-scale decoder for performing a complicated operation for image processing. Small, low cost, 18
A liquid crystal display device that realizes a function of extending 0 vertical scanning lines to 240 lines can be provided.

Note that, in the liquid crystal display device 1 of the present embodiment, the first line (the image data A in FIG.
Although the number of scanning lines of the image (L) is increased, the number of the second line (BL) or the number of the third line (CL) may be increased.

In FIG. 6, the gate driver 3 in the liquid crystal display device 1 according to the present embodiment receives the gate start signal GSRT by two consecutive gate pulse clock signals GPCK of one retrace period, thereby forming the gate. The driver 3 is a two-latch type gate driver, but one gate pulse clock signal GPC every 1H.
K is received two times by the gate start signal GSRT of the 2H period, so that the gate driver 3
It may be a latch type gate driver, and furthermore,
Although the gate driver 3 shown in FIG. 2 is a two-latch type gate driver, it may be a one-latch type gate driver.

(Second Embodiment) In the liquid crystal display device 1 of the first embodiment, one scanning line is added for every three scanning lines, and the number of vertical scanning lines is reduced to 4/3. Stretched 18 times, 18
Although it was made possible to increase the number of video signals from zero to 240, in a small liquid crystal display device or the like,
In many cases, the number of scanning lines is 220. In such a case, it is effective to extend the vertical scanning lines by 6/5 and increase the number of 180 video signals to 216.

In the second embodiment, as described above, the liquid crystal display device 10 capable of extending the vertical scanning lines 6/5 times and increasing the number of video signals of 180 to 216 is possible. (Not shown) will be described in detail with reference to FIGS. In addition, the liquid crystal display device 1 according to the second embodiment
In the description of 0, the contents described in the first embodiment with reference to FIGS. 1 to 5 are effective unless otherwise specified.

First, the configuration will be described. The liquid crystal display device 10 according to the second embodiment has the same configuration as the liquid crystal display device 1 shown in FIG.
The counter circuit 6 comprises a source driver 4, a chroma interface 5, a controller 6, and the like.
7 is different.

That is, in the liquid crystal display device 1 of the first embodiment, one scanning line is added for every three scanning lines, and the vertical scanning line is extended 4/3 times. The counter circuit 67 was configured as a 2-bit binary counter that counts three pulse signals P100H. However, in the liquid crystal display device 10 according to the second embodiment, one scanning line is added for every five scanning lines, and the vertical scanning lines are extended 6/5 times. Counter circuit 6 shown
The counter circuit 80 shown in FIG.

In FIG. 7, the counter circuit 80 has a NO
R latch 801, 802, 803, and AND gate 8
04 is a 3-bit binary counter composed of a pulse signal P input from a flip-flop 65.
100H is counted, and when the count value becomes “5”, a High signal is output to the selector circuit 63 and the reset circuit 68. This counter circuit 80
The counting operation of the pulse signal P100H is based on each circuit described below.

When the first pulse signal P100H is input from the flip-flop 65, the NOR latch 801 changes the output of the output terminal X to a High signal at the falling edge of the first pulse signal P100H. When the second pulse signal P100H is input, the output terminal X is output at the falling edge of the second pulse signal P100H.
Is a Low signal. This NOR latch 801
Is output from the High signal to L
The falling edge of the LOW signal causes the NOR latch 80
2 sets the output of the output terminal X to a High signal.

When the third pulse signal P100H is input from the flip-flop 65 to the NOR latch 801, the NOR latch 801 changes the output of the output terminal X to H again.
The signal is an "high" signal. When the third pulse signal P100H is received, the signals output from the output terminals X of the NOR latch 801 and the NOR latch 802 are both High.
h signal.

When the fourth pulse signal P100H is input, the output of the output terminal X of the NOR latch 801 becomes Lo at the falling edge of the fourth pulse signal P100H.
It becomes a w signal. The output terminal X of the NOR latch 801
The NOR latch 802 sets the output of the output terminal X to a low signal at the falling edge at which the signal output from the high-level signal changes from the high signal to the low signal. Also, NOR latch 8
The NOR latch 803 sets the output of the output terminal X to a High signal at the falling edge at which the signal output from the output terminal X of No. 02 changes from the High signal to the Low signal.

Further, when the fifth pulse signal P100H is input, the output of the output terminal X of the NOR latch 801 becomes a High signal at the falling edge of the fifth pulse signal P100H. The fifth pulse signal P100H
, The signals output from the output terminals X of the NOR latch 801 and the NOR latch 803 are both Hi.
gh signal, and both input terminals of the AND gate 804 receive a High signal. Therefore, the signal output from the AND gate 804 becomes a High signal when the pulse signal P100H input from the flip-flop 65 is counted five times.

The above is the description of the pulse signal P of the counter circuit 80.
It is an explanation of each circuit responsible for the 100H count operation.

Since the circuit configuration other than the counter circuit 80 is the same as that of the liquid crystal display device 1 of the first embodiment, the description is omitted here, but the counter circuit 80 inside the controller 6 and the reset circuit 68 and the select terminal S of the selector circuit 63.
The gate pulse clock signal GPCK is output to the gate driver 3 at a timing as shown in the time chart of FIG. By controlling the gate driver 3 at the timing of the gate pulse clock signal GPCK, the vertical scanning line can be extended 6/5 times.

The operation of the liquid crystal display device 10 for extending the vertical scanning lines 6/5 times will be described below. First, the operation of the controller 6, in which one gate pulse clock signal GPCK is increased every five gate pulse clock signals GPCK in order to extend the vertical scanning line by 6/5 times, is described in the first embodiment. The following description focuses on the operation of the counter circuit 80, which is different from the liquid crystal display device 1 of the first embodiment.

When the first pulse signal P100H is input from flip-flop 65, NOR latch 801
Sets the output of the output terminal X to a High signal at the falling edge of the first pulse signal P100H. At this time, since the output of the output terminal X of the NOR latch 803 is a Low signal, the select signal output from the AND gate 804 to the select terminal S of the selector 633 in the selector circuit 63 is a Low signal. . Therefore, the selector 633 is connected to the JK flip-flop 63
A GPCK generation signal gpck1 input from 1 is output to the gate driver 3 as a gate pulse clock signal GPCK. The gate pulse clock signal G
PCK is the first gate pulse clock signal GPCK
It turns out that.

On the other hand, at this time, the Low signal input to the flip-flop 681 in the reset circuit 68 from the AND gate 804 is latched inside the flip-flop 681, and the pulse signal P25H input to the clock terminal CK of the flip-flop 681. Is output to one input terminal of the AND gate 684 at the timing of. On the other hand, the Low signal input to the inversion gate 682 is inverted and output to the flip-flop 683 as a High signal, and the High signal is output to the flip-flop 6.
83, and is output to the other input terminal of the AND gate 684 at the timing of the pulse signal P50H input to the clock terminal CK of the flip-flop 683. Therefore, at this time, the AND gate 68
Since the reset signal input to the reset terminal R of the counter circuit 80 from No. 4 is a Low signal, the counter circuit 80 is not reset.

Further, when the second pulse signal P100H is input from the flip-flop 65, the NOR latch 8
01 indicates that the output of the output terminal X is a Low signal at the falling edge of the second pulse signal P100H. this,
At the falling edge at which the signal output from the output terminal X of the NOR latch 801 changes from the High signal to the Low signal, the NOR latch 802 changes the output of the output terminal X to High.
h signal. At this time, the outputs of the output terminals X of the NOR latch 801 and the NOR latch 803 are both Low.
Since the signal is a signal, the select signal output from the AND gate 804 to the select terminal S of the selector 633 in the selector circuit 63 is still a Low signal. Therefore, the selector 633 outputs the GPCK generation signal gpck1 input from the JK flip-flop 631.
To the gate driver 3 as the gate pulse clock signal GPCK. The gate pulse clock signal GPCK is the second gate pulse clock signal GPCK.

On the other hand, at this time, similar to the operation after the first gate pulse clock signal GPCK is generated,
Since the reset signal input from the AND gate 684 to the reset terminal R of the counter circuit 80 is a low signal, the counter circuit 80 is not reset.

Further, when the third pulse signal P100H is input from the flip-flop 65, the NOR latch 8
01 makes the output of the output terminal X a High signal again at the falling edge of the third pulse signal P100H.
When the third pulse signal P100H is received, NO
Output terminals X of R latch 801 and NOR latch 802
Are both High signals. At this time, since the output of the output terminal X of the NOR latch 803 is a Low signal, the AND gate 804 outputs the select terminal S of the selector 633 in the selector circuit 63.
Is a Low signal. Therefore, the selector 633 outputs the GPCK generation signal gpc input from the JK flip-flop 631.
k1 is output to the gate driver 3 as the gate pulse clock signal GPCK. The gate pulse clock signal GPCK is the third gate pulse clock signal GPCK.

On the other hand, at this time, as in the operation after the first gate pulse clock signal GPCK is generated,
Since the reset signal input from the AND gate 684 to the reset terminal R of the counter circuit 80 is a low signal, the counter circuit 80 is not reset.

Further, when the fourth pulse signal P100H is input from the flip-flop 65, the NOR latch 8
01 makes the output of the output terminal X a Low signal again at the falling edge of the fourth pulse signal P100H. At the falling edge at which the signal output from the output terminal X of the NOR latch 801 changes from a High signal to a Low signal, the NOR latch 802 changes the output of the output terminal X to Lo.
Let it be a w signal. Also, the output terminal X of the NOR latch 802
The NOR latch 803 sets the output of the output terminal X to a High signal at the falling edge at which the signal output from the high-level signal changes from the High signal to the Low signal. At this time, since the output of the output terminal X of the NOR latch 801 is a Low signal, the AND gate 804 outputs
The select signal output to the select terminal S of the selector 633 is a Low signal. Therefore, the selector 633 outputs the GPCK generation signal gpck1 input from the JK flip-flop 631 to the gate driver 3 as the gate pulse clock signal GPCK. The gate pulse clock signal GPCK is
This is the fourth gate pulse clock signal GPCK.

On the other hand, at this time, similar to the operation after generation of the first gate pulse clock signal GPCK,
Since the reset signal input from the AND gate 684 to the reset terminal R of the counter circuit 80 is a low signal, the counter circuit 80 is not reset.

Further, when the fifth pulse signal P100H is input from the flip-flop 65, the NOR latch 8
01 makes the output of the output terminal X a High signal again at the falling edge of the fifth pulse signal P100H.
When the fifth pulse signal P100H is received, NO
Output terminals X of R latch 801 and NOR latch 803
Are both High signals, and both input terminals of the AND gate 804 receive the High signal. At this time, AN
The select signal output from the D gate 804 to the select terminal S of the selector 633 in the selector circuit 63 is a High signal. Therefore, the selector 63
3 outputs the GPCK generation signal gpck2 input from the JK flip-flop 632 to the gate driver 3 as a gate pulse clock signal GPCK. Since the GPCK generation signal gpck2 is two consecutive pulse signals as shown in FIG. 5, the gate pulse clock signal GPCK is the fifth and sixth gate pulse clock signal GPCK.

At this time, the High signal input from the AND gate 804 to the flip-flop 681 in the reset circuit 68 is latched inside the flip-flop 681 and the clock terminal CK of the flip-flop 681 is output.
AND at the timing of the pulse signal P25H
The signal is output to one input terminal of the gate 684. Further, at this time, the flip-flop 683 maintains the state after the fourth gate pulse clock signal GPCK is generated,
h signal, the AND gate 684 outputs a High signal input from the flip-flop 683,
And Hig input from the flip-flop 681
In response to the h signal, a High signal is output to the reset terminal R of the counter circuit 80 as a reset signal, and the count value of the counter circuit 80 is reset.

On the other hand, Hi input to the inversion gate 682
The gh signal is inverted and output to the flip-flop 683 as a low signal. The low signal is latched inside the flip-flop 683 and the pulse signal P input to the clock terminal CK of the flip-flop 683.
The signal is output to the other input terminal of the AND gate 684 at the timing of 50H. Therefore, at this time, AN
D gate 684 to reset terminal R of counter circuit 80
Is a Low signal, so that
The reset of the counter circuit 80 is released.

That is, the counter circuit 80 sets the pulse signal P100H input from the flip-flop 65 to 5
Counting is performed, and a High signal is input to the select terminal S of the selector 633 in the selector circuit 63 as a select signal, and is output as a gate pulse clock signal GPCK.
A GPCK generation signal gpck2 is output. Thereafter, the counter circuit 80 is reset by the reset circuit 68 at the timing of the pulse signal P25H about 15.9 μsec later, and further, the pulse signal P5 after about 15.9 μsec.
The reset is released by the reset circuit 68 at the timing of 0H, and the next pulse signal P100H is counted again as the first pulse signal P100H.
The same operation is repeated.

By the operation of the controller 6 repeated as described above, one gate pulse clock signal GPCK is generated for every five gate pulse clock signals GPCK.
And the gate pulse clock signal GPCK is changed to 6
/ 5-fold.

Next, the operation of the liquid crystal display device 10 in which the vertical scanning line is extended 6/5 times by the gate pulse clock signal GPCK increased 6/5 times by the above-described operation will be described with reference to a time chart shown in FIG. Will be described along the timings of P21 to P29 representing the gate pulse clock signal GPCK.

In FIG. 8, the video signal shown in the top row is
The gate pulse clock signal GPCK shown in the second column, which is a video signal input to the chroma interface 5 in FIG. 1, represents the gate pulse clock signal GPCK generated by the controller 6 and input to the gate driver 3 by the above-described operation. The gate start signal GSRT in the third column indicates the gate start signal GSRT generated by the controller 6 and input to the gate driver 3.

Gate outputs X1, X2, X3,..., X1
1,... (FIG. 8 does not show X11 and thereafter).
Is a buffer circuit 36 of the gate driver 3 shown in FIG.
, Represents an electrode drive signal output to each scanning line (gate line) Xn, and indicates that the scanning line (gate line) is turned ON when a High signal is applied. ,,,,,,,,, On the signal line representing each gate output Xn, correspond to the symbols below the waveform representing the video signal at the uppermost stage. This means that image data corresponding to the video signal is output from the source driver 4 to the scanning line (gate line). To visually explain this, in FIG. 8, the gate output X
11, the source driver output is represented in time series using the above-mentioned codes.

In FIG. 8, first, the gate start signal G
The SRT is input to the gate driver 3, and while the gate start signal GSRT is ON, P21 and P22 are used as gate pulse clock signals GPCK.
Is input, the gate driver 3 changes the gate start signal GSRT to the gate pulse clock signal G.
To receive from PCK2, n-bit shift register 34
Is a 2-latch n-bit shift register that latches two High signals. This operation is performed by using the gate pulse clock signal GPCK as P1 and P2 in FIG.
Since the operation is the same as that of the liquid crystal display device 1 of the first embodiment when is input, detailed description is omitted.

The gate pulse clock signal GPCK
Occurs, the n-bit shift register 3
4 by shifting the High signal, the gate output X
1 turns ON.

The pulse signal P100H immediately before P23 is converted by the counter circuit 80 into the first pulse signal P100H.
Then, when P23 is generated as the gate pulse clock signal GPCK, the gate output X1
Is kept ON, the gate output X2 is turned ON, and at the same time, the source driver 4 outputs image data corresponding to the video signal.
Images corresponding to the video signals are simultaneously displayed on the first and second scanning lines X2. However, the second scanning line X2
The image corresponding to the video signal displayed at the next time is overwritten by the image corresponding to the video signal output at the next timing, as described later, and is not substantially effective as a display image.

The next pulse signal P100H is counted as the second pulse signal P100H by the counter circuit 80, and then the gate pulse clock signal GPC
When P24 occurs as K, the gate output X1 is turned off.
And the gate output X3 is turned on while the gate output X2 is kept on. At the same time, the image data corresponding to the video signal is output from the source driver 4, and the scanning lines X2 and 3 in the second row of the display unit are displayed. Scanning line X3 of the row
Then, an image corresponding to the video signal is simultaneously displayed. Therefore, at the timing of P24, the image corresponding to the video signal displayed on the second scanning line X2 and displayed at the timing of P23 is overwritten by the image corresponding to the video signal. Hereinafter, only valid display images will be referred to, and invalid display images which will be overwritten later will not be referred to.

The next pulse signal P100H is counted as the third pulse signal P100H by the counter circuit 80, and subsequently, the gate pulse clock signal GPC
When P25 is generated as K, the gate output X2 is turned off.
And the gate output X4 is turned on while the gate output X3 is kept on. At the same time, the image data corresponding to the video signal is output from the source driver 4, and the scanning line X3 on the third row of the display unit, the video signal Is displayed.

The next pulse signal P100H is counted as the fourth pulse signal P100H by the counter circuit 80, and subsequently, the gate pulse clock signal GPC
When P26 is generated as K, the gate output X3 is turned off.
And the gate output X5 is turned on while the gate output X4 is kept on. At the same time, the image data corresponding to the video signal is output from the source driver 4, and the scanning lines X4 and X5 in the fourth row of the display unit are displayed. Row scanning line X5
Then, an image corresponding to the video signal is simultaneously displayed. The image corresponding to the video signal displayed on the scanning line X5 becomes an effective display image without being overwritten by the image corresponding to the next video signal, as described later.

The next pulse signal P100H is counted as the fifth pulse signal P100H by the counter circuit 80, and subsequently, the gate pulse clock signal GPC
When P27 due to the GPCK generation signal gpck2 is generated as K, the gate output X4 is turned off, and the gate output X6 is turned on while the gate output X5 is kept on.

Subsequently, when P28 is generated by the GPCK generation signal gpck2, the gate output X5 is turned off, and the gate output X6 is kept on while the gate output X6 is kept on.
7 is turned on, and at the same time, the image data corresponding to the video signal is output from the source driver 4, and the image corresponding to the video signal is displayed on the sixth scanning line X6 of the display unit. The two gate pulse clock signals GPCK of P27 and P28 fall within one retrace period, and no image is displayed during this retrace period. Therefore, the image corresponding to the video signal displayed on the scanning line X5 is Thus, an effective display image is obtained without being overwritten by an image corresponding to the next video signal.

The next pulse signal P100H is counted as the first pulse signal P100H by the counter circuit 80 which has been reset by the reset circuit 68 and has a count value of "0", and subsequently the gate pulse clock signal GPCK. Occurs, the gate output X6 is turned off, the gate output X8 is turned on while the gate output X7 is kept on, and at the same time, the image data corresponding to the video signal is output from the source driver 4, and the display unit The image corresponding to the video signal is simultaneously displayed on the seventh scanning line X7.

With the above operation, the image data 〜 from the source driver 4 is changed to the gate pulse clock signal G
At the timing of PCK, six lines of images are displayed on the scanning lines X1 to X6, which are the first to sixth rows of the display unit of the liquid crystal panel 2.

Gate pulse clock signal G after P29
The same operation is repeated by the PCK, so that the liquid crystal display device 10 of the present embodiment increases the number of vertical scanning lines by 6 by increasing the number of scanning lines by one for every five scanning lines.
Thus, it is possible to expand the video signal of 180 lines to 216 lines by expanding the image signal by / 5 times.

In FIG. 8, the gate outputs X1 to X1
The waveform of X11 is always represented as a High signal in a period during which two gate pulse clock signals GPCK are received instead of being a Low signal in each retrace period, but actually, the gate driver 3 shown in FIG. As shown in FIG. 5, a gate output reset signal GRES that becomes a low signal is input for each retrace period, and during a period when the gate output reset signal GRES is a low signal, the gate output from the gate driver 3 is output. X1 to Xn
Is turned off by the AND gate circuit 35.

As described above, in the liquid crystal display device 10 of the present embodiment, the select circuit repeatedly generated by the counter circuit 80 and the reset circuit 68 in the controller 6 and input to the select terminal S of the selector circuit 63. The gate pulse clock signal GPC is generated at the timing shown in the time chart of FIG.
K is output to the gate driver 3 and the scanning line 5
The number of vertical scanning lines is increased by 6 /
The video signal is expanded by a factor of five, so that 180 video signals can be increased to 216 video signals.

Therefore, even in a small-sized liquid crystal display device having 220 scanning lines, a complicated large-scale circuit for performing a complicated operation for image processing is required in order to increase the number of horizontal scanning lines. A simple gate driver control circuit reduces the size and cost
A liquid crystal display device that realizes a function of extending 180 horizontal scanning lines to 216 lines can be provided.

In the liquid crystal display device 10 according to the present embodiment, the fourth line (the scanning line of the image based on the image data in FIG. 8) at the start of the video display is increased.
Any of the scanning lines in the line (目) may be added. (In the liquid crystal display device 1 according to the first embodiment, the case where the number of the first line is increased has been described. That is, the gate pulse clock signal GPC is used to display an image.
It can be changed depending on whether to start at the timing of K. )

In FIG. 8, in the gate driver 3 of the liquid crystal display device 10 of the present embodiment, similarly to the liquid crystal display device 1 of the first embodiment, the gate start signal GSRT is changed for one blanking period. By receiving two consecutive gate pulse clock signals GPCK, the gate driver 3 is a two-latch gate driver. However, one gate pulse clock signal GPCK is generated every 1H.
By the gate start signal GSRT in the 2H period,
By receiving two shots, the gate driver 3 may be a two-latch type gate driver.
Is a two-latch type gate driver, but this may be used as a one-latch type gate driver.

Further, the counter circuit 67 of the liquid crystal display device 1 of the first embodiment is replaced with the counter circuit 80 of the liquid crystal display device 10 of the second embodiment, The counter circuit 80 has another circuit configuration, and two scanning lines are added every nine scanning lines, the vertical scanning lines are extended 11/9 times, and 180 video signals are reduced to 220 lines. The configuration may be increased.

(Third Embodiment) In the liquid crystal display device 1 (liquid crystal display device 10) according to the first (second) embodiment, one scan is performed for every three (five) scan lines. The vertical scanning line was extended 4/3 times (6/5 times) by increasing the
In order to increase the number of video signals from 0 to 240 (216), three gate pulse clock signals GPCK (five)
Each time, the gate pulse clock signal GPCK was increased by one so as to fall within the retrace period. In this case, the video signal for one scanning line is 1
During the 1H period, the gate pulse clock signal GPCK is generated in the middle of the 1H period, and the n-bit shift register 34 in the gate driver 3 is shifted by 1 bit earlier than the normal timing, and two lines are shifted in the 1H period. Can also be displayed.

In the third embodiment, as described above, the gate pulse clock signal GPC is applied in the middle of the 1H period.
K is generated and the n-bit shift register 34 in the gate driver 3 is set to 1 bit earlier than normal timing.
By shifting and displaying two lines of video in the 1H period, one scanning line is added for every three scanning lines, and the vertical scanning line is extended 4/3 times, and A liquid crystal display device 100 (not shown) for increasing the number of video signals of a book to 240 will be described in detail with reference to FIGS.

First, the configuration will be described. The liquid crystal display device 100 according to the third embodiment includes the liquid crystal display device 1 shown in FIG.
LCD panel 2, gate driver 3, source driver 4, chroma interface 5,
And the controller 6 and the like. However, the internal circuit configuration of the controller 6 is different from that shown in FIG.

The liquid crystal display device 100 according to the third embodiment
FIG. 9 shows an internal circuit configuration of the controller 6 constituting the controller 6. FIG. 9 shows only the part related to the liquid crystal display device 100 of the third embodiment of the internal circuit configuration of the controller 6, and the same circuit as the internal circuit configuration of the controller 6 shown in FIG. Will be denoted by the same reference numerals and detailed description thereof will be omitted. Also, circuits such as the vertical decoder 76 shown in FIG. 3 are not shown.

In FIG. 9, the controller 6 comprises a falling synchronous counter 61, a horizontal decoder 94, a selector circuit 63, a flip-flop 65, a counter circuit 67,
It comprises a selector circuit 90, a flip-flop 91, a flip-flop 92, a reset circuit 93 and the like. In the following, among the internal circuits constituting the controller 6, respective circuits relating to the generation of the gate pulse clock signal GPCK and the gate output reset signal GRES will be described.

The falling synchronous counter 61 is provided with a clock inversion signal CKB input to the clock terminal Clock.
The horizontal decoder 94 is controlled by performing a count operation and outputting the count value to the horizontal decoder 94.

The horizontal decoder 94 outputs various control signals according to the count value input from the falling synchronous counter 61. That is, the horizontal decoder 94
Are GPCK generation signals gpck1s, gpck1r, g for generating a gate pulse clock signal GPCK.
GRES generation signals gres1s, gres1 for outputting pck2s and gpck2r to the selector circuit 63 and generating a gate output reset signal GRES.
r, gres2s, and gres2r are connected to the selector circuit 9
Output for 0. The horizontal decoder 94 outputs the pulse signal P100H to the counter circuit 67 via the flip-flop 65, and outputs the pulse signal P50H.
Is output to the reset circuit 93 via the flip-flop 91, and the pulse signal P75H is output to the reset circuit 93 via the flip-flop 92. Here, the pulse signal P100H is a pulse output in synchronization with the timing of the horizontal synchronization signal, and the pulse signal P100H
50H is a time (about 3 hours) obtained by dividing 1H (1 horizontal period: about 63.5 μsec) into two with respect to the pulse signal P100H.
This pulse is output with a delay of 1.8 μsec (see FIG. 10). The pulse signal P75H is the pulse signal P
1H was further divided into 4 equal parts from 50H (about 15.9 μs
ec) is a pulse that is output with a delay (see FIG. 10).

The selector circuit 63 includes a JK flip-flop 631, a JK flip-flop 632, and a selector 633. The GPCK generation signals gpck1s and gpck1 input from the horizontal decoder 94 are provided.
The gate pulse clock signal GPCK generated based on r, gpck2s, and gpck2r is output to the gate driver 3.

The selector circuit 90 includes a JK flip-flop 901, a JK flip-flop 902, and a selector 903. The GRES generation signals gres1s, gres1 input from the horizontal decoder 94.
The gate output reset signal GRES generated based on r, gres2s, and gres2r is output to the gate driver 3. The operation of the selector circuit 90 for generating the gate output reset signal GRES is performed by each circuit described below.

The JK flip-flop 901 generates the GRES generation signal gres1s input to the terminal J from the horizontal decoder 94 and the GRES generation input to the terminal K under the timing of the inverted clock signal CKB input to the clock terminal CK. Based on the signal gres1r, GRES
A generation signal gres1 (see FIG. 10) is generated and output from the terminal X to the input terminal A of the selector 903.

The JK flip-flop 902 outputs the GRES generation signal gres2s input to the terminal J from the horizontal decoder 94 and the GRES generation input to the terminal K under the timing of the inverted clock signal CKB input to the clock terminal CK. Based on the signal gres2r, GRES
A generation signal gres2 (see FIG. 10) is generated and output from the terminal X to the input terminal B of the selector 903.

The selector 903 is the selector 6 shown in FIG.
33, and when the select signal input to the select terminal S from the counter circuit 67 is a Low signal, the GRES generation signal g input to the input terminal A
res1 from the output terminal X to the gate output reset signal G
RES is output to the gate driver 3.
When the select signal input from the counter circuit 67 to the select terminal S is a High signal, the selector 903 outputs the GRES generation signal g input to the input terminal B.
res2 from the output terminal X to the gate output reset signal G
RES is output to the gate driver 3.

The above is a description of each circuit responsible for the gate output reset signal GRES generation operation of the selector circuit 90.

The flip-flop 65 is connected to the horizontal decoder 9
Latch the pulse signal P100H input from 4 and
Clock inverted signal CKB input to clock terminal CK
Is output to the counter circuit 67 at the same timing. The flip-flop 91 latches the pulse signal P50H input from the horizontal decoder 94 and outputs the same to the reset circuit 93 in accordance with the timing of the inverted clock signal CKB input to the clock terminal CK. The flip-flop 92 latches the pulse signal P75H input from the horizontal decoder 94 and outputs the same to the reset circuit 93 in accordance with the timing of the inverted clock signal CKB input to the clock terminal CK.

The counter circuit 67 includes a NOR latch 67
1, a 2-bit binary counter constituted by a NOR latch 672 and an AND gate 673, and a pulse signal P100H input from the flip-flop 65
Is counted, and when the count value becomes “3”, Hig
The h signal is output to the selector circuit 63, the selector circuit 90, and the reset circuit 68.

The reset circuit 93 is connected to the flip-flop 9
31, a high-level signal input from the counter circuit 67, a pulse signal P50H input from the horizontal decoder 94 via the flip-flop 91, and a flip-flop. The reset signal (High signal) is output to the reset terminal R of the counter circuit 67 based on the pulse signal P75H input from the horizontal decoder 94 via the counter 92. The reset operation of the counter circuit 67 by the reset circuit 93 is performed by each circuit described below.

Pulse signal P10 from counter circuit 67
When the count value of 0H is not "3", A
The signal input from the ND gate 673 to the reset circuit 93 is a Low signal, and the flip-flop 931
The Low signal is internally latched and output to one input terminal of the AND gate 934 at the timing of the pulse signal P50H input to the clock terminal CK. The inversion gate 932 inverts the Low signal, The signal is output to the flip-flop 933 as a High signal. The flip-flop 933 latches the High signal internally, and outputs a pulse signal P75H input to the clock terminal CK.
At the timing of (1) and outputs to the other input terminal of the AND gate 934.

Pulse signal P10 from counter circuit 67
The count value of 0H becomes “3” and the AND gate 67
3 to the reset circuit 93 is High.
When a signal is output, the flip-flop 931 outputs the signal High.
The signal is internally latched, and the inverting gate 932
The h signal is inverted and output to the flip-flop 933 as a low signal, and the flip-flop 933 latches the low signal internally. At this time, a signal input from the flip-flop 933 to one terminal of the AND gate 934 is a High signal, and a signal input from the flip-flop 931 to the other terminal of the AND gate 934 is a Low signal. So, AN
From the D gate 934 to the reset terminal R of the counter circuit 67
Is a Low signal.

When the pulse signal P50H is input from the flip-flop 91 to the clock terminal CK of the flip-flop 931 about 31.8 μsec after the High signal input from the counter circuit 67, the pulse signal P50H rises. On the falling edge, the flip-flop 931 outputs the internally latched High signal from the output terminal X to one input terminal of the AND gate 934. At this time, the AND gate 934 outputs the High signal input from the flip-flop 933 and the High signal input from the flip-flop 931.
Upon receiving the signal, a High signal is output to the reset terminal R of the counter circuit 67 as a reset signal, and the count value of the counter circuit 67 is reset.

Further, about 15.9 μm of the pulse signal P50H
After sec, the clock terminal C of the flip-flop 933
When the pulse signal P75H is input to K, the flip-flop 93 is input at the falling edge of the pulse signal P75H.
Reference numeral 3 outputs the internally latched Low signal from the output terminal X to one input terminal of the AND gate 934. In response to the Low signal, the AND gate 934 outputs L
The ow signal is output to the reset terminal R of the counter circuit 67, and the reset of the counter circuit 67 is released.

The above is an explanation of each circuit of the reset circuit 93 responsible for the reset operation of the counter circuit 67.

The above is a description of each of the circuits relating to the generation of the gate pulse clock signal GPCK and the gate output reset signal GRES among the internal circuits constituting the controller 6. The selector circuit 63 and the selector circuit 90 are repeatedly generated by the counter circuit 67 and the reset circuit 93 inside the controller 6.
Select signal input to the select terminal S of
The gate pulse clock signal GPCK is output to the gate driver 3 at the timing as shown in the time chart of FIG. 11, and the gate pulse clock signal GP for displaying the same two lines at regular intervals.
By controlling the gate driver 3 at the timing of CK, the vertical scanning line can be extended 4/3 times.

Hereinafter, the operation of the liquid crystal display device 100 for extending the vertical scanning lines by 4/3 will be described. First, an operation of the controller 6 for increasing one gate pulse clock signal GPCK for every three gate pulse clock signals GPCK in order to extend the vertical scanning line by 4/3 times will be described.

When a video signal is input to the chroma interface 5, a composite synchronizing signal C is obtained from the input video signal.
When the SYNC is separated and output to the controller 6, the input video signal is separated into R, G, and B signals, and the inverted image data for video display is generated by the controller 6. Are output to the source driver 4 at a timing based on the horizontal synchronization signal input from the source driver 4.

When the composite synchronizing signal CSYNC is input to the controller 6, the composite synchronizing signal CSYNC and the falling synchronizing counter 61 are supplied to the clock terminal Clock.
The horizontal decoder 94 is controlled by a count value output to the horizontal decoder 94 by performing a count operation in response to a clock inversion signal CKB input to the horizontal decoder 94.

That is, the horizontal decoder 94 generates a gate pulse clock signal GPCK.
PCK generation signals gpck1s, gpck1r, gpck
2s and gpck2r are output to the selector circuit 63, and GRES generation signals gres1s, gres1r,
Gres2s and gres2r are output to the selector circuit 90. Also, the horizontal decoder 94
The pulse signal P100H is output to the counter circuit 67 via the flip-flop 65 and the pulse signal P5
0H is supplied to the reset circuit 9 via the flip-flop 91.
3 and the pulse signal P75H is output to the reset circuit 93 via the flip-flop 92.

From the horizontal decoder 94, the selector circuit 63
, Based on the GPCK generation signal gpck1s input to the terminal J of the JK flip-flop 631 and the GPCK generation signal gpck1r input to the terminal K.
A K generation signal gpck1 (see FIG. 10) is generated and output from the terminal X to the input terminal A of the selector 633.

From the horizontal decoder 94, the selector circuit 63
, Based on the GPCK generation signal gpck2s input to the terminal J of the JK flip-flop 632 and the GPCK generation signal gpck2r input to the terminal K.
A K generation signal gpck2 (see FIG. 10) is generated and output from the terminal X to the input terminal B of the selector 633.

As shown in FIG. 10, the pulse signal P100
H is output at the same 1H cycle as the GPCK generation signal gpck1 and at a timing slightly later than the GPCK generation signal gpck1. This pulse signal P100H
Is input from the horizontal decoder 94 to the NOR latch 671 in the counter circuit 67 via the flip-flop 65.

From the flip-flop 65 to the counter circuit 6
7, immediately before the first pulse signal P100H is input, the select signal output from the AND gate 673 to the select terminal S of the selector 633 in the selector circuit 63 is a Low signal ( This is based on a reset operation of the counter circuit 67 by a reset circuit 93 described later. Therefore, the selector 633 outputs the GPCK generation signal gp input from the JK flip-flop 631.
ck1 as a gate pulse clock signal GPCK
Output to the gate driver 3. The gate pulse clock signal GPCK is the first gate pulse clock signal GPCK. Further, the selector circuit 90 outputs the GRES generation signal gres1 input from the JK flip-flop 901 to the gate driver 3 as a gate output reset signal GRES.

When the first pulse signal P100H is input from flip-flop 65, NOR latch 671
Sets the output of the output terminal X to a High signal at the falling edge of the first pulse signal P100H. At this time, since the output of the output terminal X of the NOR latch 672 is a Low signal, the select signal output from the AND gate 673 to the select terminal S of the selector 633 in the selector circuit 63 is a Low signal. .

Therefore, immediately before the second pulse signal P100H is input from the flip-flop 65 to the counter circuit 67, the selector 633 determines the GPCK generation signal gp input from the JK flip-flop 631.
ck1 as a gate pulse clock signal GPCK
Output to the gate driver 3. The gate pulse clock signal GPCK is the second gate pulse clock signal GPCK. Further, the selector circuit 90 outputs the GRES generation signal gres1 input from the JK flip-flop 901 to the gate driver 3 as a gate output reset signal GRES.

On the other hand, at this time, the Low signal input from the AND gate 673 to the flip-flop 931 in the reset circuit 93 is latched inside the flip-flop 931 and the pulse signal P50H input to the clock terminal CK of the flip-flop 931 Is output to one input terminal of the AND gate 934 at the timing of. On the other hand, the Low signal input to the inversion gate 932 is inverted and output as a High signal to the flip-flop 933, and the High signal is output to the flip-flop 933.
33, and is output to the other input terminal of the AND gate 934 at the timing of the pulse signal P75H input to the clock terminal CK of the flip-flop 933. Therefore, at this time, the AND gate 93
Since the reset signal input from 4 to the reset terminal R of the counter circuit 67 is a Low signal, the counter circuit 67 is not reset.

When the second pulse signal P100H is input from the flip-flop 65, the NOR latch 6
Reference numeral 71 designates the output of the output terminal X as a Low signal at the falling edge of the second pulse signal P100H. this,
At the falling edge at which the signal output from the output terminal X of the NOR latch 671 changes from a High signal to a Low signal, the NOR latch 672 changes the output of the output terminal X to High.
h signal. At this time, since the output of the output terminal X of the NOR latch 671 is a Low signal, the select signal output from the AND gate 673 to the select terminal S of the selector 633 in the selector circuit 63 is still a Low signal. It is.

Therefore, immediately before the third pulse signal P100H is input from the flip-flop 65 to the counter circuit 67, the selector 633 determines the GPCK generation signal gp input from the JK flip-flop 631.
ck1 as a gate pulse clock signal GPCK
Output to the gate driver 3. The gate pulse clock signal GPCK is the third gate pulse clock signal GPCK. Further, the selector circuit 90 outputs the GRES generation signal gres1 input from the JK flip-flop 901 to the gate driver 3 as a gate output reset signal GRES.

On the other hand, at this time, similar to the operation after the first gate pulse clock signal GPCK is generated,
Since the reset signal input from the AND gate 934 to the reset terminal R of the counter circuit 67 is a Low signal, the counter circuit 67 is not reset.

When the third pulse signal P100H is input from the flip-flop 65, the NOR latch 6
Reference numeral 71 designates the output of the output terminal X as a High signal again at the falling edge of the third pulse signal P100H.
When the third pulse signal P100H is received, NO
Output terminal X of R latch 671 and NOR latch 672
Are output as High signals, and both input terminals of the AND gate 673 receive the High signal. At this time, AN
The select signal output from the D gate 673 to the select terminal S of the selector 633 in the selector circuit 63 is a High signal.

Therefore, after the third pulse signal P100H is input from the flip-flop 65 to the counter circuit 67, the selector 633 sets the GPCK generation signal gpc input from the JK flip-flop 632.
k2 is output to the gate driver 3 as the gate pulse clock signal GPCK. The GPCK generation signal gpck2 is, as shown in FIG.
Since the pulse signal is generated in a cycle obtained by dividing the 1H period of pck1 into two equal parts, the fourth gate pulse clock signal GPCK is generated approximately 31.8 μsec after the third gate pulse clock signal GPCK. Will be. Further, the selector circuit 90 outputs the fourth gate pulse clock signal G by the GPCK generation signal gpck2.
At the same time as the PCK, a GRES generation signal gres2 input from the JK flip-flop 902 is output to the gate driver 3 as a gate output reset signal GRES.

On the other hand, at this time, the High signal input from the AND gate 673 to the flip-flop 931 in the reset circuit 93 is latched inside the flip-flop 931 and the clock terminal CK of the flip-flop 931
AND at the timing of the pulse signal P50H
The signal is output to one input terminal of the gate 934. Further, at this time, the flip-flop 933 keeps the state after the second generation of the gate pulse clock signal GPCK is generated,
h signal, the AND gate 934 outputs the High signal input from the flip-flop 933,
And Hig input from the flip-flop 931
In response to the h signal, a High signal is output to the reset terminal R of the counter circuit 67 as a reset signal, and the count value of the counter circuit 67 is reset.

The reset timing of the counter circuit 67 is performed at the timing of the pulse signal P50H as described above, but as shown in FIG.
Since the generation of 0H is slightly after the GPCK generation signal gpck2, after the fourth gate pulse clock signal GPCK is generated about 31.8 μsec after the third gate pulse clock signal GPCK, The counter circuit 67 will be reset.

On the other hand, Hi input to the inversion gate 932
The gh signal is inverted and output to the flip-flop 933 as a Low signal. The Low signal is latched inside the flip-flop 933 and the pulse signal P input to the clock terminal CK of the flip-flop 933.
The signal is output to the other input terminal of the AND gate 934 at a timing of 75H. Therefore, at this time, AN
From the D gate 934 to the reset terminal R of the counter circuit 67
Is a Low signal, so that
The reset of the counter circuit 67 is released.

The reset release timing of the counter circuit 67 is performed at the timing of the pulse signal P75H as described above. As shown in FIG. 10, the pulse signal P75H is changed to the next GPC after the generation of the pulse signal P50H.
Since it is generated before the generation of the K generation signal gpck1, the counting operation can be newly repeated from the next GPCK generation signal gpck1.

That is, the counter circuit 67 changes the pulse signal P100H input from the flip-flop 65 to 3
Counting is performed, and a High signal is input to the select terminal S of the selector 633 in the selector circuit 63 as a select signal, and is output as a gate pulse clock signal GPCK.
A GPCK generation signal gpck2 is output. Thereafter, the counter circuit 67 is reset by the reset circuit 93 at the timing of the pulse signal P50H about 31.8 μsec later, and further the pulse signal P7 after about 15.9 μsec.
The reset is released by the reset circuit 93 at the timing of 5H, and the next pulse signal P100H is counted again as the first pulse signal P100H.
The same operation is repeated.

By the operation of the controller 6 thus repeated, one gate pulse clock signal GPCK is generated for every three gate pulse clock signals GPCK.
And the gate pulse clock signal GPCK is set to 4
/ 3 times.

Next, the operation of the liquid crystal display device 100 in which the vertical scanning line is extended 4/3 times by the gate pulse clock signal GPCK increased 4/3 times by the above-described operation will be described with reference to the time chart shown in FIG. Will be described along the timings of P31 to P36 representing the gate pulse clock signal GPCK.

In FIG. 11, the video signals shown in the uppermost column are the video signals input to the chroma interface 5 in FIG. 1, and each video signal is provided with a code representing the video signal above. The gate output reset signal GRES shown in the second column represents the gate output reset signal GRES generated by the controller 6 by the above-described operation and input to the gate driver 3, and is Hi.
gh signal, A in the gate driver 3 shown in FIG.
This shows that the gate electrode drive signal is output from the ND gate circuit 35 to turn on the scanning line (gate line). Also, A, B, C, D, and E shown on the signal line representing the gate output reset signal GRES correspond to the symbols attached to the upper part of the waveform representing the uppermost video signal, and are indicated by the respective symbols. This means that image data corresponding to the video signal at the timing is output from the source driver 4 to a scanning line (gate line). The gate pulse clock signal GPCK shown in the third column represents the gate pulse clock signal GPCK generated by the controller 6 by the above-described operation and input to the gate driver 3. The number of lines shown in the lowermost row indicates the number of scanning lines (gate lines) Xn of the display unit of the liquid crystal panel 2 up to that time.

First, when a gate start signal GSRT (not shown in FIG. 11) is input to the gate driver 3 shown in FIG. 2, the inverting comparator circuit 31 uses the gate start signal GSRT input to the inverting input terminal as a reference. Assuming that the voltage has exceeded the voltage (the gate voltage input to the non-inverting input terminal (+)), the inversion signal of the gate start signal GSRT is output to the inverting gate circuit 32. And inverting comparator circuit 3
A signal having the same phase as the gate start signal GSRT input to 1 is output to the flip-flop 33.

When P31 is generated as the gate pulse clock signal GPCK, the inverting comparator circuit 31 outputs the gate pulse clock signal GP input to the inverting input terminal.
Assuming that CK (P31) has exceeded the reference voltage, the inverted signal of the gate pulse clock signal GPCK (P31) is output as the scan shift clock inverted signal CKB to the inverted gate circuit 32 and the clock terminal CK of the flip-flop 33. Then, the inverting gate circuit 32 further inverts the signal to make it a signal having the same phase as the gate pulse clock signal GPCK input to the inverting comparator circuit 31, and as the scan shift clock signal CK, the flip-flop 33
To the clock terminal CKB.

The flip-flop 33 has a clock terminal C
The gate start signal GSRT input to the terminal I is latched based on the scan shift clock inversion signal CKB input to K and the scan shift clock signal CK input to the clock terminal CKB. Output to the bit shift register 34, and the flip-flop at the first stage of the n-bit shift register 34 internally latches the scan start signal ST input from the flip-flop 33. Also, immediately after P31, FIG.
A pulse signal P10 inputted from the horizontal decoder 94 shown in FIG.
0H is counted as the first pulse signal P100H.

Further, the gate pulse clock signal GPCK
Occurs, the n-bit shift register 3
4 outputs the latched scan start signal ST to the AND gate connected to the scan line X1 of the AND gate circuit 35 at the timing of the scan shift clock signal CK input to the clock terminal CK. The output is output to the second-stage flip-flop, and the second-stage flip-flop internally latches the scan start signal. At the same time, the source driver 4 outputs image data A corresponding to the video signal A, and during the 1H period in which the gate output reset signal GRES after P32 is a High signal, the first line of the liquid crystal panel 2 Image data A corresponding to video signal A is displayed as a scanning line. Immediately after P32, the horizontal decoder 9 shown in FIG.
From the counter circuit 6 via the flip-flop 65
The pulse signal P100H input to 7 is counted as the second pulse signal P100H.

Further, the gate pulse clock signal GPCK
Occurs, the n-bit shift register 3
The second flip-flop of No. 4 outputs the latched scan start signal ST to the AND gate connected to the scan line X2 of the AND gate circuit 35 at the timing of the scan shift clock signal CK input to the clock terminal CK. And the flip-flop of the third stage, and the flip-flop of the third stage latches the scan start signal internally. At the same time, the image data B corresponding to the video signal B is output from the source driver 4, and during the half period of 1H in which the gate output reset signal GRES after P33 is a High signal, two lines of the liquid crystal panel 2 are output. The image data B corresponding to the video signal B
Is displayed. Immediately after P33, the pulse signal P100H input from the horizontal decoder 94 shown in FIG. 9 to the counter circuit 67 via the flip-flop 65 is counted as the third pulse signal P100H.

The counter circuit 67 that has counted three pulse signals P100H outputs a High signal as a select signal to the selector circuit 63 and the selector circuit 90. Therefore, the selector 633 inside the selector circuit 63 outputs the GPCK generation signal gpck2 input from the JK flip-flop 632 to the gate driver 3 as the gate pulse clock signal GPCK (P34 shown in FIG. 11). Also, the selector circuit 90
The internal selector 903 is a JK flip-flop 902
Is output to the gate driver 3 as the gate output reset signal GRES. That is, as shown in FIG. 11, the gate output reset signal GRES generates a Low signal at a time corresponding to the gate pulse clock signal GPCK P34.

When P34 is generated as the gate pulse clock signal GPCK by the operation described above, the third stage flip-flop of the n-bit shift register 34 inputs the latched scan start signal ST to the clock terminal CK. At the timing of the scan shift clock signal CK, the AND gate circuit 35 outputs the signal to the AND gate connected to the scan line X3 and the fourth flip-flop, and the fourth flip-flop outputs the scan start signal. Latch inside. At this time, the image data B corresponding to the video signal B is still output from the source driver 4, and the liquid crystal panel 2 is turned on during the half period of 1H when the gate output reset signal GRES after P34 is a High signal. The image data B corresponding to the video signal B is displayed as the third scanning line. Also, P
Immediately after 34, the count value of the counter circuit 67 is reset by the pulse signal P50H input to the reset circuit 93 via the flip-flop 91 from the horizontal decoder 94 shown in FIG. The reset of the counter circuit 67 is released by the pulse signal P75H input to the reset circuit 93 through the reset circuit 93.

Further, the gate pulse clock signal GPCK
Is generated, the n-bit shift register 3
4, the flip-flop of the fourth stage converts the latched scan start signal ST into an AND gate connected to the scan line X4 of the AND gate circuit 35 at the timing of the scan shift clock signal CK input to the clock terminal CK. And the flip-flop of the fifth stage, and the flip-flop of the fifth stage latches the scan start signal internally. At the same time, the image data C corresponding to the video signal C is output from the source driver 4, and during the 1H period in which the gate output reset signal GRES is a High signal after P35, the fourth line of the liquid crystal panel 2 Image data C corresponding to video signal C is displayed as a scanning line. Immediately after P35, the horizontal decoder 9 shown in FIG.
From the counter circuit 6 via the flip-flop 65
7 is counted as the first pulse signal P100H.

By the above operation, the image data A to C from the source driver 4 are converted to the gate pulse clock signal G
At the timing of the PCK, four lines of images are displayed on the scanning lines X1 to X4, which are the first to fourth rows of the display unit of the liquid crystal panel 2.

Gate pulse clock signal G after P36
The same operation is repeated by the PCK, so that the liquid crystal display device 100 of the present embodiment increases the number of vertical scanning lines by 4/3 by increasing the number of scanning lines by one for every three scanning lines. It is possible to increase the number of video signals from 180 to 240.

As described above, in the liquid crystal display device 100 according to the present embodiment, the selection terminal S of the selector circuit 63 and the selector circuit 90 is repeatedly generated by the counter circuit 67 and the reset circuit 93 in the controller 6. The gate pulse clock signal GPCK and the gate output reset signal GRES are output to the gate driver 3 at the timing shown in the time chart of FIG. The number of scanning lines is increased, the vertical scanning lines are expanded by 4/3 times, and 180 video signals are
It was made possible to increase the number to zero.

Therefore, in order to increase the number of horizontal scanning lines, it is not necessary to provide a complicated and large-scale decoder for performing a complicated operation for image processing. Small, low cost, 18
A liquid crystal display device that realizes a function of extending 0 horizontal scanning lines to 240 lines can be provided.

In the liquid crystal display device 100 according to the third embodiment, the second line (the scanning line of the image based on the image data B in FIG. 11) for starting the image display is increased. The line (A) or the third line (C) may be increased.

Further, the counter circuit 67 of FIG. 9 is replaced by a circuit having another configuration to increase the vertical scanning line by a factor of 6/5 or 1/11.
The extension may be 9 times.

Each of the circuit diagrams shown in the description of the first to third embodiments shows a circuit configuration as an example for realizing the present invention, and does not depart from the gist of the present invention. Of course, another circuit configuration having the same function may be used within the scope. Also, the magnification for extending the vertical scanning line can be freely set as appropriate.

In the first to third embodiments, the case where the present invention is applied to a liquid crystal display device has been described in detail as an example of the case where the present invention is applied. It goes without saying that the present invention extends not only to the liquid crystal display device but also to other matrix display devices such as a plasma display having a matrix type display panel.

[0219]

According to the present invention, the number of scanning timing signals can be increased arbitrarily and the number of scanning lines can be easily increased. A complicated and large-scale circuit decoder is not required to perform a complicated operation, and the function of extending the vertical scanning lines can be realized by a small-sized and low-cost matrix display device.

According to the fourth aspect of the present invention, even when the aspect ratio of the video signal is different from that of the display panel, the number of scanning lines of the video signal can be increased by a predetermined number. Optimal image display can be realized with a small-sized and low-cost matrix display device.

According to the fifth aspect of the present invention, even when the video signal is a video signal for a so-called wide screen and the display panel is an existing display panel having an aspect ratio of 4: 3, the scanning line of the video signal is used. Since the number can be increased by a predetermined number, the vertical scanning line of the video signal for a wide screen having an aspect ratio of 16: 9 is extended to 4/3 times, which is most suitable for a display panel having an aspect ratio of 4: 3. A simple video display can be realized with a small-sized and low-cost matrix display device.

According to the invention described in any one of claims 6 to 8, by employing the liquid crystal driving method of the present invention in a liquid crystal display device, a complicated operation for performing image processing can be performed. Since a decoder serving as a large-scale circuit is not required, when a function of extending a vertical scanning line is added to a liquid crystal display device, it can be realized at a small size and at low cost.

[Brief description of the drawings]

FIG. 1 is a schematic circuit configuration diagram of a liquid crystal display device 1 according to the present invention.

FIG. 2 is a diagram showing a circuit configuration example of a gate driver 3 shown in FIG.

FIG. 3 is a diagram showing a circuit configuration example of a controller 6 shown in FIG. 1;

FIG. 4 shows a selector circuit 6 in the controller 6 shown in FIG.
FIG. 6 is a diagram showing a circuit configuration example of a selector 633 forming No. 3;

FIG. 5 is a time chart showing various control signals for controlling the controller 6 shown in FIG. 3;

6 is a time chart showing an operation of extending a vertical scanning line by 4/3 times by a gate pulse clock signal GPCK generated by a controller 6 shown in FIG. 3;

FIG. 7 shows a liquid crystal display device 10 according to a second embodiment of the present invention.
5 is a diagram showing a circuit configuration example of a counter circuit 80 applied to replace the counter circuit 67 in the controller 6 shown in FIG.

8 is a time chart illustrating an operation of extending a vertical scanning line by 6/5 times by a gate pulse clock signal GPCK generated by a controller 6 illustrated in FIG. 3;

FIG. 9 shows a liquid crystal display device 10 according to a third embodiment of the present invention.
FIG. 4 is a diagram showing an example of a circuit configuration of the controller 6, which is applied as an alternative circuit to the controller 6 shown in FIG. 3 at 0.

10 is a time chart showing various control signals for controlling the controller 6 shown in FIG.

11 is a time chart showing an operation of extending a vertical scanning line by 4/3 times by a gate pulse clock signal GPCK generated by the controller 6 shown in FIG. 9;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Liquid crystal display device 2 Liquid crystal panel 3 Gate driver 31 Inverting comparator circuit 32 Inverting gate circuit 33 Flip-flop 34 N-bit shift register 35 AND gate circuit 36 Buffer circuit 4 Source driver 5 Chroma interface 6 Controller 61 Falling synchronous counter 62 Horizontal decoder 63 selector circuit 631,632 JK flip-flop 633 selector 633a, 633b AND gate 633c inversion gate 633d OR gate 64 JK flip-flop 65,66 flip-flop 67 counter circuit 671,672 NOR latch 673 AND gate 68 reset circuit 681,683 flip-flop 682 Inverting gate 684 AND gate 69 JK flip-flop 70 AND gate G, 71, 72 Flip-flop 73, 74 OR gate 75 Asynchronous counter 76 Vertical decoder 77, 78 Flip-flop 10 Liquid crystal display device 80 Counter circuit 801, 802, 803 NOR latch 804 AND gate 100 Liquid crystal display device 90 Selector circuit 901, 902 JK flip-flop 903 selector 91, 92 flip-flop 93 reset circuit 931, 933 flip-flop 932 inverting gate 934 AND gate 94 horizontal decoder

Claims (8)

[Claims] 1. A matrix display panel having a plurality of signal lines and a plurality of scanning lines arranged in a matrix, and having a display element at each intersection of the signal lines and the scanning lines; Timing setting means for generating a sampling signal for setting a timing for sampling a video signal, and a scanning timing signal for setting a scanning timing; and the plurality of scans at a scanning timing according to the scanning timing signal generated by the timing setting means Scanning means for sequentially scanning lines; sampling a video signal based on a sampling signal generated by the timing setting means to generate a signal line drive signal for driving the plurality of signal lines; A signal line driving means for driving, wherein the timing The determining unit includes a counting unit that counts a scanning timing set by the scanning timing signal. Each time the count value of the scanning timing reaches a predetermined value, the scanning is performed by increasing the number of the scanning lines by an arbitrary number. Generating a scanning timing signal for setting a timing, wherein the scanning means scans by increasing the number of the scanning lines by an arbitrary number at predetermined scanning timings according to the scanning timing signal generated by the timing setting means. Matrix display device. 2. The method according to claim 1, wherein the timing setting unit includes: a non-signal line driving period in which the signal line is not driven by the signal line driving unit after a count value of the scanning timing by the counting unit becomes a predetermined value; Generating a scanning timing signal for setting the scanning timing so as to simultaneously scan a plurality of the scanning lines; wherein the scanning unit is configured to perform the non-signal line driving period according to a scanning timing signal generated by the timing setting unit; 2. The matrix display device according to claim 1, wherein a plurality of the scanning lines are simultaneously scanned every time. 3. The timing setting means sequentially scans a plurality of the scanning lines at predetermined timings during a signal line driving period after a count value of the scanning timing by the counting means becomes a predetermined value. Generating a scanning timing signal for setting the scanning timing as described above, wherein the scanning means, in accordance with the scanning timing signal generated by the timing setting means, for each predetermined timing during the signal line driving period, 2. The matrix display device according to claim 1, wherein the scanning lines are sequentially scanned. 4. The image signal is a signal for displaying an image having a predetermined aspect ratio, and the aspect ratio is different from the aspect ratio of the matrix display panel. A scan timing signal for setting a scan timing so that the scan line is increased by a predetermined number so that the aspect ratio of the video signal becomes the aspect ratio of the matrix display panel every time the count value of the matrix signal reaches a predetermined value. The scanning means increases a predetermined number of the scanning lines according to a scanning timing signal set by the timing setting means so that an aspect ratio of the video signal becomes an aspect ratio of the matrix display panel. The matrix display device according to any one of claims 1 to 3, wherein scanning is performed by scanning. 5. The aspect ratio of the video signal is 16: 9, and the aspect ratio of the matrix display panel is 4: 9.
The matrix display device according to claim 4, wherein the number is 3. 6. A method according to claim 1, further comprising: arranging a plurality of signal lines and a plurality of scanning lines in a matrix and driving a matrix display panel having a display element at each intersection of the signal lines and the scanning lines. A sampling signal for setting a timing for sampling a video signal, and a scanning timing signal for setting a scanning timing, and sequentially scanning the plurality of scanning lines at a scanning timing according to the scanning timing signal; and In the matrix display device driving method for generating a signal line driving signal for driving the plurality of signal lines by sampling a video signal based on the sampling signal and driving each of the display elements, the method is set by the scanning timing signal The scanning timing is counted, and each time the count value of the scanning timing reaches a predetermined value, the scanning line is arbitrarily set. A matrix display, comprising: generating a scan timing signal for setting the scan timing so as to increase the number of scans, and scanning the scan line by increasing the number of scan lines at predetermined scan timings in accordance with the scan timing signal. Device driving method. 7. The scanning timing is set such that a plurality of scanning lines are simultaneously scanned each time a non-signal line driving period in which the signal line is not driven is performed after the count value of the scanning timing becomes a predetermined value. 7. The method according to claim 6, further comprising: generating a scan timing signal for scanning, and scanning the plurality of scan lines simultaneously in each non-signal line drive period according to the scan timing signal. 8. A scanning timing for setting the scanning timing so as to sequentially scan a plurality of the scanning lines at each predetermined timing during a signal line driving period after the count value of the scanning timing becomes a predetermined value. 7. The method according to claim 6, wherein a signal is generated, and a plurality of the scanning lines are sequentially scanned at predetermined timings during the signal line driving period in accordance with the scanning timing signal. .