JPH05160133A - Electrode structure of semiconductor device - Google Patents
Electrode structure of semiconductor deviceInfo
- Publication number
- JPH05160133A JPH05160133A JP3321955A JP32195591A JPH05160133A JP H05160133 A JPH05160133 A JP H05160133A JP 3321955 A JP3321955 A JP 3321955A JP 32195591 A JP32195591 A JP 32195591A JP H05160133 A JPH05160133 A JP H05160133A
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- semiconductor device
- hole
- plating
- electrode structure
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
Abstract
Description
【０００１】[0001]
【産業上の利用分野】この発明はワイヤボンディングま
たはワイヤレスボンディングが行なわれる半導体装置の
電極構造に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrode structure of a semiconductor device for wire bonding or wireless bonding.
【０００２】[0002]
【従来の技術】ワイヤレスボンディングとは、半導体装
置に形成された突起形状をした電極とパッケージのリー
ドとをワイヤを用いないで接続する方法をいう。従来の
半導体装置の電極の作製方法を図７〜図１２を用いて以
下説明する。2. Description of the Related Art Wireless bonding refers to a method for connecting a projecting electrode formed on a semiconductor device and a package lead without using a wire. A conventional method for manufacturing an electrode of a semiconductor device will be described below with reference to FIGS.
【０００３】図７に示すように、半導体基板１上にアル
ミニウム膜を形成し、パターニングしボンディングパッ
ド３にする。ボンディングパッド３は半導体基板１に形
成された素子と電気的に接続されている。半導体基板１
の全面上に表面保護膜５を形成する。As shown in FIG. 7, an aluminum film is formed on the semiconductor substrate 1 and patterned to form bonding pads 3. The bonding pad 3 is electrically connected to the element formed on the semiconductor substrate 1. Semiconductor substrate 1
A surface protective film 5 is formed on the entire surface of the.
【０００４】図８に示すように、通常の写真製版技術と
エッチング技術を用いて、表面保護膜５にボンディング
パッド３に達するスルーホール７を形成する。As shown in FIG. 8, a through hole 7 reaching the bonding pad 3 is formed in the surface protective film 5 by using a normal photoengraving technique and etching technique.
【０００５】図９に示すように、半導体基板１の全面上
に、真空蒸着あるいはスパッタリングによりＴｉＷ−Ａ
ｕ９を形成する。ＴｉＷ−Ａｕ９は電気メッキを行なう
際の電極となるものである。As shown in FIG. 9, TiW-A is formed on the entire surface of the semiconductor substrate 1 by vacuum deposition or sputtering.
u9 is formed. TiW-Au9 serves as an electrode when performing electroplating.
【０００６】図１０に示すように、半導体基板１の全面
上にフォトレジスト１１を形成し、通常の写真製版技術
を用いて所定のパターニングを施す。As shown in FIG. 10, a photoresist 11 is formed on the entire surface of the semiconductor substrate 1, and a predetermined patterning is performed by using a normal photoengraving technique.
【０００７】図１１に示すように、ＴｉＷ−Ａｕ９を陰
極としてメッキ液中で電気メッキを行ない、ＴｉＷ−Ａ
ｕ９にＡｕ１３を析出させる。Ａｕ１３は表面保護膜５
から突起している。As shown in FIG. 11, TiW-Au9 is used as a cathode to perform electroplating in a plating solution.
Au13 is deposited on u9. Au13 is the surface protection film 5
Protruding from.
【０００８】図１２に示すように、レジスト１１を除去
し、Ａｕ１３の下以外に形成されているＴｉＷ−Ａｕ９
を除去する。これにより従来の半導体装置の電極構造の
作製が完了する。As shown in FIG. 12, the resist 11 is removed, and TiW-Au9 formed except under Au13.
To remove. This completes the fabrication of the conventional electrode structure of the semiconductor device.
【０００９】一方ワイヤボンディングとは半導体装置に
形成された電極とパッケージのリードとをワイヤを用い
て接続する方法をいう。On the other hand, wire bonding refers to a method of connecting the electrodes formed on the semiconductor device and the leads of the package with wires.
【００１０】[0010]
【発明が解決しようとする課題】従来の半導体装置の電
極構造の問題点を図１３〜図１５を用いて以下説明す
る。図１３は表面保護膜５にボンディングパッド３に達
するスルーホール７を形成した状態である。この後半導
体基板１の全面上にメッキ用の電極９となるＴｉＷ−Ａ
ｕを形成するが、図１４に示すように表面保護膜５と下
部電極３との段差である段差部１５全面にＴｉＷ−Ａｕ
９が形成されないことがある。ＴｉＷ−Ａｕ９は真空蒸
着やスパッタリングといった物理的気相成長法で形成し
ているが、この方法では急峻な箇所では被覆性が安定し
ないからである。この状態でＡｕ１３を析出させると、
図１５に示すようにＡｕ１３にボイド１６が発生する。
これはＴｉＷ−Ａｕ９が欠落している箇所からはＡｕ１
３のメッキ成長が行なわれないからである。Problems of the electrode structure of the conventional semiconductor device will be described below with reference to FIGS. FIG. 13 shows a state in which a through hole 7 reaching the bonding pad 3 is formed in the surface protective film 5. After that, TiW-A, which will be the electrode 9 for plating, is formed on the entire surface of the semiconductor substrate 1.
u is formed, but as shown in FIG.
9 may not be formed. This is because TiW-Au9 is formed by a physical vapor deposition method such as vacuum deposition or sputtering, but in this method, the covering property is not stable at a steep portion. When Au13 is deposited in this state,
As shown in FIG. 15, a void 16 is generated in Au 13.
This is Au1 from where TiW-Au9 is missing.
This is because the plating growth of No. 3 is not performed.
【００１１】このボイド１６により電極での抵抗が増大
する。またボイド１６によりＡｕ１３の表面が凸凹とな
り、パッケージのリードとの接合性が悪くなる。The voids 16 increase the resistance at the electrodes. Further, the voids 16 make the surface of the Au 13 uneven, which deteriorates the bondability with the leads of the package.
【００１２】またワイヤボンディングの場合、図１３に
示す状態でボンディングパッド３にワイヤボンディング
する。ワイヤがスルーホール７に入らなければワイヤと
ボンディングパッド３とが接合しないので、スルーホー
ル７の開口面積ひいてはボンディングパッド３の面積を
所定値以上にしなければならない。これが半導体装置の
集積度向上を妨げる１つの原因になっていた。In the case of wire bonding, wire bonding is performed on the bonding pad 3 in the state shown in FIG. If the wire does not enter the through hole 7, the wire and the bonding pad 3 are not joined, so that the opening area of the through hole 7 and thus the area of the bonding pad 3 must be set to a predetermined value or more. This has been one of the causes that hinder the improvement of the integration of semiconductor devices.
【００１３】この発明はかかる従来の問題点を解決する
ためになされたものである。請求項１に記載の発明の目
的は、電極にボイドの発生を防ぐことができる半導体装
置の電極構造を提供することである。The present invention has been made to solve the conventional problems. An object of the invention described in claim 1 is to provide an electrode structure of a semiconductor device capable of preventing the occurrence of voids in the electrode.
【００１４】請求項２に記載の発明の目的はボンディン
グパッドの面積を小さくすることができる半導体装置の
電極構造を提供することである。An object of the invention described in claim 2 is to provide an electrode structure of a semiconductor device which can reduce the area of a bonding pad.
【００１５】[0015]
【課題を解決するための手段】請求項１に記載の半導体
装置の電極構造は、半導体基板上に形成された素子と電
気的に接続された下部電極と、素子および下部電極を覆
うように形成され下部電極に達する貫通孔を有する表面
保護膜と、貫通孔内に形成され下部電極と電気的に接続
された中間電極と、中間電極および表面保護膜上に形成
されたメッキ用電極と、メッキ用電極上に形成された上
部電極とを備えている。An electrode structure of a semiconductor device according to claim 1 is formed so as to cover a lower electrode electrically connected to an element formed on a semiconductor substrate and the element and the lower electrode. A surface protection film having a through hole reaching the lower electrode, an intermediate electrode formed in the through hole and electrically connected to the lower electrode, a plating electrode formed on the intermediate electrode and the surface protection film, and a plating And an upper electrode formed on the working electrode.
【００１６】請求項２に記載の半導体装置の電極構造
は、半導体基板に形成された素子と電気的に接続された
下部電極と、素子および下部電極を覆うように形成さ
れ、下部電極に達する貫通孔を有する表面保護膜と、貫
通孔内に形成され下部電極と電気的に接続された中間電
極と、中間電極および表面保護膜上に形成されワイヤが
ボンディングされる上部電極と、を備えている。According to another aspect of the electrode structure of the semiconductor device, a lower electrode electrically connected to the element formed on the semiconductor substrate, and a penetrating portion formed to cover the element and the lower electrode and reaching the lower electrode. A surface protective film having a hole, an intermediate electrode formed in the through hole and electrically connected to the lower electrode, and an upper electrode formed on the intermediate electrode and the surface protective film to which a wire is bonded are provided. ..
【００１７】[0017]
【作用】請求項１に記載の発明は、中間電極および表面
保護膜をメッキ用電極形成面にしている。したがって、
メッキ用電極をメッキ用電極形成面全面に形成すること
が可能となる。According to the first aspect of the invention, the intermediate electrode and the surface protective film are used as the plating electrode formation surface. Therefore,
It becomes possible to form the plating electrode on the entire surface on which the plating electrode is formed.
【００１８】請求項２に記載の発明は、貫通孔上に形成
された上部電極でワイヤがボンディングされる。このた
め貫通孔の大きさをワイヤが入るような大きさにする必
要がなくなる。したがって、貫通孔の開口面積ひいては
ボンディングパッドの面積を小さくできる。According to the second aspect of the present invention, the wire is bonded by the upper electrode formed on the through hole. Therefore, it is not necessary to make the size of the through hole large enough to receive the wire. Therefore, the opening area of the through hole and thus the area of the bonding pad can be reduced.
【００１９】[0019]
【実施例】（第１実施例）この発明に従った半導体装置
の電極構造の第１実施例を図１〜図３を用いて説明す
る。半導体基板１にはボンディングパッド３が形成され
ている。ボンディングパッド３は半導体基板１上に形成
された素子と電気的に接続されている。半導体基板１の
全面に表面保護膜５が形成されている。表面保護膜５に
はボンディングパッド３に達するスルーホール７が形成
されている。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) A first embodiment of the electrode structure of a semiconductor device according to the present invention will be described with reference to FIGS. Bonding pads 3 are formed on the semiconductor substrate 1. The bonding pad 3 is electrically connected to the element formed on the semiconductor substrate 1. A surface protective film 5 is formed on the entire surface of the semiconductor substrate 1. Through holes 7 reaching the bonding pads 3 are formed in the surface protective film 5.
【００２０】図２に示すように、スルーホール７に選択
ＣＶＤ法を用いてタングステン１７を形成した。タング
ステンを選択成長させる技術は、“T. Moriya etal, Te
chnical Digest 1983, IEEE International Electron D
evice Meeting, P.550”に開示されている。なおＣｕを
選択成長させてもよい。Ｃｕを選択成長させる技術は、
“N. Awaya etal, 1990 Proceeding IEEE VLSI Multile
vel InterconnectionConference, P.254 ”に開示され
ている。As shown in FIG. 2, tungsten 17 was formed in the through hole 7 by using the selective CVD method. The technology for selective growth of tungsten is described in “T. Moriya et al, Te
chnical Digest 1983, IEEE International Electron D
evice Meeting, P.550 ”. Note that Cu may be selectively grown. The technology for selectively growing Cu is
“N. Awaya et al, 1990 Proceeding IEEE VLSI Multile
vel Interconnection Conference, P.254 ".
【００２１】タングステン１７の厚みを表面保護膜５の
厚みと同じにした。したがって、メッキ用電極形成面で
あるタングステン１７表面および表面保護膜５表面はほ
ぼ平坦になった。The tungsten 17 has the same thickness as the surface protective film 5. Therefore, the surface of the tungsten 17 and the surface of the surface protective film 5, which are the surfaces for forming the plating electrodes, became substantially flat.
【００２２】図３に示すように真空蒸着またはスパッタ
リングを用いてメッキ用の電極９となるＴｉＷ−Ａｕを
形成した。メッキ用電極形成面がほぼ平坦なのでＴｉＷ
−Ａｕはメッキ用電極形成面全面に形成された。メッキ
用電極９の材料としては他にＣｒ−Ｃｕ−Ａｕ、Ｔｉ−
Ｐｔ−Ａｕなどがある。またこの実施例ではメッキ用電
極を１層構造にしているが、多層構造にしてもよい。As shown in FIG. 3, TiW-Au to be the electrode 9 for plating was formed by using vacuum deposition or sputtering. The surface on which the electrode for plating is formed is almost flat, so TiW
-Au was formed on the entire surface on which the plating electrode was formed. Other materials for the plating electrode 9 include Cr-Cu-Au and Ti-
Pt-Au and the like. Although the plating electrode has a single-layer structure in this embodiment, it may have a multi-layer structure.
【００２３】次に従来と同じ方法を用いてＡｕ１３を析
出させた。ＴｉＷ−Ａｕ９が欠落なく形成されているの
でＡｕ１３にはボイドが発生しなかった。Next, Au13 was deposited by the same method as the conventional method. Since TiW-Au9 was formed without omission, no void was generated in Au13.
【００２４】（第２実施例）この発明の第２の実施例を
図４〜図６を用いて説明する。図４までの工程はこの発
明の第１実施例である図２までの工程と同じである。図
５に示すようにスパッタリングを用いて半導体基板１全
面にアルミニウム膜を形成し、所定のパターニングを施
しアルミニウム電極１９にした。そして図６に示すよう
にこのアルミニウム電極１９にワイヤ２１をボンディン
グした。(Second Embodiment) A second embodiment of the present invention will be described with reference to FIGS. The steps up to FIG. 4 are the same as the steps up to FIG. 2 which is the first embodiment of the present invention. As shown in FIG. 5, an aluminum film was formed on the entire surface of the semiconductor substrate 1 by sputtering, and a predetermined patterning was performed to form an aluminum electrode 19. Then, as shown in FIG. 6, a wire 21 was bonded to the aluminum electrode 19.
【００２５】第１実施例および第２実施例においてはス
ルーホール７にタングステン１７を完全に埋め込んでい
るが、この発明においてはこれに限定されるわけではな
く完全に埋め込まれてなくてもよい。すなわち第１実施
例ではＴｉＷ−Ａｕ９が欠落なくメッキ用電極形成面全
面に形成されるならば、タングステン１７はスルーホー
ル７を完全に埋め込んでなくてもよい。またアルミニウ
ム電極１９とワイヤ２１との接合性に問題がなければ、
タングステン１７はスルーホール７に完全に埋め込まれ
てなくてもよい。In the first and second embodiments, the tungsten 17 is completely buried in the through hole 7, but the present invention is not limited to this, and it may not be completely buried. That is, in the first embodiment, if the TiW-Au 9 is formed on the entire surface of the plating electrode formation surface without omission, the tungsten 17 may not completely fill the through hole 7. If there is no problem in the bondability between the aluminum electrode 19 and the wire 21,
The tungsten 17 may not be completely embedded in the through hole 7.
【００２６】第１実施例におよび第２実施例においては
選択ＣＶＤ法を用いてスルーホール７を埋め込んでいる
が、この発明においてはこれに限定されるわけではな
く、スルーホール７を埋め込むことができる技術なら他
の技術でもよい。In the first embodiment and the second embodiment, the through hole 7 is filled by using the selective CVD method, but the present invention is not limited to this, and the through hole 7 may be filled. Any other technology may be used as long as it is possible.
【００２７】[0027]
【発明の効果】請求項１に記載の発明によれば、メッキ
用電極を欠落なく形成できるので、上部電極にボイドが
発生しない。したがってボイドが原因で電極の抵抗が増
大したり、パッケージのリードとの接合性が悪化すると
いうことはなくなる。According to the invention described in claim 1, since the plating electrode can be formed without omission, no void is generated in the upper electrode. Therefore, the void does not increase the resistance of the electrode or deteriorate the bondability with the lead of the package.
【００２８】請求項２に記載の発明によれば、貫通孔の
開口面積ひいてはボンディングパッドの面積を小さくす
ることができるので、半導体装置の集積度を向上させる
ことが可能となる。According to the second aspect of the present invention, since the opening area of the through hole and thus the area of the bonding pad can be reduced, it is possible to improve the integration degree of the semiconductor device.
【図１】この発明に従った半導体装置の電極構造の第１
実施例の製造方法の第１工程を示す断面図である。FIG. 1 is a first electrode structure of a semiconductor device according to the present invention.
It is sectional drawing which shows the 1st process of the manufacturing method of an Example.
【図２】この発明に従った半導体装置の電極構造の第１
実施例の製造方法の第２工程を示す断面図である。FIG. 2 shows a first electrode structure of a semiconductor device according to the present invention.
It is sectional drawing which shows the 2nd process of the manufacturing method of an Example.
【図３】この発明に従った半導体装置の電極構造の第１
実施例の製造方法の第３工程を示す断面図である。FIG. 3 shows a first electrode structure of a semiconductor device according to the present invention.
It is sectional drawing which shows the 3rd process of the manufacturing method of an Example.
【図４】この発明に従った半導体装置の電極構造の第２
実施例の製造方法の第１工程を示す断面図である。FIG. 4 is a second electrode structure of a semiconductor device according to the present invention.
It is sectional drawing which shows the 1st process of the manufacturing method of an Example.
【図５】この発明に従った半導体装置の電極構造の第２
実施例の製造方法の第２工程を示す断面図である。FIG. 5 is a second electrode structure of a semiconductor device according to the present invention.
It is sectional drawing which shows the 2nd process of the manufacturing method of an Example.
【図６】この発明に従った半導体装置の電極構造の第２
実施例の製造方法の第３工程を示す断面図である。FIG. 6 shows a second electrode structure of a semiconductor device according to the present invention.
It is sectional drawing which shows the 3rd process of the manufacturing method of an Example.
【図７】従来の半導体装置の電極構造の製造方法の第１
工程を示す断面図である。FIG. 7 is a first method of manufacturing a conventional electrode structure of a semiconductor device.
It is sectional drawing which shows a process.
【図８】従来の半導体装置の電極構造の製造方法の第２
工程を示す断面図である。FIG. 8 is a second manufacturing method of a conventional electrode structure of a semiconductor device.
It is sectional drawing which shows a process.
【図９】従来の半導体装置の電極構造の製造方法の第３
工程を示す断面図である。FIG. 9 is a third conventional method for manufacturing an electrode structure of a semiconductor device.
It is sectional drawing which shows a process.
【図１０】従来の半導体装置の電極構造の製造方法の第
４工程を示す断面図である。FIG. 10 is a cross-sectional view showing a fourth step of the conventional method for manufacturing the electrode structure of the semiconductor device.
【図１１】従来の半導体装置の電極構造の製造方法の第
５工程を示す断面図である。FIG. 11 is a sectional view showing a fifth step of the conventional method for manufacturing the electrode structure of the semiconductor device.
【図１２】従来の半導体装置の電極構造の製造方法の第
６工程を示す断面図である。FIG. 12 is a sectional view showing a sixth step of the conventional method for manufacturing the electrode structure of the semiconductor device.
【図１３】従来の半導体装置の電極構造の問題点を説明
するための図であり、電極構造の製造方法の第１工程を
示す断面図である。FIG. 13 is a diagram for explaining the problem of the electrode structure of the conventional semiconductor device, and a cross-sectional view showing the first step of the method for manufacturing the electrode structure.
【図１４】従来の半導体装置の電極構造の問題点を説明
するための図であり、電極構造の製造方法の第２工程を
示す断面図である。FIG. 14 is a diagram for explaining the problem of the electrode structure of the conventional semiconductor device, and a cross-sectional view showing a second step of the method for manufacturing the electrode structure.
【図１５】従来の半導体装置の電極構造の問題点を説明
するための図であり、電極構造の製造方法の第３工程を
示す断面図である。FIG. 15 is a diagram for explaining the problem of the electrode structure of the conventional semiconductor device, and a cross-sectional view showing the third step of the method for manufacturing the electrode structure.
３ ボンディングパッド ５ 表面保護膜 ７ スルーホール ９ ＴｉＷ−Ａｕ １３ Ａｕ １７ タングステン １９ アルミニウム電極 3 Bonding Pad 5 Surface Protective Film 7 Through Hole 9 TiW-Au 13 Au 17 Tungsten 19 Aluminum Electrode
Claims (2)
に接続された下部電極と、 前記素子および前記下部電極を覆うように形成され、前
記下部電極に達する貫通孔を有する表面保護膜と、 前記貫通孔内に形成され、前記下部電極と電気的に接続
された中間電極と、 前記中間電極上および前記表面保護膜上に形成されたメ
ッキ用電極と、 前記メッキ用電極上に形成された上部電極と、 を備えた半導体装置の電極構造。1. A lower electrode electrically connected to an element formed on a semiconductor substrate, and a surface protective film having a through hole formed to cover the element and the lower electrode and having a through hole reaching the lower electrode. An intermediate electrode formed in the through hole and electrically connected to the lower electrode; a plating electrode formed on the intermediate electrode and the surface protective film; and an plating electrode formed on the plating electrode. And an upper electrode, and an electrode structure of a semiconductor device including.
置の電極構造であって、 半導体基板に形成された素子と電気的に接続された下部
電極と、 前記素子および前記下部電極を覆うように形成され、前
記下部電極に達する貫通孔を有する表面保護膜と、 前記貫通孔内に形成され、前記下部電極と電気的に接続
された中間電極と、 前記中間電極上におよび前記表面保護膜上に形成され、
ワイヤがボンディングされる上部電極と、 を備えた半導体装置の電極構造。2. An electrode structure of a semiconductor device to be wire-bonded, comprising: a lower electrode electrically connected to an element formed on a semiconductor substrate; a lower electrode formed to cover the element and the lower electrode; A surface protective film having a through hole reaching the lower electrode, an intermediate electrode formed in the through hole and electrically connected to the lower electrode, and formed on the intermediate electrode and on the surface protective film. ,
An electrode structure of a semiconductor device comprising an upper electrode to which a wire is bonded, and.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3321955A JPH05160133A (en) | 1991-12-05 | 1991-12-05 | Electrode structure of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3321955A JPH05160133A (en) | 1991-12-05 | 1991-12-05 | Electrode structure of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05160133A true JPH05160133A (en) | 1993-06-25 |
Family
ID=18138297
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3321955A Withdrawn JPH05160133A (en) | 1991-12-05 | 1991-12-05 | Electrode structure of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05160133A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003224158A (en) * | 2002-01-25 | 2003-08-08 | Texas Instruments Inc | Flip chip for substrate assembly with no bump and polymer layer |
| US6696357B2 (en) | 2001-08-30 | 2004-02-24 | Renesas Technology Corporation | Method for manufacturing semiconductor integrated circuit devices using a conductive layer to prevent peeling between a bonding pad and an underlying insulating film |
| KR100482364B1 (en) * | 1997-12-31 | 2005-09-05 | 삼성전자주식회사 | Multilayer pad of semiconductor device and its manufacturing method |
| CN104779149A (en) * | 2014-01-15 | 2015-07-15 | 无锡华润上华半导体有限公司 | Manufacturing method of metal electrode of semiconductor device |
| US10418336B2 (en) | 2017-03-14 | 2019-09-17 | Fuji Electric Co., Ltd. | Manufacturing method of semiconductor device and semiconductor device |
| CN113219680A (en) * | 2021-05-08 | 2021-08-06 | 中国科学院半导体研究所 | Adjustable delay line chip and manufacturing method thereof |
-
1991
- 1991-12-05 JP JP3321955A patent/JPH05160133A/en not_active Withdrawn
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100482364B1 (en) * | 1997-12-31 | 2005-09-05 | 삼성전자주식회사 | Multilayer pad of semiconductor device and its manufacturing method |
| US6696357B2 (en) | 2001-08-30 | 2004-02-24 | Renesas Technology Corporation | Method for manufacturing semiconductor integrated circuit devices using a conductive layer to prevent peeling between a bonding pad and an underlying insulating film |
| JP2003224158A (en) * | 2002-01-25 | 2003-08-08 | Texas Instruments Inc | Flip chip for substrate assembly with no bump and polymer layer |
| JP4698125B2 (en) * | 2002-01-25 | 2011-06-08 | テキサス インスツルメンツ インコーポレイテッド | Flip chip for substrate assembly without bumps and polymer layers |
| CN104779149A (en) * | 2014-01-15 | 2015-07-15 | 无锡华润上华半导体有限公司 | Manufacturing method of metal electrode of semiconductor device |
| US10418336B2 (en) | 2017-03-14 | 2019-09-17 | Fuji Electric Co., Ltd. | Manufacturing method of semiconductor device and semiconductor device |
| CN113219680A (en) * | 2021-05-08 | 2021-08-06 | 中国科学院半导体研究所 | Adjustable delay line chip and manufacturing method thereof |
| CN113219680B (en) * | 2021-05-08 | 2023-08-15 | 中国科学院半导体研究所 | Adjustable delay line chip and manufacturing method thereof |
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Legal Events
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| A300 | Withdrawal of application because of no request for examination |
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