JPH05153566A - Vertical drive pulse generating circuit - Google Patents

Abstract

PURPOSE:To generate an accurate extract pulse by generating an extract pulse generating timing earlier by one period of a clock signal of a frequency divider circuit than a regular generating timing of a character signal. CONSTITUTION:A video signal from a terminal 9 is subject to synchronization separation by a synchronizing separator circuit 10 and the result is locked to a horizontal synchronizing signal by a phase comparator circuit 11, a voltage controlled oscillator 12 and a frequency divider circuit 13. Then a frequency (2 X horizontal synchronizing signal frequency) from the circuit 13 is fed to a clock terminal of the frequency divider circuit 15, in which the clock signal is frequency-divided to generate a vertical drive pulse whose frequency is nearly 60Hz. The circuit 15 outputs a vertical drive pulse in response to the resetting. In the case of extracting a character signal, since a front ridge of the character signal cannot be extracted owing to a delay time of the circuit or the like depending on the reset timing of the circuit 15, it is prevented that the detection timing is extracted earlier by one period of the clock signal of the circuit 15.

Description

Detailed Description of the Invention

[0001]

The present invention relates to a TV (television).
The present invention relates to a count-down type vertical drive pulse generation circuit used in a receiver, and more particularly to a vertical drive pulse generation circuit suitable for use in a TV receiver that receives a character broadcast or a caption broadcast.

[0002]

2. Description of the Related Art A TV receiver for receiving a teletext signal is known. FIG. 2 shows such a TV receiver, and a video signal including a character signal can be obtained at the output end of the detection circuit (1). The Y / C processing circuit (2) processes the luminance signal (Y) and the color signal (C) in the video signal and applies them to the switching circuit (3). Since the character signal exists at a specific position during the vertical blanking period in the video signal, a pulse for extracting the character signal is generated by the pulse generation circuit (4). Then, the sampling circuit (5) extracts the character signal by the sampling pulse. The extracted character signal is decoded by the decoding circuit (6) and the character signal to be displayed is applied to the switching circuit (3). As a result, an image signal in which characters are displayed is obtained at the output terminal (7) of the switching circuit (3).

[0003]

However, the sampling pulse generation circuit (4) of FIG. 2 is unique to the PLL circuit,
Since the frequency divider circuit is required, the number of elements becomes huge, which is a problem. Therefore, a method for generating a sampling pulse with a simple configuration has been desired.

[0004]

The present invention has been made in view of the above-mentioned points, and a signal corresponding to a vertical synchronizing signal in a video signal is applied as a reset signal, and a horizontal synchronizing signal in the video signal is applied. In a vertical drive pulse generation circuit that generates a vertical drive pulse by using a frequency divider circuit to which a signal corresponding to the above is applied as a clock signal, the timing for returning the state of the vertical drive pulse to the character existing during the blanking period of the video signal It is characterized in that the signal generation timing is determined earlier by one cycle of the clock signal.

[0005]

According to the present invention, the sampling pulse is created using the terminal for the vertical driving pulse generated from the vertical deflection frequency dividing circuit built in the Y / C processing circuit. Since the sampling pulse is generated earlier than the normal generation timing of the character signal by one cycle of the clock signal of the frequency dividing circuit, the sampling pulse can be accurately created.

[0006]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows the principle of the present invention.
A sampling pulse is created in the C processing circuit (8) and applied to the sampling circuit (5). FIG. 3 shows Y /
2 shows a sampling pulse generation circuit in the C processing circuit (8), in which a video signal from a terminal (9) is a sync separation circuit (1
0), the synchronization is separated. Phase comparison circuit (11), VCO
(Voltage controlled oscillator) (12) and frequency divider (13)
A PLL circuit ( 14 ) is configured and locked to the horizontal sync signal from the sync separation circuit (10). Then, the frequency dividing circuit (1
The signal of frequency 2f _H (f _H is the horizontal synchronizing signal frequency) from 3) is applied to the clock terminal of the frequency dividing circuit (15).
The frequency divider circuit (15) divides the clock signal to generate about 60H.
Generate a vertical drive pulse for z. Vertical separation circuit (16)
Extracts the vertical synchronizing signal and applies the extracted vertical synchronizing signal as a reset signal to the frequency dividing circuit (15).
The frequency divider circuit (15) outputs a vertical drive pulse to the outside in response to the reset.

Now, the character signal to be extracted is shown at 14th H (H is 1 horizontal period) shown in FIGS. 4A and 4B (277H).
4), and the reset timing of the frequency dividing circuit (15) is set to the position of 1/4 of the 4Hth, as shown in FIG. In this case, the terminal (17) of the frequency dividing circuit (15) has the configuration shown in FIG.
The signal of (c) and the signal of FIG. 4 (d) are generated at the terminal (18). The signal at the 14th H in FIG. 4A is located at 9.5H from the reset timing,
If the sampling pulse is generated from the timing of 9.5H, the leading edge of the character signal may not be sampled due to the delay time of the circuit. Therefore, in the present invention, the detection timing is 0.5H earlier than the regular timing. Here, 0.5H is 1 of the clock signal of the frequency dividing circuit (15).
This is a cycle, and this timing can be easily created.

On the other hand, the discriminating circuit (19) performs field discrimination based on the horizontal synchronizing signal from the synchronizing separating circuit (10) and the vertical synchronizing signal from the vertical separating circuit (16), and the signal of FIG. Switch (20) when it arrives
Indicates the terminal (17), and the switch (20) selects the terminal (18) when the signal of FIG. Generally, it is sufficient to transmit only the rising timing information of the vertical drive pulse to the vertical deflection system circuit subsequent to the frequency dividing circuit (15). Therefore, in the present invention, the sampling pulse of the character signal to be extracted is created by utilizing the falling timing (state restoration timing) of the vertical drive pulse which has not been used until now. Switch (20)
Is applied to the first M · M (mono-multivibrator) (21) that operates at the falling edge, and its pulse width is waveform-shaped to a width of 1H suitable for extracting a character signal. The waveform-shaped sampling pulse is normalized by the clock signal of frequency 2f _{H in} the synchronizing circuit (22).

Therefore, the sampling circuit (5) is shown in FIG.
As shown in (g) and (g), a good sampling pulse can be obtained for extracting the character signals of the 14th and 277th H. on the other hand,
The output vertical drive pulse of the switch (20) is the second M · M
At (23), the pulse width is shaped into a pulse width necessary for driving the circuit at the subsequent stage. For example, as shown in FIG. 4 (e), it is applied to the sawtooth oscillator (24) and the vertical output circuit (25).

Therefore, according to the circuit of FIG. 3, the character signal extraction pulse can be easily created by adding the information for character signal extraction to the vertical drive pulse. Although the above description has been made with respect to the 14th (277th) character signal, any character signal can be extracted by changing the timing for returning the state of the vertical drive pulse.

FIG. 5 shows a specific circuit example of the frequency dividing circuit (15) shown in FIG. 3, in which a vertical synchronizing signal is supplied to the terminal A and a terminal B is supplied.
Is applied with a clock signal, and a vertical drive pulse is generated at the terminal C. 9H for the output of the first AND gate (26)
The signal which becomes "H" level at the second AND gate (2
At the output of 7), a signal that becomes "H" level at 9.5H is output. The third AND gate (28) is for self-resetting at 296H when it is not reset from the outside. As shown in FIG. 5, in the actual frequency dividing circuit, the vertical drive pulse is generated from one terminal C. The terminal C originally exists as a pin of the IC when the Y / C processing circuit (8) of FIG. 1 is integrated into an IC. Therefore, even if the function of the present invention is added to the existing Y / C processing circuit (2) in FIG. 2, the number of IC pins is not increased.

[0012]

As described above, according to the present invention, it is possible to provide a vertical drive pulse generating circuit for generating a vertical drive pulse on which information for extracting a character signal is superimposed. Therefore, the sampling pulse of the character signal can be created by a simple circuit.

[Brief description of drawings]

FIG. 1 is a block diagram showing a principle diagram of the present invention.

FIG. 2 is a block diagram showing a conventional TV receiver capable of receiving teletext.

FIG. 3 is a diagram showing a vertical drive pulse generation circuit of the present invention.

FIG. 4 is a waveform diagram for explanation of FIG.

5 is a specific circuit diagram of the frequency dividing circuit (15) of FIG.

[Explanation of symbols]

 (15) Frequency divider (20) Switch (21) 1st M · M (22) Synchronous circuit

Claims (1)

[Claims] 1. A vertical drive using a frequency divider circuit in which a signal corresponding to a vertical synchronizing signal in a video signal is applied as a reset signal and a signal in accordance with a horizontal synchronizing signal in the video signal is applied as a clock signal. In a vertical drive pulse generation circuit for generating a pulse, the state recovery timing of the vertical drive pulse from the generation timing of the character signal existing during the blanking period of the video signal,
A vertical drive pulse generation circuit characterized in that the clock signal is determined earlier by one cycle or more.