JPH05143520A - Dma transfer system - Google Patents

Abstract

PURPOSE:To improve transfer efficiency by temporarily interrupting transfer when a data error occurs during DMS transfer and restarting the correction of data so as to avoid necessity for re-executing DMA transfer from the first. CONSTITUTION:A memory address register 13 stores an address for the memory 3 during DMA transfer. When an error flip-flop 12 is by set by the detection of the data error by a parity checker 11, a DMA signal 51 for a microprocessor 1 is interrupted, a gate 15 is closed and also the data error is reported to a DMA controller 2 and an I/O port 4 to temporarily interrupt DMA transfer. The microprocessor 1 confirms the DMA signal and a TC signal and knows data error occurrence to start a compensation processing. At the time of transfer from the memory to I/O port, the memory address register reads out data from the memory 3. At the time of transfer from the I/O port to the memory 3, data is read from a data register 19 to be written in the memory 3 based on an address register 18.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DMA transfer system,
The present invention relates to a DMA transfer method which sometimes has a data error processing function.

[0002]

2. Description of the Related Art In conventional DMA transfer, when a data error is detected during data transfer, the DMA transfer process is interrupted,
The microprocessor again performs initialization for DMA transfer, and then repeats data transfer from the beginning by DMA transfer.

[0003]

DISCLOSURE OF THE INVENTION Conventional DMA described above
In the transfer, if a data error is detected during the transfer, the data transfer process is interrupted. Therefore, the transfer efficiency is deteriorated when the retransfer process is performed as the data error detection of the transfer data reaches the final part. there were.

[0004]

According to the DMA transfer method of the present invention, a memory address register for holding an address sent to a memory is set during a DMA transfer, and a data error is set when a data error is detected during the DMA transfer. An error flip-flop that is reset when the data error correction process is completed, the output of the memory address register, and the CPU
And a multiplexer for switching the address bus of the I / O port, and in the I / O port, an address register and an I / O for holding an address to store data at the time of data transfer from the memory to the I / O port. When data is transferred from the port to the memory, a data register for holding the data transferred to the memory is provided, and when a data error occurs, the DMA transfer is temporarily suspended, the data is corrected, and then restarted. To do.

[0005]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of an embodiment of the present invention.

In FIG. 1, 1 is a microprocessor,
2 is a DMA controller, 3 is a memory, 4 is an I / O port, 100 is an address bus, 200 is a data bus, 11
Is a parity checker for detecting a data error on the database 200, 12 is an error flip-flop that is set when the parity checker 11 detects a data error, and is reset after the data error correction processing, and 13 is for a memory during DMA transfer. A memory address register for holding an address, 14 is a multiplexer for switching the output of the memory address register 13 and the address bus of the microprocessor 1, and 15 is a DMA.
Gates for controlling the address bus output from the controller 2, 16 and 17 are AND gates, 18 is a memory 3
From the I / O port 4 to the I / O port 4, an address register for holding an address to store the data, and 19 is a data register for holding the data transferred to the memory 3 at the time of the transfer from the I / O port 4 to the memory 3.

Reference numeral 51 is a DMA signal indicating that the DMA transfer is in progress, 52 is an EXT signal indicating the transfer direction during the DMA transfer,
53 is a TC signal indicating the end of the DMA transfer, 54 is an output of the error flip-flop 12, and an ERR signal indicating that a data error has occurred during the DMA transfer, and 55 is when the microprocessor 1 reads from or writes to the memory 3. The output MMAC signal 56 is an RST signal for resetting the error flip-flop 12 when the data error correction processing is completed.

A normal DMA transfer process is started when the microprocessor 1 initializes the DMA controller 2. At this time, the DMA signal 51 becomes active to inform the microprocessor 1 that the DMA transfer is in progress, and the EXT signal 52 which is a signal indicating the transfer direction of the DMA transfer is also sent out.

Each time an address for the memory 3 is sent from the DMA controller 2 via the address bus 100 during the DMA transfer, this address is stored in the memory address register 13. Further, the data on the data bus 200 which is the transfer data is the parity checker 11
Constantly monitors for data errors. When the transfer is completed by the transfer length at the time of initialization, the RC signal 53 is transferred from the DMA controller 2 to the microprocessor 1.
Sent to.

Here, a processing method when a data error is detected during DMA transfer will be described.

When the parity checker 11 detects a data error, the error flip-flop 12 is set. The gate 15 is closed by the ERR signal 54 which is the output signal of the error flip-flop 12, and the DMA signal 51 is closed to the microprocessor 1 by being input to the AND gate 17.

At the same time, the ERR signal 54 is also input to the DMA controller 2 and the I / O port 4, and when it is notified that a data error has occurred during the DMA transfer, the DMA controller 2 suspends the DMA transfer. I / O port 4 receives I / O from memory 3 when ERR54 signal is input.
When the data is being transferred to the port 4, the address that should have stored the data when the data error occurs is temporarily held in the address register 18. If data is being transferred from the I / O port 4 to the memory 3, the data transferred to the memory 3 is temporarily held in the data register 19 when a data error occurs.

The microprocessor 1 has an AND gate 17
If it is confirmed that the output of is inactive and the TC53 signal is also inactive, it is known that a data error has occurred during the DMA transfer, the EXT signal 52 is confirmed, the transfer direction of the previous DMA transfer is known, Start the data correction process.

First, when the transfer direction is from the memory to the I / O port 4, the microprocessor 1 acquires the erroneous data from the memory 3 again in order to obtain the error data from the memory 3.
Activate the MMAC signal 55 indicating a read request,
When input to the AND gate 16, the multiplexer 14 is switched by the output of the AND gate 16 and the address in the memory address register 13 which is the address when the data error occurs is sent to the address bus 100 and transmitted to the memory 3.

As a result, the microprocessor 1 obtains the data when the error occurs. Next, when the MMAC signal 55 is made inactive to send the obtained data to the I / O port 4, the multiplexer 14 is switched, and the microprocessor 1 obtains the I / O port 4 from the address and the memory 3. Sent data.

Thereafter, the microprocessor 1 sets the RST signal 56 and resets the error flip-flop 12 to notify that the correction processing of the data is completed, avoid the temporary interruption of the DMA transfer, and restart the DMA transfer. Report to controller 2.

When the transfer direction is from the I / O port 4 to the memory 3, the microprocessor 1 obtains the error data from the data register 19 in the I / O port 4 again. Next, an MMAC signal 5 indicating a memory write request for transmitting the obtained data to the memory 3
When 5 is activated and input to AND gate 16,
The multiplexer 14 is switched by the output of the AND gate 16, and the address in the memory address register 13 which is the address when the data error occurs is transmitted to the memory 3 via the address bus 100 and the data previously obtained from the I / O port 4 is transmitted. Is written in the memory 3.

Thereafter, the microprocessor 1 sets the RST signal 56 and resets the error flip-flop 12 to notify that the correction processing of the data is completed, and avoids the temporary interruption of the DMA transfer and restarts the DMA controller. Report to 2.

[0019]

As described above, according to the present invention, the DMA
When a data error occurs during the transfer, the data transfer efficiency can be improved by temporarily suspending the data transfer, restarting the DMA transfer after performing the correction processing of the data, without stopping the data transfer. is there.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

[Explanation of symbols]

 1 Microprocessor 2 DMA Controller 3 Memory 4 I / O Port 11 Parity Checker 12 Error Flip Flop 13 Memory Address Register 14 Multiplexer 15 Gate 16 AND Gate 17 AND Gate 18 Address Register 19 Data Register

Claims (1)

[Claims] 1. A memory address register that holds an address to be sent to a memory during a DMA transfer, and is set when a data error is detected during the DMA transfer, and is reset when a data error correction process is completed. It has an error flip-flop, a multiplexer for switching the output of the memory address register and the address bus of the CPU, and stores data in the I / O port at the time of data transfer from the memory to the I / O port. An address register that holds the address to be stored and a data register that holds the data transferred to the memory at the time of data transfer from the I / O port to the memory are provided, and when a data error occurs, the DMA transfer is temporarily suspended, A DMA transfer method characterized by restarting after correcting data.