JP2871171B2 - Microcomputer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microcomputer, and more particularly to a microcomputer having a built-in direct memory access (DMA) controller.

[0002]

2. Description of the Related Art In recent years, microcomputers without demands for higher functions and higher speeds include an interrupt controller, a timer,
Various peripheral units such as a counter and a serial data communication device are built in. Data transfer between such a peripheral unit and the memory is required. However, if such data transfer is executed by a central processing unit (CPU) through software (program), data processing efficiency is reduced.
Therefore, the data transfer between the peripheral unit and the memory is
It is common to have it executed by a DMA controller instead of a PU.

A DMA controller has an address register for storing address information of a memory to be accessed, a terminal counter register for storing the number of data to be transferred, and a control for storing control data such as a data transfer direction and a memory address update direction. The CPU has registers, in which necessary information is initialized by the CPU. When the peripheral unit requests data transfer from the DMA controller, the DMA controller obtains the right to use the bus from the CPU and executes data transfer between the peripheral unit and the memory. When the data transfer is completed, the DMA controller passes the right to use the bus to the CPU and waits for the next data transfer request. When the number of transferred data reaches the number of data set in the terminal counter register, the DMA controller issues an interrupt request to the CPU. Based on the request, the CPU executes an interrupt processing routine, resets necessary information to the above registers,
The next data transfer is permitted.

[0004]

The DMA controller is in a data transfer prohibited state during a period from when an interrupt request is issued to the CPU to when information required for the next data transfer is reset. The peripheral unit may issue a data transfer request during this prohibition period. Such a request will not be accepted and will be suspended. The length of the data transfer prohibition period depends on the priority of an interrupt request from the DMA controller and the number of transfer channels supported by the controller. May issue a data transfer request again during the suspension period. For example, in a serial data receiving device, a data transfer request is issued every time data of a predetermined number of bits is received, but when the reception of the next data is completed before the previous data is transferred to the memory, the previous data is destroyed. As a result, a reception overrun error occurs. As another example, in a serial data receiving apparatus, data to be transmitted next is not transferred and a transmission underrun error occurs. The reception overrun error and the transmission underrun error are more likely to occur when the speed of the serial line is increased. Even if the number of stages of the receive / transmit data buffer is increased, an error still occurs if data transfer is suspended more than the number of stages, and if the number of buffer stages is increased enough to meet a high-speed serial line, the hardware will increase. Bring.

Accordingly, it is an object of the present invention to provide a microcomputer having a DMA controller in which the period from the end of the current data transfer execution state to the start of the next data transfer execution state is substantially eliminated.

Another object of the present invention is to provide a microcomputer having a built-in DMA controller capable of preventing occurrence of an error due to suspension of a data transfer request from a peripheral unit.

Another object of the present invention is to provide a microcomputer having a built-in DMA controller capable of supporting a serial data communication device for a high-speed serial line.

[0008]

A microcomputer according to the present invention issues a DMA transfer request signal, issues a DMA transfer end instruction signal when processing is completed, and outputs a DMA transfer end instruction signal when the processing is completed or when a state saving instruction signal is detected. Peripheral circuit including state saving storage means for saving and storing the internal state, and first, second, and third three units including a DMA control information storage unit including at least DMA transfer continuation instruction information and a DMA transfer count storage unit.
DMA control storage means, and when the DMA transfer request signal is detected, DMA transfer is performed between the peripheral circuit and the memory, and DMA in the second DMA control storage means is performed.
The value of the number-of-transfers storage unit is updated, and either the result of the update becomes a predetermined value or the DMA transfer end instruction signal is detected, and the DMA transfer in the second DMA control storage means is performed. If the continuation instruction information is valid, the second
The contents of the DMA control storage means are transferred into the third DMA control storage means, and then the contents of the first DMA control storage means are transferred to the second DMA control storage means, and the state saving instruction signal is issued. Having control means for performing
Transfer means.

Further, the microcomputer according to the present invention further comprises a first bus for the central processing means to perform data processing, and a second bus for the DMA transfer means to perform DMA transfer. Features.

[0010]

[0011]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a block diagram showing a microcomputer system constituted by using a microcomputer 100 according to a first embodiment of the present invention. The microcomputer 100 includes a CPU 10, a DMA controller (DMAC) 20, an interrupt controller (INTC) 30, and a serial data receiving unit 4 as peripheral units.
0 and other units 50 such as a timer and a counter. These are formed on the same semiconductor substrate and have an internal bus 6
0 interconnected.

The CPU 10 fetches and executes an instruction from a program memory 110 connected via a system bus 130 to perform processing on operand data. The data memory 120 is also connected to the system bus 130.

The INTC 30 receives a plurality of interrupt request signals including the interrupt request signals 23 and 51 from the DMAC 20 and the peripheral unit 50, and when two or more interrupt requests occur simultaneously, the interrupt request is performed according to a predetermined priority. And generates an interrupt processing request signal 31 to the CPU 10 and supplies the interrupt vector number 32 to the CPU 10. Based on the interrupt processing request, the CPU 10
Suspends the program processing being executed, saves the program counter, program status word, and general-purpose registers (all not shown) at that time and executes the interrupt processing routine.

The serial data receiving unit 40 receives serial data supplied from outside via a serial line 150. Serial data is stored in the shift register 40
5 in turn. When data of a predetermined number of bits (for example, 8 bits) is received, the data is transferred to the buffer register 404, and the shift register 405 starts receiving the next serial data. When the data is transferred to the buffer register 404, the reception control unit 401 activates the DMA transfer request signal 42 and requests the DMA 20 to transfer data. The data transferred to the buffer register 404 is EO indicating the end of one frame of the serial data transfer.
In the case of the F (End Of Frame) code, the block switching signal 41 is activated to request the DMAC 20 to perform block switching. The reception of the EOF code and the occurrence of an error in the received data are recorded in the status register 402. The reception control unit 401 is a DMAC2
The contents of the buffer register 404 are output to the internal bus 60 in synchronization with the data output instruction signal 25 from 0. Also,
The contents in the status register 402 are saved in the status save register 403 in response to the status save instruction signal 24 from the DMAC 20.

The DMAC 20 has a transfer control unit 201,
The control unit 201 executes DMA data transfer between the unit 40 and the memory 120 based on the control information stored in the current register block 202. The control information stored in the register block 202 includes transfer count information indicating a data transfer count, memory address information indicating an access address of the memory 120, and control / status information. The control / status information includes the direction of the DMA data transfer (that is, the transfer from the memory to the peripheral unit or from the peripheral unit to the memory, from the serial receiving unit 40 to the memory 120 in this embodiment), the update direction of the memory address, the DMA transfer request Has transfer request acceptance permission information indicating whether or not to accept DMA.
It includes block continuation instruction information indicating whether transfer can be continued to the next block. DMAC 20 further includes a next register block 20 in accordance with the present invention.
3 and a save register block 204. The next register block 203 stores information necessary for the next DMA transfer to be executed after the end of the current DMA transfer, that is, information on the number of transfers of the next DMA transfer, memory address information, and control / status information. The save register block 204 saves the transfer count information and the control / state information of the current register block 202. The transfer control unit 201 issues a hold request (HLD
RQ) signal 21 and receives a hold acknowledge (HLDACK) signal 22 from the CPU 10 to
Then, the data transfer from the serial receiving unit 40 to the memory 120 is executed. Each time data transfer is performed, the number of transfers of the current register block 202 is 1
At the same time, the memory address 202 is updated. When the number of transfers becomes 0, that is, when the number of transferred data reaches the number of data specified by the current DMA transfer or when the block switching request signal 41 based on the reception of the FOF code from the unit 40 becomes active, the current register block 202 Is saved in the save register block 204.
When the block continuation instruction information included in the saved control / state information indicates “continuation”, the contents of the next register block 203 are copied to the current register block 202, and the interrupt request signal 23 is generated. . When the block continuation instruction information indicates “non-continuation”, the interrupt request signal 23 is generated without copying from the next register block 203 to the current register block 232.

The data memory 120 stores operand data to be processed and processed by the CPU 10, and further stores the serial data receiving unit 40.
Has N blocks 122, 124,... The block control data area 12 corresponds to each of these blocks.
, 127 are provided. Each of the block control data areas includes a transfer count data area indicating the size of a corresponding block, a memory address data area indicating a head address of the corresponding block, and control / status in DMA transfer between the corresponding block and the receiving unit 40. It has a data area, a peripheral state save data area to which the contents of the status save register 403 of the receiving unit 40 are to be transferred, and a next address data area for storing a head address of a control data area for another block. The data memory 120 further has a control data area address storage area 121.

Hereinafter, the specific operation of the microcomputer will be described in detail with reference to the operation flow shown in FIGS.

The CPU performs an initial setting before activating the DMAC 20. That is, the first to Nth blocks 12
, 126 are assigned to the data memory 120, and the corresponding block control data areas 123, 12
Data is written in 5,... 127 as described above. The block continuation instruction information in the DMA control / status data of the first to (N-1) th block control data areas is "continue".
And that of the Nth block control data area indicates "non-continuation". Also, the next address data of the first block control data area includes the start address of the second block control data area, the second block control data area includes the start address of the third block control data area, and the (N- 1) It is assumed that the start address of the Nth block control data area is set in the block control data area. Control data area address 12
1 is set to the start address of the first block control data area 123. The CPU 40 also sets information necessary for serial data reception in the serial data receiving unit 40, for example, the speed of the serial line 150, and permits serial reception. Then, the transfer count data of the second block control data area 125, the memory address data, and the DMA control / state data are set in the next register block 203 of the DMAC 20, and the transfer count data of the first block control data area 123 is set in the current register block 202. , Memory address data and DMA control / status data are set and the DMAC 20 is started. CPU 10 subsequently fetches and executes instructions from program memory 10.

On the other hand, the activated DMAC 20 operates according to the operation flow shown in FIG. That is, it is checked whether the block switching request signal 41 accompanying the reception of the EOF code from the serial data receiving unit 40 is active (251), and it is checked whether the data transfer request signal 42 is active (252).

The serial data receiving unit 40 is also activated, and receives serial data transmitted via the serial line 150. When data of a predetermined number of bits is received, it is checked whether the data is an EOF code or normal data, and a signal 41 or 42 is generated.

If the serial data receiving unit 40 generates a data transfer request signal 42, the transfer control unit 20
1 activates the HLDRQ signal 21 to activate the bus 60,
The right to use 130 is requested to the CPU 10 (253). C
The PU 10 temporarily suspends the program processing being executed, puts the inside in a hold state, and outputs the HLDACK signal 22 to the DMAC 2
Return to 0. The transfer control unit 201 has an active level HL
When the DACK signal 22 is detected (254), the memory address of the current register block 202 is transferred to the bus 60, 1
The data is supplied to the data memory 120 through the bus 30 and the data output instruction signal 25 is generated to make the serial data receiving unit 40 output the received data to the bus 60. Thus, the received data is stored in the first block 1 in the memory 120.
It is transferred to the head address of No. 22 (255). After the transfer,
The HLDRQ signal 21 is withdrawn and the right to use the bus is returned to the CPU 10. The transfer control unit 201 sets the current register block 2
02 is updated and rewritten, and one is subtracted from the transfer count data and rewritten (257). If desired, the updated address may be used as the access address of the first block 122. The transfer control unit 201 determines whether the subtracted transfer count is zero (258), and if not, returns to step 251. This process is executed every time the data transfer request signal 42 becomes active.

The block switching request signal 41 is generated or the number of transfers becomes zero, that is, the first block 122
Is satisfied with the received data, the process proceeds to step 259. That is, the transfer count information and the control / state information of the current register block 202 are saved in the save register block 204. The transfer control unit 201 determines the block continuation instruction information in the saved control / state information (260). In this description, since the information indicates “continuation”, the process proceeds to step 261 and the contents of the next register block 203 are stored in the current register block 20.
2 Thus, the DMAC 20 has a CPU
The DMA transfer between the serial data receiving unit 40 and the second block 124 of the memory 120 can be executed without waiting for resetting by 10. Transfer control unit 201
Generates a peripheral save signal 24 and an interrupt request signal 23, and shifts to step 251. Therefore, when the serial data receiving unit 40 subsequently generates the data transfer request signal 42, the received data is transmitted to the second block 12
4 will be transferred.

On the other hand, in response to the peripheral save signal 24, the reception control unit 401 saves the contents of the status register 402 in the status save register 403.

The INTC 30 issues an interrupt processing request to the CPU 10 in response to the interrupt request signal 23 from the DMAC 20. The CPU 10 suspends the program execution based on the request, saves information necessary for resuming the suspended program execution to a stack area (not shown) of the data memory 120, and executes the interrupt processing routine of FIG.

In this interrupt processing routine, the CPU
10 first reads the saved status information from the status save register 132 in the receiving unit 40 (301), and checks whether an error has occurred in the received data or the receiving state (302). If an error has occurred, as an error process 303, the operations of the DMAC 20 and the data receiving unit 40 are stopped, a request is made to the source of serial data for retransmission of data, and
The AC 20 and the unit 40 are reset. If no error occurs, the contents of the status save register 403 are transferred to the peripheral state save data area of the first block control data area 123, and the contents of the save register block 204 of the DMA 20 are transferred to the transfer count data area and DMA control of the area 123. / Transfer to the status data area (304). For this processing, the head address of the data area 123 is stored as the control data area address 121, and the address of each data area is calculated from the same address and a predetermined offset amount of each data area in each block. Is done. Of course, DMAC2
The addresses of 0 and each register in the receiving unit 40 are predetermined. Then, the next address data of the first block control data area 123, that is, the second address data,
The head address of the block control data area is set as the control data area address 121. Next, block continuation instruction information of the DMA control / status data saved in the first block control data area 123 is determined (3.
05). In the present description, the information indicates “continuation”, so that the newly set control data area address 121
And the next address data in the second block control data area 125, and transfers the transfer count data, memory address data, and DMA control / status data in the third block control data area (not shown) to the next register of the DMAC 20. Transfer to block 203 (30
6).

Returning to FIG. 2, when the block continuation instruction information indicates "non-continuation" in step 260, the transfer control unit 201 outputs a signal without copying the contents of the next register block 203 to the current register 202. 2
4 and 23 are generated, and the DMAC 20 waits for the CPU 10 to reset the data and enters the DMA transfer prohibited state.
Accordingly, in the interrupt processing routine of the CPU shown in FIG. 3, the process proceeds from step 305 to step 307, in which the transfer count data, memory address data, and DMA control / status data in the second and third block control data areas are current. Are transferred to the register block 202 and the next register block 203, respectively.
20 is restarted.

After execution of step 306 or 307, the CP
U10 performs processing on the data transferred to the first block 122 (308). After execution, data memory 1
The information saved from step 20 is restored, and the suspended program is resumed.

Since the transfer count information of the save register block 204 is also transferred to each block control data area, even if the above-described block switching is executed by the block switching request signal 41 due to the reception of the FOE code,
It is possible to determine how many data are transferred to each block.

As described above, if the block continuation instruction information is set to “continue”, even if a predetermined number of data is transferred or the FOE code is received, the DMAC 20 sets the data transfer permission state to the next block. Therefore, occurrence of a reception overrun error can be prevented.

When the microcomputer 100 also incorporates a serial data transmission unit, a current register block, a next register block and a save register block for the same unit are further prepared in the DMAC 20 to provide a transmission unit and a reception unit. Executing the data transfer in a time-division manner can prevent both the reception overrun error and the transmission underrun error.

Referring to FIG. 4, a microcomputer 101 according to a second embodiment of the present invention includes a DMA between a serial data receiving unit 40 and a local memory 400.
It has a DMAC 20 for executing transfer. Note that the same components as those in FIG. 1 are denoted by the same reference numerals and description thereof is omitted. DMAC
20, the receiving unit 40 and the local memory 400 are interconnected by a local bus 450. When the receiving unit 40 issues a data transfer request, the transfer control unit 20
1 obtains the right to use the local bus from a processor (not shown) that manages the local bus 450 based on the HLDRQ signal 21 and the HLDACK signal 22, and transfers data from the receiving unit 40 to the local memory 400.

In such a configuration, the CPU 10 shown in FIG.
This interrupt processing routine is not temporarily interrupted by the DMA transfer, so that the processing efficiency of the CPU can be further improved. The local memory 400 is also under the control of the microcomputer 101, and the local bus 450
When used as a dedicated bus for A transfer, the transfer control unit 201 can execute DMA transfer without using the signals 21 and 22.

The interrupt processing routine of FIG. 3 is stored in the program memory 110 and can be changed relatively freely by the user. For example, error check (30
2) and data processing (308) for all blocks 1
, 126 may be executed collectively after the data transfer to data transfer to the memory devices 22, 124,... However, steps 304 to 30
6 is preferably executed as long as it instructs block continuation.

In executing the interrupt processing routine shown in FIG. 3, the CPU 10 firstly stores the current state of the interrupted program execution, that is, the contents of the program counter (PC), program status word (PSW) and general-purpose registers. There is a so-called overhead of saving the data in the data memory 120 and restoring the saved contents after executing the interrupt processing routine to restart the program. Eliminate such overhead and use DMA
If the microcomputer itself executes the rated processing based on the interrupt request from C20 as if it were a part of the hardware, the processing efficiency can be further increased and the user's program load can be reduced.

FIG. 5 shows a configuration for this purpose as a third embodiment. FIG. 5 shows only the CPU 15 and the INTC 30 of the microcomputer in this embodiment.
Other configurations are the same as those in FIG. The CPU 15 employs a microprogram control method, and each function stored in the program memory 110 executes a corresponding series of microinstructions (that is, microprograms) to achieve this function. The microprogram is completely invisible to the user because it is invisible to the user.

That is, the program counter (PC) 1
51 is transferred to the buses 60 and 130 via the address bus driver 153, so that the instruction read from the program memory 110 is transferred to the data buffer 154.
Is temporarily stored in the instruction register (IR) 155 via The instruction from the IR 155 is decoded by the decoder 156 and supplied to the execution unit 158. The execution unit has a microprogram memory 1585, and by setting the microaddress of the decoded instruction to the microprogram pointer 1584, a series of microinstructions is read and executed. The execution unit 158 further includes an arithmetic logic unit (ALU) 1581 and a program status word (PSW) 158 for temporarily storing the operation state.
2. It has a temporary register 1583 and executes a series of micro-instructions in cooperation with the general-purpose register 157, thereby performing the function of the instruction stored in the IR 155. Control signal group 159 output from execution unit 158
Is a sequence control signal for instruction execution.

The micro program memory 1585 stores the macro service micro program 15 according to the present embodiment.
86 are stored. The macro service will be described later in detail. This macro service program 1586
Is activated when the interrupt request from the INTC 30 specifies a macro service request.

That is, the INTC 30 is the DMAC 20
Flag 3 that specifies whether to process an interrupt request from the server as a macro service or as a normal vector interrupt
Three. When the flag 33 is set, the macro service is specified, and when it is cleared, the vector interrupt is specified. When receiving the interrupt request, the INTC 30 generates an interrupt processing request signal 31 in the execution unit 158 and stores the interrupt mode information 32-1 in the IR 155. Further, the execution unit 15 stores the vector number information 32-2.
8 As a result of decoding the interrupt mode information 32-1, if a vector interrupt is designated, the start address of the interrupt processing routine is obtained from the vector number information 32-2, and
151, the contents of the PSW 1582, and the contents of the general-purpose register 157 are saved in the data memory 120, the start address is set in the PC, and the interrupt processing routine is executed. On the other hand, when the interrupt mode information 32-1 specifies the macro service, the head micro address of the macro service micro program 1582 is obtained from the vector number 32-2, and this is set in the pointer 1584 to execute the micro program. . At this time, the contents of the PC 151, the PSW 1582, and the general-purpose register 157 are left unsaved without being saved, and updating of the contents is prohibited.

Next, the operation will be described in detail. The CPU 15 executes the program stored in the program memory 110 as described in FIG.
0, serial data receiving unit 40 and DMAC2
Perform initialization to 0. However, in this embodiment, DM
A control / status information followed by macro service followed by C
Vector interrupt request designation information for causing the PU 15 to shift to vector interrupt processing is also included. In the present description, no vector interrupt request is specified in the first to (N-1) th blocks.
It is specified in the Nth block. In addition, the first to (N
-1) In the block, the block continuation designation information is "continuation", and in the Nth block, it is "non-continuation". Further, in the present embodiment, the INTC 30
Is set. After such initial settings, the CP
U15 continues to fetch and execute instructions from the program memory 110.

On the other hand, the DMAC 20 operates according to the flow shown in FIG. 2, and every time data of a predetermined number of bits is received, the data is DMA-transferred from the receiving unit 40 to the first block 122 of the data memory 120. . When the transfer count data of the current register block 202 becomes zero or the FOF code is received, in this description, the transfer count data and the control / status data of the current register 202 are saved in the save register block 204, and the next The contents of the register block 203 are copied to the current register block 202 (2 in FIG.
59 to 261), then the peripheral save instruction signal 24 is generated and the interrupt request signal 23 is generated.

Since the flag 33 is set, IN
The TC 30 transfers the macro service mode designation information 32-1 to the IR 155 in response to the interrupt request signal 23. Thus, the macro service microprogram is
1, the PSW 1582 and the general-purpose register 157 are started without saving. A flowchart of the macro service micro program is shown in FIG. That is, using the value of the control data area address 121 of the data memory 120, the contents of the status save register 403 and the contents of the save register block 204 of the DMAC 20 are transferred to the corresponding areas of the first block control data area 123, respectively (601). ). The block continuation instruction information of the saved DMA control / status data is checked (60).
2). In this description, since the instruction is “continuation”, the first
The next address data of the block control data area 123 is set as the area address 121 (60).
3), the same address and the second block control data area 12
Using the next address data 2 of No. 5, the transfer count data, memory address data and DMA control / status data of the third block control data area are transferred to the next register block 203 of the DMAC 20 (60).
4). Thereafter, the vector interrupt request instruction information of the DMA control / status data transferred to the first block control data area 123 is checked (605). In this description, since no vector interrupt request is made, the macro service ends.

When the macro service ends, the PC 15
1, the update of the PSW 1582 and the general-purpose register 157 are permitted, and the execution of the interrupted program is resumed. Since there is no overbed due to the interruption and resumption of the program, the processing efficiency of the CPU is further increased.

If "non-continuation" is designated in step 602, the flow shifts to step 605. If a vector interrupt request has been specified in this step, the flag 33 is cleared (606), and the macro service ends.

When the flag 33 is cleared, I
The NTC 30 sets the vector interrupt mode code 32-1 to IR / 55 again, and as a result, an interrupt routine by the user program is started.

Various processes can be considered for the processing by the interrupt routine according to the block continuation instruction information and / or the vector interrupt request instruction information corresponding to each block. In this description, since the vector interrupt is activated after the data is transferred to the N-th block 126, the error check based on the peripheral state save data in each block and the processing for each data are collectively executed in the interrupt processing routine. Is done.

As described above, according to the present embodiment, the DMAC
Since the necessary data transfer between the memory 20 and the data memory 120 is executed as a part of the hardware of the microcomputer as a macro service by the microprogram, the execution efficiency of the data processing is further improved, and the burden of program creation on the user is reduced. Can be reduced.

Also in the present embodiment, the DMA
C20 can cause a DMA transfer between the receiving unit 40 and the local memory 400 to be performed.

[0049]

As described above, according to the present invention, the DMA
Switching of transfer blocks can be performed at a very high speed of several clocks, and the transfer prohibition period can be extremely shortened.
It is possible to cope with a case where the issue period of the A transfer request is short.

It is clear that the present invention is not limited to the above-described embodiment, but can be modified as appropriate. For example, instead of copying the next register block 203 to the current register block 202, a register to be referred to by the transfer control unit 201 is stored in the next register block 2 by the multiplexer.
03 may be switched. At this time, the next information is loaded into the register block 202, which becomes the next register block.

[Brief description of the drawings]

FIG. 1 is a system block diagram using a microcomputer according to a first embodiment of the present invention.

FIG. 2 is an operation flowchart of a DMAC shown in FIG. 1;

FIG. 3 is a flowchart illustrating an example of an interrupt processing routine of the microcomputer illustrated in FIG. 1;

FIG. 4 is a system block diagram according to a second embodiment of the present invention.

FIG. 5 is a block diagram showing a CPU of a microcomputer according to a third embodiment of the present invention.

FIG. 6 is a flowchart of a macro service microprogram of the CPU shown in FIG. 5;

Claims (2)

(57) [Claims] 1. A direct memory access (hereinafter referred to as DM)
A) A transfer request signal is issued, and D is
A peripheral circuit including state saving storage means for issuing an MA transfer end instruction signal and saving and storing the internal state upon completion of the processing or upon detection of the state saving instruction signal;
DMA control information storage unit including A transfer continuation instruction information and DM
A first, second, and third D types including an A transfer number storage unit
MA control storage means, and when the DMA transfer request signal is detected, performs a DMA transfer between the peripheral circuit and the memory, and updates a value of a DMA transfer number storage unit in the second DMA control storage means, If either a predetermined value is obtained as a result of the update or the DMA transfer end instruction signal is detected, and the DMA transfer continuation instruction information in the second DMA control storage means is valid, the second DM
The contents of the A control storage means are transferred into the third DMA control storage means, then the contents of the first DMA control storage means are transferred to the second DMA control storage means, and the state saving instruction signal is issued. And a DMA transfer unit having a control unit. Wherein the first bus for the central processing unit performs data processing, according to claim 1, wherein the DMA transfer means, characterized by further comprising a second bus for DMA transfers Microcomputer.