JPS63239549A - Data chaining control system - Google Patents

Abstract

PURPOSE:To execute the link array chain without reducing the priority of the bus acquisition right of an I/O by specifying the starting of a DMA transfer in a system equipped with a DMA controller having a double plane register group. CONSTITUTION:A DMA controller 1 is equipped with double plane register groups 2 and 3 to accumulate transfer information to access a memory 10. Before a DMA is started, the transfer information of a first block is written to the register group 2 of the controller 1 and the transfer information of a second block is written to a register group 3 and a DMA transfer is started. Thus, without reducing the priority of the bus acquisition right of the I/O, the link array chain can be executed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data chaining control method for easily performing DMA, and particularly to a data chaining control method for easily performing DMA of multiple blocks in the memory of a virtual system. The present invention relates to a data chaining control method suitable for.

[Conventional technology]

Conventional methods of this type include 5, for example, Japanese Patent Application Laid-Open No. 59-1
A method disclosed in No. 77633 is known. This method uses the main memory (MS) when data chaining a write operation in a channel device.
There are two types of microprograms: one that performs data chaining following an operation that fetches data from an MS fetch operation, and in some cases terminates without performing data chaining after an MS fetch operation, and another that performs data chaining alone. In this system, each microroutine is used depending on the state of the channel device.

[Problem that the invention seeks to solve]

In the above-mentioned conventional technology, it is necessary to provide a means for preferentially selecting processing requests of the data buffer control circuit and other processing requests, and the conditions for preferential selection are also byte count, chain data flag, channel command word (hereinafter referred to as r
ccWJ), etc.

Therefore, in the above conventional technology, the channel device is M
When performing an S fetch, it is necessary to check whether the byte count is "0", whether the chain data flag is on, and whether the data is being transferred, and if it is being transferred, whether it is related to the previous CCW. The problem is that the channel equipment is expensive due to its complexity.

The present invention has been made in view of the above circumstances, and its purpose is to solve the above-mentioned problems in the prior art, and to give priority to Ilo bus acquisition rights in a system where the memory block size is larger than a certain level. without lowering your rank,
It is a data chain that can perform link array chains, and can easily configure virtual systems even when using Ilo, which was designed without being aware of the existence of link array chains. The objective is to provide an inning control method.

Another object of the present invention is that even if a link array chain is performed in a virtual system to which the present invention is applied,
An object of the present invention is to provide a data chaining control system that allows a worker 10 to acquire the bus right with the highest priority and allows the use of an inexpensive Ilo with the smallest buffer.

[Means for Solving the Problems] The above object of the present invention is to provide a system in which a DMA controller having two register groups A and B for storing transfer information for accessing a memory shares a bus with the memory. Before starting the DMA transfer, after writing the first block transfer information to the register group A of the DM4 controller and the second block transfer information to the register group B, start the DMA transfer. This is achieved by a data chaining control method featuring:

[Effect]

In the data chaining method according to the present invention,
Before starting a DMA transfer using a link array chain, the processing unit (MPU) registers registers A,
Write the transfer information of the first block (the above CCW) and the transfer information of the second block to the DMAC equipped with B, and then issue a DMA transfer start request to the input/output device (Ilo) adapter. .

The DMAC registers register l at the request from the I10 adapter.
The DMA transfer of the first block is performed using the transfer information in #A, and then the DMA transfer of the second block is performed using the transfer information in register group B. During the transfer, the transfer information regarding the third block is read from the transfer information table in memory (see below).

This operation is called "command read").

Write to register group A.

The priority order of bus use is set in the order of DMA transfer, command read, and MPU memory access (see Figure 2).
During MA transfer, command read for the fourth block is performed.

D until the last block using link array chain
Continue MA transfer.

By the way, in the virtual system to which the present invention is applied, the block size of physical addresses is constant. DMA using link array chain at this physical address
When performing a transfer, the DMAC uses 1 as shown in FIG.
DMA transfer starts from the middle of the second block, and from the second block onwards, DMA transfer is performed in blocks,
DMA transfer ends in the middle of the last block.

〔Example〕

EMBODIMENT OF THE INVENTION Below, one embodiment of the present invention will be described in detail based on the drawings.

FIG. 4 is a system configuration diagram showing an embodiment of the present invention. In the figure, 1 is DMAC, 4 is MPU, 6 is data bus, 9 is Ilo, 10 is memory, and
22, 23, and 24 indicate command read, MPU read, and DMA read operations, which will be described later.

FIG. 3 shows a more detailed configuration of the DMAC 1 and memory 10. In the figure, 2 and 3 are the DMA start address (hereinafter referred to as rADJ), the number of DMA transfer bytes (hereinafter referred to as rCTJ), and the command Code (hereinafter r
A group of registers A, B, and 5 for taking in data (referred to as CDJ) indicate a physical address bus. Further, 8 is an address converter, 15 is a priority determination circuit that determines the use of the data bus 6, 18 is a DMA control circuit that controls DMA in the device 109, and 11 is a block in the memory (size 4 bytes).
, 19 indicate a transfer information table in the memory 10 as well.

The DMAC 1 shown in each of the above uses the physical address bus 5, the data bus 6, and the memory lead line 25 to transfer data from the transfer information table 19 in the memory 10 to the above-mentioned AD.
, CT, and CD. This operation is the command read operation (22), which takes about 400 ns.

Furthermore, the MPU 4 has a function of reading data from the memory 10 via the data bus 6 by outputting the logical address 12 and the memory lead line 25. This operation is the M P U U-do operation (23), and is about 40
It takes 0ns. Furthermore, the MPU4
By using the 0 line 7, the above-mentioned AD,
It has a function of writing CT and CD, and a function of issuing a DMA start command to l109.

Note that the address converter 8 converts the logical address 12 on the logical address bus into a physical address.

It has a function of outputting to the physical address bus 5.

The memory IO has a function of outputting data corresponding to a physical address on the physical address bus 5 to the data bus 6. As described above, a space partitioned into four bytes on the memory 10 is called a block. Also, memory 10
has a transfer information table 19 that stores the transfer information AD, CT, and CD.

The l109 outputs a data bus use request signal (DREQ) 13 to the DMAC1 every 800 ns in response to the f7) DMA start command from the MPU4. D
In the MAC 1, the priority determining circuit 15 receives a data bus use request (CRE Q) 20 from the DMA control circuit 18 and the DREQL3, and turns on a data bus use request (HRE Q) 16 to the MPU 4. MPU4
When the above HREQ16 is received, data bus use is permitted (
HACK) 17 is output.

In response to the HACK 17, the priority determination circuit 15 issues a data bus use permission (CACK) 21 to the DMA control circuit 18;
Alternatively, permission to use the data bus for Engineering 109 (DA
CK)14. The worker 109 reads data from the memory 10 upon receiving the DACK14. This operation is the DMA read (24) and requires about 400 ns. Note that the priority determination circuit 15 is configured to perform DMA read (24), command read (22), and MPU read (2) as described above.
Priority decisions are made in the order of 3).

Hereinafter, a specific example of the operation of this embodiment configured as described above will be explained. 6 FIG.
It shows the operation of DMA reading data divided into three blocks from address 3000H to address 3FFFH and from address 100OH to address 1001H to the workpiece 109.

First, the MPU 4 uses the write I10 line 7 to set AD=4FFEH, CT=2H2 and a CD indicating byte DMA read (24) in 5 register group A (2), and sets AD=4 in register group B (3). 3000H, CT=1000
H, and byte DMA IJ-code (24), command read (22), and set CD indicating that the start address of the transfer information table 19 is FOOOH. In the transfer information table 19, AD=1000H
, CT=2H, and after performing a byte DMA read (24), a CD indicating the end of DMA is set.

Next, the MPU 4 activates the write I109 via the write I10 line 7. The l109 issues a DMA read (24) request by turning on the DREQ13. The priority determination circuit 15 has a DMA read (24) and a command read (24).
2) The right to use the data bus 6 is given in the order of MPU read (23). This situation is shown in FIG.

That is, when the DMAC1 turns on the DACK14, the DMA control circuit 18 extracts the first DMA address AD=4FFEH from the register group A(2), outputs it to the physical address bus 5, and further outputs the first DMA address AD=4FFEH from the register group A(2). ) updates the value. Memory IO.

The data at address 4FFEH is output to the data bus 6, and the device 109 reads the data. When l109 reads the data, it turns off DREQ13. This results in HREQ
16. HACK17. It is turned off sequentially with DACK14.

When DMA read (24) is performed again, the 2-byte DMA read (24) set in register group A (2) is performed.
end. The DMA control circuit 18 performs the third DMA read (24) on the AD of register group B (3).

DMACl is performed from address 3000H of the memory 10 using CT and CD.
While performing a DMA read (24) of byte 4 using T and CD, a command read (22) is performed from the transfer information table 19 of FOOOH, and the register group A (2) is read.
This command read (22), which writes AD, CT, and CD in three steps, is lower than the DMA read (24), and the M
Since it is performed with higher priority than PU read (23), D
The time from when DREQ13 is issued to when DACK14 is returned in MA read (24) is the same as command read (24).
Regardless of 2), it is 400 ns or less. This situation is shown in FIG.

The above command read (22) is the DMA read (24)
Do this three times in between. In this case, since the size of block 11 is 4 bytes, there are 4095 intervals between DMA reads (24), and command reads (22) are always possible. In this way, AD=1000H, CT of the transfer information table 19 is stored in register group A(2) of DMACl.
= 2H, after performing the DMA IJ-de of the byte, D
The CD that completes the MA read (24) is set.

After completing the 4th byte DMA read (24), the DMAC1 performs two DMA reads (24) using the register group A (2). Here, the CD includes, as mentioned above,
After the DMA read (24) of CT=2H ends, the series of DMA transfers ends because it is written to end the DMA read (24).

In the above embodiment, there are two register groups A.

AD, CT, and CD are written in B in advance, and the effect of this will be explained in detail with reference to FIG. 7 below.

l109 outputs DREQ13 every 800ns.

Since l109 does not have an internal buffer, the DMA read (24) must be completed before the next DREQ13 is output.The DMA read (24) is not completed before the next DREQ13 is output. in case of,
l109 causes an overrun and the data in memory 10 is not transferred to l109.

CREQ20 of DMAC1 is turned from off to on as necessary (necessary until the third DMA transfer, unnecessary thereafter) 200 ns after CACK21 turns from on to off. DMACl is set as necessary depending on the contents of the CD of register group A (2) or register group B (3).
Command read (22) to write AD, CT, and CD to register group B (3) or register group A (2) is performed three times.

In the example shown in Figure 5, the block to be transferred is 3000H.
When there is 3 F F FH, DMAC1 is 3
The command read (22) can be performed reliably. However, when the block is from 4FFEH to 4FFFH, the command read does not end.6 In the present invention! In order to solve this problem, as mentioned above, the MPU4
Using write/○ line 7, register group B (
3), since the AD, CT, and CD are set, the command read (22) is not necessary.

FIG. 8 shows register group B (
3) without setting AD, CT, and CD in advance,
FIG. 4 is a diagram showing a case where DMA transfer is performed from 4FFEH to 4FFFH. In this case, register group B (3
), the block is switched when AD and CT are written. DMAC1 cannot perform DMAIJ-code (24) because there is no CD in register group B (3).
l109 causes an overrun.

Furthermore, FIG. 9 shows the priority order of data bus use, which is not based on the present invention, such as command read (22), DMA read (22),
24), MPU read (23), and command read is performed three times in a row.

In this case, even if the block size is the smallest, the DMA
Before the read (24) moves to the next block, the writing of AD, CT, and CD to the register group B (3) is completed. However, in this case, the l109 DMA lead (24)
However, because I had to wait more than 800ns.

Overrun occurs.

In order to eliminate the above-mentioned overrun without relying on the present invention,
By providing many buffers in l109, DMACl is
, CD, and it is necessary to change the order of use priority of the data bus, making the l109 and DMAC1 complicated and expensive.

In the embodiment described above, DMA read has been described, but the same applies to writing data from the l109 to the memory 10, and the present invention is effective even when there are a plurality of l109s.

〔Effect of the invention〕

As described above, according to the present invention, there is a two-sided register group A that stores transfer information for accessing memory.

In a system in which a DMA controller having B shares a bus with the memory, before starting DMA, transfer information of the first block is transferred to the register group A of the DM4 controller, and transfer information of the first block is transferred to the register group B of the DM4 controller. Since the DMA transfer is started after the transfer information of the first block is written, in a system where the memory block size is larger than a certain value, the link array Even if Ilo is designed without being aware of the existence of a link array chain, it is possible to perform a link array chain, and a virtual system can be easily configured.゛Also, in a virtual system to which the present invention is applied, even if link array chaining is performed, I
Since LO can acquire the bus right with the highest priority, the buffer in I10 can be minimized, so it is possible to use inexpensive ILO, and the DMAC structure can be simplified, making the DMAC inexpensive. It also has the effect of making it possible.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the configuration of the present invention, FIG. 2 is a time chart thereof, FIG. 3 is a diagram showing the detailed configuration of the DMAC1° memory IO of the embodiment, and FIG. 4 is a diagram showing an embodiment of the present invention. The system configuration diagram shown in FIG. 5 is a specific configuration diagram of the memory, and FIG.
7 shows the timing of command read according to the present invention, FIGS. 8 and 9 show the transfer of the right to use the data bus.
The figure is a diagram showing the timing when performing conventional DMA transfer. 1: DMAC12, 3: Register group A, B, 4: M
PU, 5: Physical address bus, 6: Data bus, 8 Near address converter, 9: Ilo, IO: Memory, 11: Block in memory, 15: Priority determination circuit, 18: DMA
Control circuit, 19: Transfer information table, 22: Command read, 23: MPU read, 24: DMA read, AD
: DMA start address, CT: DMA transfer byte number, CD: command code. Figure 4 Q Figure 5

Claims (1)

[Claims] 1. Direct memory access (
DMA) In a system where a controller shares a bus with the memory, the DMA controller
Data chaining characterized in that DMA transfer is started after writing the transfer information of the first block to the register group A of the controller and the transfer information of the second block to the register group B of the controller. control method.