JPH05136808A - Time managing system - Google Patents

Abstract

PURPOSE:To enable a polishing control even if a cell having the same destination is not generated for more than one period Tck of a clock counter in the polishing control of the cell having plural users. CONSTITUTION:A control part 4 refers to the content of a cell arrival history memory 3 with the counted value of a timing generation circuit 2 (corresponding to user's identifier) as an address. When the number of cells xm generated in elapse time tm from the start of supervisory is not zero, the counted value CTs of (the clock counter 1-previous cell arrival time tp+elapse time tm) is calculated. When it is more than supervisory time width Tm, xm, tp and tm are set to zero When it is not more than Tm, CTs-tp+tm is newly set to tm, and CTs is newly set to tp. Thus, a time update processing is executed at least once for any cell of the users.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a time management system in an apparatus for measuring the number of fixed length data such as ATM cells generated within a predetermined time.

[0002]

2. Description of the Related Art ATM (Asynchronous T
In the transfer mode) network, the user declares the bandwidth to be sent to the network. Therefore, when the user sends out ATM cells (hereinafter abbreviated as cells) exceeding the declared value, cells exceeding the pre-allocated band will flow in, which will affect the quality of service of other calls. Will affect.

For this reason, it is necessary to monitor by the function of monitoring the declared bandwidth of the user so that cells exceeding the declared value of the user do not flow into the network. Hereinafter, the function of monitoring the user's reported bandwidth will be referred to as policing.
An example of this policing method is shown below. This method
As a monitoring parameter, it has a monitoring time width Tm, which is a time unit for monitoring the number of cells transmitted from the user, and a maximum number of cells Xm allowed to exist in Tm, and X within Tm time.
When more than m cells are input, the input cell is regarded as a violation cell and the violation cell processing is performed.

Here, consider policing control for a single user. Figure 8 is a conceptual diagram of the cell format.
FIG. 9 is a policing control time chart for a single user when Tm = 5 and Xm = 2, and FIG. 10 is an operation flowchart thereof. As shown in FIG. 8, the cell has a fixed length of 53 bytes. The 5-byte header portion has cell destination information, and at the same time can be used as a user identifier. The 48-byte information section is composed of information (voice, image, data) to be transferred to the destination. And
The cell sync is a signal that is periodically generated once per cell time.

A cell is input to a policing circuit (not shown) in synchronization with a cell sync. The policing control in the policing circuit is performed by a clock counter that manages the monitoring time width Tm of the user, a cell number counter that manages the maximum number of cells Xm allowed to exist during Tm, and a control unit that controls these. .. The clock counter counts up in synchronization with the cell sync and is reset when the counter value reaches Tm. The cell number counter is counted up when there is an input cell and is reset when the clock counter is reset. If the cell number counter value at that time is Xm, the input cell is regarded as a violating cell and is processed as a violating cell. For example, “Broadband ISDN-compatible ATM communication technology” supervised by Masatake Nagai, P. 12
There are various processing methods as described in No. 6, Trikeps Co., Ltd., issued November 29, 1990, but here, there are unconditional disposal methods (cells judged as violating cells are unconditionally discarded. Be done).

As described above, the policing control for a single user can be easily performed.

[0007]

However, if policing control is performed for a plurality of users by the conventional method, a policing control function corresponding to the number of users is required.
There was a problem that the hardware scale became very large and the cost increased. The present invention solves the above-mentioned problems, and in a device that measures the number of times a plurality of types of fixed length data occur within a predetermined time for each type of fixed data, a clock counter that manages time for each fixed length data. It is an object of the present invention to provide a time management system that does not require a data number counter for managing the number of fixed-length data items and therefore can significantly reduce the cost and the scale of hardware. It is another object of the present invention to provide a time management method that enables the number of occurrences of fixed-length data of the same type to be measured even if the same type of fixed-length data does not occur for one cycle or more.

[0008]

In order to achieve the above object, the present invention has U types (where U is an integer of 2 or more).
In a device for measuring the number of fixed length data generated within a predetermined time for each type of the fixed length data, the first timing signal generated for each data length of the fixed length data is input, A clock counter for counting, a first timing signal and a clock signal in synchronization with the first timing signal, and a second timing signal having a speed that is U / Tck (but rounded up if not an integer) times the first timing signal, A timing generation circuit that outputs a counter value that counts the second timing signal as a clock input, data that indicates the type of input fixed-length data as an address, the arrival time tp of the previous fixed-length data, and monitoring of the fixed-length data Of the fixed length data, the number of fixed length data xm generated during the elapsed time tm A fixed value data monitoring time width Tm set for each class, a memory having the maximum number Xm of fixed length data allowed to exist in Tm, a clock counter, a timing generation circuit, and A control unit for controlling the memory is provided, and when the second timing signal is detected,
The content of the memory is referred to by using the counter value of the timing generation circuit as an address, and if xm is not 0, the counter value of the clock counter −tp + tm is calculated. If this is Tm or more, xm, tp, tm are set to 0, and Tm or more Otherwise, the counter value −tp + tm is newly set to tm, and the counter value of the clock counter is newly set to tp.

[0009]

According to the present invention, since the time management system is configured as described above, when the second timing signal is detected, the control unit refers to the contents of the memory by using the counter value of the timing generation circuit as an address, and xm is If it is not 0, the counter value −tp + tm of the clock counter is calculated, and if it is Tm or more, it means that the monitoring time has elapsed. Therefore, xm, tp, and tm in the memory are set to 0. The counter value −tp + tm of the counter is newly set as tm in the memory, and the counter value of the clock counter is newly set as tp in the memory.

Therefore, for any fixed-length data, the time update process is performed at least once during the period Tck of the clock counter, and the number of occurrences of fixed-length data is generated even if the fixed-length data is not generated for Tck or more. Can be measured.

[0011]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a time management system according to an embodiment of the present invention, which is composed of a clock counter 1, a timing generation circuit 2, a cell arrival history memory 3 and a control unit 4.

The clock counter 1 receives a cell sync as an input and counts up. Then, the counter value is reset when one cycle elapses, and is newly counted up. The timing creation circuit 2 receives the cell sync and the clock synchronized with the cell sync as inputs, and creates the timing for performing the time update processing described later and the logical channel number LCN of the user who should perform the time update processing. The cell arrival history memory 3 uses the logical channel number LCN of the input cell as an address, and has the previous cell arrival time tp, the monitoring elapsed time tm, the number of cells in tm xm, the monitoring time width Tm, and the maximum permitted existence. The number of cells Xm is included in the data. However, the address is from 0 to the number of users (U) -1. The control unit 4
The normal processing for determining a violating cell and the time update processing provided for coping with the case where there is no input cell for one cycle (Tck) or more of the clock counter are performed. These two processes may be performed serially (no order relation) or in parallel.

2 and 3 are flowcharts of the normal processing of the time management method according to the embodiment of the present invention. here,
The unlawful discard method was adopted for the processing of the violating cell. In FIG.
First, in step 11, it is determined whether or not there is a cell sync. If there is a cell sync, the process proceeds to step 12, and if the input cell is an empty cell in step 12, this processing is not performed. If it is not an empty cell, the logical channel number LCN of the input cell is used as an address and the cell arrival history memory 3 is read as shown in step 13. Then, in step 14, the monitoring elapsed time tm
If the number of cells in the cell xm is 0, in order to enter the monitoring state, xm in the cell arrival history memory 3 is set to 1 in step 15,
In step 16, the previous cell arrival time tp in the cell arrival history memory 3 is set to the counter value CTs of the clock counter 1.
If xm is not 0 in step 14, it means that the monitoring state is set, and therefore, the process proceeds to step 17 in FIG.

At step 17, (CTs-tp) + t
If m ≧ Tm, it means that the monitoring elapsed time is equal to or longer than the monitoring time width. Therefore, in step 18, {(CTs-t
p) + tm} -Tm is newly set as tm in the cell arrival history memory 3. Further, xm in the cell arrival history memory 3 is set to 1 in step 19, and tp is set to CTs in step 20. On the other hand, in step 17, (CTs-tp) + tm <T
If it is m, the monitoring elapsed time is less than the monitoring time width, and therefore, in step 21, a violation cell determination is performed. Where xm
If +1> Xm, it is regarded as a violation cell and step 25
Violation cells are processed in. In step 21, xm + 1
If ≦ Xm, it is not regarded as a violating cell, so that (CTs−tp) + tm is set to tm in step 22, and step 2
In step 3, xm + 1 is newly set as xm. In addition, step 2
In step 4, CTs is set to tp. Here, CTs-tp
When CTs-tp> 0, as shown in the conceptual diagram of the arrival cell elapsed time considering the counter cycle in FIG.
s-tp is acceptable, but when CTs-tp <0, CTs-t
Let p + Tck. When CTs = tp, this value is regarded as Tck. Actually, the two's complement of CTs and tp may be added.

By the way, if there is no input cell for one cycle or more of the clock counter by the normal processing alone, the elapsed monitoring time cannot be determined and the policing processing becomes impossible. Therefore, time update processing is performed. The processing timing and the logical channel number LCN of the user who should perform the processing are
Made with a timing creation circuit. FIG. 5 is a block diagram showing the configuration of the timing generation circuit in the embodiment of the present invention.

1 cell time (1 cell hold time on the line =
The number of times the time update process is performed during the cell sync interval is
If U is the number of users and Tck is the period of the clock counter, then U / Tck is obtained. However, if this value is not an integer, round it up to an integer. A cell sync and a clock are input to the pulse generation circuit 31 of FIG. 5, and a pulse synchronized with the cell sync is generated at a speed of U / Tck times the speed of the cell sync. This is a pulse corresponding to the timing at which the time update processing is performed. Then, this pulse is input to the clock of the counter 32, and the logical channel number LCN of the user who performs the time update processing is created. However, the counter value is 0 to U-1. As described above, the time update process is performed at least once in the cycle Tck of the clock counter 1 in any user cell.

Actually, the functions of the clock counter 1 and the timing generation circuit 2 in FIG. 1 can be treated as the same function. For example, U = 4096, n = 204
When it is 8, a pulse having a double speed synchronized with the cell sync is generated, and this pulse is used as a clock input from 0 to 409.
If a counter that repeats up to 5 is created and all the bit outputs of the counter are used for time update processing, and the output excluding the lower 1 bit of the counter is used as the clock counter, two operations of the clock counter and the timing generation circuit can be performed with one function. Become. However, here, in order to simplify the explanation, it is divided into two functions.

FIG. 6 is a flowchart of the time update processing of the time management method according to the embodiment of the present invention. Hereinafter, the time update processing operation will be described with reference to FIGS. 1, 5, and 6. First, if there is an output pulse of the pulse generation circuit 31 in step 41 of FIG. 6, the cell arrival history memory 3 is read in step 42 using the counter value of the counter 32 as an address. In step 43, if xm = 0 in the cell arrival history memory 3, there is no previous cell arrival, so this processing is not performed. If xm ≠ 0, in step 44 (CT
s-tp) + tm ≧ Tm is judged, and if this holds, it means that the monitoring time has elapsed, so step 4
In step 5, xm, tp and tm in the cell arrival history memory 3 are reset to 0 and reset. On the other hand, if the above condition is not satisfied, only the time is updated. Therefore, in step 46, tm in the cell arrival history memory 3 is set to (CTs-tp) + tm,
Set CTs to tp. By the above processing, the violating cell can be determined even if no cell is generated for the period Tck of the clock counter 1 or more.

In FIG. 7, the number of users U = 3, the period Tck of the clock counter = 4, the monitoring time widths Tm1, Tm2, Tm3 of the users u1, u2, u3 are 2, 3, 4 and Tm, respectively.
1, maximum number of cells X allowed to exist in Tm2, Tm3
It is a control time chart when m1, Xm2, and Xm3 are set to 1 (therefore, U / Tck = 3/4).
→ 1). Hereinafter, with reference to FIGS. 1 to 7, the user u1
The normal process and time update process for the cell will be described.
However, it is assumed that the cell C1 of the user u1 is the cell of the user u1 to be input first and the cells C1 to C3 are not empty cells. Also, the counter value of the timing generation circuit is 0,
It is assumed that 1 and 2 respectively indicate the logical channel numbers LCN of the users u1, u2 and u3.

First, when the cell C1 is input to the control unit 4 of FIG. 1, normal processing is performed. At this time, since YES is determined in both step 11 and step 12 of FIG. 2, the process proceeds to step 13. Here, the cell arrival history memory 3 is read by using the logical channel number LCN of the user u1 as an address, but since it is the first input cell, NO is determined in step 14, and the cell arrival history memory 3 is determined in step 15.
Xm = 1 in the above, and tp = CTs = 3 in step 16.

Next, when the counter value of the timing generation circuit of FIG. 7 becomes the first 0, the time updating process for the user u1 is performed. At this time, in step 41 of FIG. 6, Y
It is determined to be ES, and in step 42, the cell arrival history memory is read with the counter value of the timing generation circuit = 0 as an address. Since xm = 1 has already been set, step 43 becomes YES and the routine proceeds to step 44. here,
(CTs-tp) + tm = 1 (CTs = 0, tp = 3,
Since tm = 0), NO is obtained and the routine proceeds to step 46. Here, tm = 1 and tp = 0.

Next, when the cell C2 is input, normal processing is performed in the same manner as described above, CTs = 1, Tp = 0, tm =
1, xm = 1, so YES in step 17 of FIG.
Then, in step 18, tp = 1, tm = 0, xm = 1
And Next, when the cell C3 is input, normal processing is performed in the same manner as described above, xm = 1, CTs = 2, tp = 1,
Since tm = 0, NO in step 17 and NO in step 21 of FIG. 3, and the cell C3 is discarded in step 25.

Next, when the counter value of the timing generation circuit of FIG. 7 becomes the second 0, the user u1
The time update processing for is performed. CTs = 3, xm =
Since 1, tm = 0 and tp = 1, YES at step 43 and YES at step 44 in FIG. 6 and reset at step 45 xm = 0, tp = 0, tm =
It becomes 0.

Thereafter, the normal process and the time update process are similarly performed, and the normal process and the time update process are similarly performed in the cells of the users u2 and u3. It should be noted that the present invention is not limited to the above embodiments, and various modifications can be made based on the spirit of the present invention, and they are not excluded from the scope of the present invention.

[0025]

As described above in detail, according to the present invention, in a device for measuring the number of types of fixed length data generated within a predetermined time for each type of fixed length data, Even if the fixed length data does not occur for one or more cycles of the clock counter, the number of occurrences can be measured.

Therefore, if the present invention is applied to policing control of an ATM cell having a plurality of users, even if cells having the same destination do not occur for one cycle or more of the clock counter,
Policing control is possible. Further, even if the clock counter is not prepared for each user, the reference clock counter 1
In addition, since the control can be performed only by preparing the cell arrival history memory and the cell arrival time memory, the hardware scale and the cost can be greatly reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a time management system according to an embodiment of the present invention.

FIG. 2 is a part of a normal processing flowchart of a time management method according to an embodiment of the present invention.

FIG. 3 is a part of a normal processing flowchart of a time management method according to an embodiment of the present invention.

FIG. 4 is a conceptual diagram of an arrival cell elapsed time in the embodiment of the present invention.

FIG. 5 is a block diagram showing a configuration of a timing generation circuit according to an embodiment of the present invention.

FIG. 6 is a flowchart of a time update process of the time management method according to the embodiment of the present invention.

FIG. 7 is an operation time chart of the time management system according to the embodiment of the present invention.

FIG. 8 is a conceptual diagram of a cell format.

FIG. 9 is an example of a conventional policing control time chart for a single user.

FIG. 10 is an example of a conventional policing control operation flowchart for a single user.

[Explanation of symbols]

 1 Clock Counter 2 Timing Creation Circuit 3 Cell Arrival History Memory 4 Control Unit

Claims (2)

[Claims] 1. An apparatus for measuring, for each type of fixed length data, the number of U types (where U is an integer of 2 or more) of fixed length data generated within a predetermined time, wherein: (a) the fixed length data First occurs for each data length of
And a clock counter that counts time with a cycle Tck, and (b) receives the first timing signal and a clock signal synchronized with the first timing signal as an input, and outputs the first timing signal of U / Tck (however, rounding up if not an integer) times the second timing signal and the second timing signal.
A timing generation circuit that outputs a counter value that counts the timing signal as a clock input, and (c) data indicating the type of the input fixed length data as an address, the arrival time tp of the previous fixed length data, and the fixed length. The elapsed time tm from the start of data monitoring,
The number xm of the fixed length data generated during the elapsed time,
A specified value Tm of the fixed time data monitoring time width set in advance for each type of fixed length data and the specified value Tm
A memory having the maximum number Xm of the fixed length data permitted to exist therein, and (d) a control unit for controlling the clock counter, the timing generation circuit and the memory, and at the time of detecting the second timing signal. , The content of the memory is referred to by using the counter value of the timing generation circuit as an address, and the counter value −tp + tm of the clock counter is calculated if xm is not 0, and if this is greater than or equal to Tm, xm, tp, and tm are set to 0. The time management method is characterized in that the counter value of the clock counter −tp + tm is newly set to tm and the counter value of the clock counter is newly set to tp if Tm or more. 2. The time management method according to claim 1, wherein the U types of fixed length data are ATM cells having different destinations, and the first timing signal is a cell sync.