JP3501603B2 - Arithmetic circuit failure monitoring method - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a usage parameter control (UPC: User Parameter Control) device or network usage parameter control (Network Parameter Co).
The present invention relates to a failure monitoring method for a policing / shaping arithmetic circuit that performs arithmetic operations in a traffic shaping device or a traffic shaping device.

Asynchronous transfer mode (ATM: Asynchronous) in which information to be communicated is divided into fixed-length cell units and transferred.
Transfer Mode) In traffic control performed in a network, in particular, by detecting a violation of traffic volume with respect to negotiated parameters and taking appropriate measures, QOS (Quality of Se
ruse), which is used to protect users and networks from interference by malicious users, for example, User Parameter Control (UPC) and network parameter control (Network Parameter).
ter control) is performed by the arithmetic circuit in the UPC device or NPC device. Further, the cell delay fluctuation (CDV: Cell Delay Variation) generated in the ATM device is reduced, and the traffic shaping operation for shaping the traffic characteristic into a desired shape is performed in the shaping device (shaper). The present invention relates to a fault monitoring method for such a polishing / shaping arithmetic circuit.

[0003]

2. Description of the Related Art Role of UPC device / shaper In ATM communication, a user declares a transfer amount of information to the network side, and the network side performs accommodation design and gives allocation permission to the user (contract). When one user transfers information in excess of the contracted amount, it may affect other users such as cell loss. For this reason,
UPC device (or NPC device) at the entrance of the network
Is placed to monitor the flow rate of information sent by the user, and if there is a violation, the information is discarded. UPC (or NPC)
Is also called policing because it has the above functions.

However, due to cell delay fluctuation (CDV) generated in the user equipment or the like, information is discarded to some extent in the UPC equipment even though the user complies with the contract amount. Pass the violation. Therefore, a shaper is arranged in the latter stage of the UPC device to reduce the cell delay fluctuation (CDV).

Regarding the UPC device, the UPC device monitors whether or not the traffic characteristics of the cell flow sent from the user of the ATM service comply with the parameters contracted with the user, and controls the cell flow as necessary. For example, discard processing is performed on cells that violate the contract. Violation is determined using a virtual scheduling algorithm, leaky bucket algorithm, or an equivalent algorithm.

FIG. 2 shows an example of a policing algorithm (virtual scheduling algorithm). In FIG. 2, the minimum cell interval T and the CDV allowable value τ are parameters set as a result of negotiation. The theoretical cell arrival time TAT and the cell arrival time ta are parameters for calculation.

In the cell flow defined by the cell interval T, cells always arrive at T intervals. Therefore, based on the cell arriving at the time ta, the time at which the cell next arrives is theoretically defined by (ta + T). The time at which the cell should arrive is called the theoretical cell arrival time TAT.

The theoretical cell arrival time TAT is compared with the cell arrival time ta (step S2). If the actual arrival time ta of the cell arrives later than the theoretically specified time (YES in step S2), it is determined that the cell is a suitable cell, and the TAT is changed to the current time (step S3). ), And TAT is updated (step S4).

If the actual arrival time ta of the cell arrives earlier than the theoretically specified time (NO in step S2), it means that the cell violates the contract, but immediately. Does not judge that the user is a nonconforming cell that has violated the contract, and the difference between the theoretical cell arrival time TAT and the cell arrival time ta (TAT-ta: indicates how much the arrived cell violates the contract). And the CDV allowable value τ are compared in size to determine conformity / nonconformity (step S5).

If the difference (TAT-ta) is larger than the CDV allowable value τ (YES in step S5), the cell is determined to be a nonconforming cell and a discarding process is performed (step S6). On the other hand, when the difference (TAT-ta) is less than or equal to the CDV allowable value τ (NO in step S5), it is determined that the cell violates the contract but is within the allowable range and the TAT is updated (step S4).

Shaper The shaper has a function of reducing cell delay fluctuation (CDV) including cell flow. A cell that has violated the contract due to cell delay fluctuation (CDV) is buffered and the cell is output at a desired time. The cell output time Tout is determined by using a virtual scheduling algorithm, a leaky bucket algorithm, or an algorithm equivalent thereto. When the cell output time Tout conflicts with another cell, output competition control based on the FIFO discipline is performed,
Output without reversing the order of cells with the same connection.

FIG. 3 shows an example of the shaping algorithm (virtual scheduling algorithm).
In FIG. 3, the minimum cell interval T and the CDV residual value τ are parameters set as a result of negotiation. The theoretical cell transmission time TET, cell output time Tout, and cell arrival time ta are parameters for calculation.

In the cell flow defined by the cell interval T, cells always arrive at T intervals. Therefore, based on the cell that arrived at time ta, the next time the cell should arrive is
It is theoretically defined by (ta + T). The time at which the cell should arrive is called the theoretical cell arrival time TAT. Since the shaper basically controls to output at that time,
In particular, it is also called theoretical cell transmission time TET.

The theoretical cell transmission time TET is compared with the cell arrival time ta (step S12). The actual arrival time ta of the cell is TET at the theoretically specified time.
When arriving later (YES in step S12),
After determining that the cell is compatible, the theoretical cell transmission time TET is changed to the current time ta (step S13), and then the theoretical cell transmission time TET is updated (step S17). The cell outputs at the current time (step S14).

If the actual arrival time ta of the cell arrives earlier than the theoretically specified time (NO in step S12), it means that the cell violates the contract, but immediately. Does not judge that the user is a nonconforming cell that has violated the contract, and the difference between the theoretical cell transmission time TET and the cell arrival time ta (TET-ta: indicates how much the arrived cell violates the contract). And CDV residual value τ
The size relationship of is compared to determine conformity / nonconformity (step S15).

When the difference (TET-ta) is larger than the CDV residual value τ (YES in step S15), the cell is determined to be a non-conforming cell, shaping is performed, and the cell is output at the time (TET-T) (step S16). ), The difference (TET-ta)
Is less than or equal to the CDV residual value τ (N in step S15
O), the cell violates the contract but is output as the conforming cell within the allowable range at the current time (step S14), and the theoretical cell transmission time TET is updated (step S17).

Example Algorithm of UPC / Shaper Device FIG. 4 shows an example algorithm of the UPC / shape device.
FIG. 4 shows an embodiment in which a VSA (Virtual Scheduling Algorithm) is used as a traffic monitoring method in a UPC (NPC) device and an output time calculating method in traffic shaping.

In FIG. 4, the minimum cell spacing T (UPC,
Shaper common), CDV allowable value τ _u , CDV residual value τ _S
Are parameters set as a result of negotiation. Theoretical cell arrival time TAT, cell output time Tout,
The cell arrival time ta is a parameter for calculation. UPC
It is a feature of this algorithm that the minimum cell interval T used in the apparatus and the minimum cell interval T used in the shaper are expressed by a common parameter, and the CDV is immediately reduced after the violation judgment.

In the cell flow defined by the cell interval T, cells always arrive at T intervals. Therefore, based on the cell arriving at the time ta, the time when the next cell should arrive is theoretically defined by ta + T. The time at which the cell should arrive is called the theoretical cell arrival time TAT.

The theoretical cell arrival time TAT is compared with the cell arrival time ta (step S22). If the actual arrival time ta of the cell arrives later than the theoretically specified time (YES in step S22), it is determined as a conforming cell, and the theoretical cell arrival time TAT is set to the current time t.
After changing to a (step S23), the theoretical cell arrival time TAT is updated (step S25). The cell outputs at the current time (step S24).

If the actual arrival time ta of the cell arrives earlier than the theoretically specified time (NO in step S22), it means that the cell violates the contract, but immediately. Does not judge that the user is a nonconforming cell that has violated the contract, and the difference between the theoretical cell arrival time TAT and the cell arrival time ta (TAT-ta: indicates how much the arrived cell violates the contract). And CDV allowable value τ
_Matching / unmatching is determined by comparing the magnitude relationship of _u (step S26).

If the difference (TAT-ta) is larger than the CDV allowable value τ _u (YES in step S26), the cell is determined to be a non-conforming cell and the discarding process is performed (step S3).
0). On the other hand, when the difference (TAT-ta) is equal to or less than the CDV allowable value τ _u (NO in step S26), the contract is violated but the cells are not discarded as conforming cells within the allowable range, and shaping (reduction of CDV) is performed. To do.

In shaping, the difference (TAT
-Ta) is compared with the CDV residual value τ _S (step S
27). When the difference (TAT-ta) is larger than the CDV residual value τ _S (YES in step S27, [(TA
The CDV is reduced by (T−ta) −τ _S ], and the time (T
AT- [tau] _S ) is output to the cell (step S28), and when the difference (TAT-ta) is less than or equal to the CDV residual value [tau] _S (NO in step S27), the cell is output to the current time ta (step S29). ), The theoretical cell arrival time TAT is updated (step S25).

Device Configuration of UPC / Shaper Device FIG. 5 shows a circuit example of the UPC / shape device. This device can also be operated as a UPC unit or a shaper unit by hardware or software control. The device configuration includes a cell detection device 3, storage devices 6 and 7 for storing traffic parameters and calculation parameters, a calculation device 4 for performing violation determination and calculation of output time, a storage device 1 for writing cell data, and memory control. It comprises a device 5, a memory control storage device 8, and an output control device 2.

Here, the cell detector 3 reads the control data described in the header of the arrived cell. The parameter storage memory 6 stores traffic parameters, and the arithmetic memory 7 stores arithmetic parameters.
The calculation unit 4 determines the violation and calculates the output time of the cell. The storage device 1 for storing cell data writes the input cell data. The memory control unit 5 uses the address of the cell data written in the storage device 1 for storing cell data as the calculation unit 4
Management is performed based on the output time input from. The memory control device storage device 8 manages the address of the cell data.
The output control unit 2 reads out and outputs the data of the corresponding cell from the cell data storage device 1 at the output time of the cell.

The storage devices 6 and 7 store parameters for each cell type. When the cell arrives, the cell detection unit 3 reads the control data described in the header of the cell and identifies the cell type. The computing unit 4 performs violation determination and calculation of the output time Tout according to the above algorithm for each cell type while accessing the storage devices 6 and 7 as necessary. The memory control unit 5 manages the address of the cell data written in the cell data storage device 1 based on the output time Tout input from the calculation unit 4. The memory control storage device 8 stores data necessary for managing the cell data address. The output control unit 2 reads out and outputs the data of the corresponding cell from the cell data storage memory 1 at the cell output time Tout.

Example of Violation Monitoring Circuit of UPC / Shaper Device FIG. 6 shows an example of a circuit of a portion of the arithmetic unit 4 of the UPC / shape device which performs violation monitoring. This circuit performs violation monitoring according to the algorithm of FIG. In FIG. 6, reference numeral 40 is a header detection unit for sending out the sender information, and 41 is a time counter for counting the cell arrival time. 42
˜45 are respectively memories, the memory 42 stores the theoretical cell arrival time TAT, the memory 43 stores the CDV tolerance τ _u , the memory 44 stores the CDV residual value τ _S , and the memory 45 stores the minimum cell. The interval T is stored. Reference numeral 47 is an adder for updating the theoretical cell arrival time TAT stored in the memory 42 by adding the minimum cell interval T stored in the memory 45 thereto. Reference numeral 46 denotes a difference device, which outputs (TAT-ta) from the outputs of the memory 42 and the time counter 41.
) Is calculated and output. 48 is a comparator, (TAT
-Ta) and τ _u are compared to perform UPC determination and UPC failure detection. 49 is a comparator, which is (TAT-ta) and τ _S
Is compared to perform SHPR (shaper) determination.

The operation of this circuit will be described below. The header detection unit 40 extracts header information such as VPI and VCI of the corresponding connection. Based on the value, the theoretical cell arrival time TAT is read out and stored in the memory 42. Similarly, the CDV allowable value τ _u , the CDV residual value τ _S , and the minimum cell interval T are read out and stored in the memories 43 and 4, respectively.
4 and 45.

The time counter 41 is a time counter that counts up every cell time, and its output is the current time ta. Next, the difference device 46 calculates the current time ta.
By calculating the difference between the theoretical cell arrival time TAT and the theoretical cell arrival time TAT, it is possible to find how early or late the arriving cell arrived from the theoretically defined time of the cell to arrive.

Next, the CDV allowable value τ _{u of the} corresponding connection
Is read from the memory 43. This CDV allowable value τ _u
And the time interval (TAT-ta) are compared with each other to determine UPC violation. When (TAT-ta) is larger than the CDV allowable value τ _u , it is determined that the cell is a nonconforming cell, and the discarding process is performed. When (TAT-ta) is equal to or smaller than the CDV allowable value τ _u , the contract is violated, but the cell is not discarded as a conforming cell within the allowable range, and shaping (reduction of CDV) is performed.

Next, the CDV residual value τ _{S of the} corresponding connection
Are read from the memory 44. Shaping is performed by comparing calculated by calculating the above (TAT-ta) and the CDV residual value tau _S. When (TAT-ta) is larger than the CDV residual value τ _S , the cell delay fluctuation (CDV) is reduced by [(TAT-ta) −τ _S ], and the time (TAT-ta) is reduced.
-Tau _S) to output a cell, (TAT-ta) is in the following cases: CDV residual value tau _S outputs the cell to the current time ta.

Next, the minimum cell interval T of the corresponding connection is read from the memory 45, added to the theoretical cell arrival time TAT previously read from the memory 42 by the adder 47, and the value is updated. Cell arrival time TAT
Are again stored in the memory 42.

[0033]

When a failure occurs in the above-mentioned policing arithmetic circuit, it is possible to cause a great trouble to the user by discarding non-violating cells. Therefore, the UPC / NPC calculation unit performs failure monitoring, and when a failure is detected, a failure alarm is notified to the OPS (Operation System).

Further, in order to avoid inconvenience to the user or the network due to the failure of the shaping operation circuit, the failure is monitored by the shaping operation.
When a failure is detected, a failure alarm is notified to the OPS.

By the way, with the arrival of the future full-scale multimedia age, there is a demand for downsizing of ATM-related devices. Therefore, regarding the failure monitoring method of the arithmetic circuit,
It is necessary to devise a method that is as simple as possible in terms of hardware scale and that can be monitored regardless of a policing algorithm such as a leaky bucket algorithm (LBA) or a virtual scheduling algorithm (VSA). Especially, when the policing function and the shaping function are realized by a single device (LSI), further simplification is made due to the limitation of the circuit scale, and a monitoring method that can be commonly used for policing and shaping is devised. There is a need to.

For example, a method of detecting the presence / absence of an operation failure by duplicating the hardware of the operation unit and collating the results can be considered, but this method increases the hardware scale and becomes redundant.

Further, known data (parameters for the arithmetic unit to perform arithmetic) whose arithmetic result is known is prepared in advance, the known data is set in the arithmetic unit, and the known data is arithmetically operated. A method of comparing the calculation result with the previously known result is possible, but this method is
It is difficult to judge when, what kind of data and how often should be done. When actually detecting a fault by this method, a large number of parameters (data)
It is considered that it is necessary to prepare the above, and to perform the calculation by the data selected at random, and the faults that can be detected are inevitably limited.

Further, the hardware scale of the failure detection circuit may be large and complicated as compared with the arithmetic circuit. For example, FIG. 7 shows an example of a device configuration in the case of performing failure monitoring by the above method. When performing fault monitoring by the above method, in addition to the device configuration described in the related art, a storage device 10 that stores a plurality of known data for fault monitoring, and a plurality of fault monitors stored in the storage device 10 at fault detection timings. It is necessary to have a failure monitoring control unit 9 that randomly reads out a set of data from known data for use, and a failure determination unit 11 that makes a violation determination by collating the result calculated by the read parameters with known data. Will be very large. Particularly, the storage device 10 that needs to store a large amount of data requires a large storage capacity. Regarding the data for failure monitoring, it is necessary to consider what value should be used and how much data should be prepared.

Further, it is considered that the fault monitoring control will be very complicated. It is also necessary to pay attention to the timing of failure detection. That is, when performing this failure determination, the operating system must be temporarily stopped for failure determination. Even considering the above, it can be said that there is no merit in adopting this failure monitoring method.

The present invention has been made in view of the above problems, and is simple, has a small hardware scale, does not depend on an algorithm, and has a failure in a polishing operation unit and a shaping operation unit that can be commonly used for polishing and shaping. To provide a monitoring method.

[0041]

In order to solve the above problems, in the present invention, traffic control is performed in an asynchronous transfer mode network in which information to be communicated is divided into fixed length cell units and transferred. In this case, a traffic volume violation for the negotiated parameters is detected, and a failure of the operation unit of the usage parameter control device or the inter-network usage parameter control device that performs processing such as discarding on the violated cells is periodically generated. There is provided a failure monitoring method for an arithmetic circuit, which performs detection on the basis of the determination result of the conformance test by performing a policing operation on the OH generating cell with a monitoring parameter having a cycle corresponding to the cycle of the OH generating cell.

In the present invention, as another form,
Asynchronous communication mode in which information to be communicated is divided into fixed-length cell units and transferred When controlling traffic in a network, shaper operation unit failure that reduces cell delay fluctuations and shapes traffic characteristics into the desired shape To
For the periodically generated OH generation cells, the input and output cell intervals of the OH generation cells input to the shaper are compared, and if they differ, it is detected that some abnormality has occurred in the shaping calculation unit. A failure monitoring method for an arithmetic circuit is provided.

[0043]

[0044]

[0045]

[0046]

[0047]

DETAILED DESCRIPTION OF THE INVENTION An embodiment of the present invention will be described below with reference to FIG. This embodiment circuit is provided in the arithmetic unit in the UPC / shape device of FIG. In FIG. 1, the circuit having the same reference numeral as that in the failure monitoring circuit described in the conventional example of FIG. 6 has the same configuration. That is, the header detection unit 40, the time counter 41,
Memories 42 to 45, differencer 46, adder 47, comparator 4
8 and 49 are the same circuits. As a difference, a starter 400 that monitors the cycle of the OH generation cell, a memory 401 that stores the previous cell transmission time (previous Tout), a differentiator 402 that obtains the difference between the theoretical cell arrival time TAT and the previous Tout,
A comparator 403 for comparing the difference (TAT-previous Tout) from the differentiator 402 with the minimum cell interval T is added.

This embodiment circuit uses the OH generation cell (overhead generation cell) generated when the ATM cell format is converted from the transmission path format to the in-apparatus format to monitor the failure of the arithmetic unit. Is. That is, since the cell format of 53 bytes on the transmission line is converted into the cell format of 54 bytes in the ATM switch for processing, the OH generation cell for correcting this difference is generated at a constant cycle. .

Since this OH generation cell is basically input to the UPC in a constant cycle, if the policing operation is performed with the monitoring parameter of the same cycle, it will not be judged as a violation in the conformity test. When it is determined that there is a violation, it can be determined that some abnormality has occurred in the arithmetic unit.
Further, when a cell flow of a constant cycle (that is, OH generation cell) that does not violate the shaper is input, and if the cell interval after shaping is not the same as the input cell interval, some abnormality occurs in the arithmetic unit. You can judge that.

In FIG. 1, each memory 42, 43, 4
OH cell monitoring parameters (that is, TAT, τ _u , τ _S , and previous Tout) are set in advance in 4, 45, and 401, respectively. Since the setting parameter is monitored in the same cycle as the OH generation cell, the specified OH generation cell is set in the minimum cell interval T, the CDV allowable value τ _u , the CDV residual value τ _S , and the theoretical cell arrival time TAT. , Previous cell transmission time Tout is set to 0.

The header detecting section 40 extracts the header information of the corresponding connection (cell type information, etc.) to identify the cell. If the cell type is an OH generation cell, the OH generation cell cycle monitoring unit 400 monitors the arrival cycle, and if it is a prescribed cycle, performs failure monitoring, and if it is not a prescribed cycle, the original cell Fault monitoring is not performed because the cycle is incorrect.

The theoretical cell arrival time TAT is read out based on the header information such as the VPI and VCI of the relevant connection extracted by the header detection unit 40. Time counter 4
Reference numeral 1 is a time counter that counts up every cell time, and its output is the current time ta. Next, the difference unit 46 obtains the difference between the current time ta of the time counter 41 and the theoretical cell arrival time TAT of the memory 42, so that the arrived cell is theoretically defined from the time at which the cell should arrive, You can ask how early or how late you arrive.

Next, the CDV allowable value τ _{u of the} corresponding connection
Is read from the memory 43. This CDV allowable value τ _u
And the time interval (TAT-ta) are compared by the comparator 48, and U
Violation judgment of PC is performed. The time interval (TAT-ta) is C
If it is larger than the DV allowable value τ _u , it is a non-conforming cell, but when monitoring the OH generation cell, since it is monitored at the same cycle as the OH generation cell cycle, if this UPC operation unit is normal. It is never judged as non-conforming. If it is determined to be non-conforming, it can be determined that some abnormality has occurred in the UPC calculation unit. However, at this time, the OH generation cell is passed without being discarded. If the time interval (TAT-ta) is equal to or less than the CDV allowable value τ _u , the contract is violated but the cells are not discarded as conforming cells within the allowable range, and shaping (CDV deletion) is performed.

Next, the CDV residual value τ _{S of the} corresponding connection
Are read from the memory 44. The shaping is performed by comparing the time interval (TAT-ta) calculated previously with the CDV residual value τ _S by the comparator 49. Time interval (TAT
-Ta) is larger than the CDV residual value τ _S ,
[(TAT-ta)-[tau] _S ] cell delay fluctuation (C
DV) is reduced, cells are output at time (TAT-τ _S ), and if the time interval (TAT-ta) is less than or equal to the CDV residual value τ _S , cells are output at current time ta.

Next, the previous Tout of the corresponding connection is read from the memory 401, and the subtractor 402 subtracts it from the theoretical cell arrival time TAT previously read from the memory 42. At this time, the difference (TAT-previous Tout) is always T. Therefore, the minimum cell interval T previously read from the memory 45 is compared with the comparator 403, and if they are not equal, there is some abnormality in the shaper calculation unit. You can judge that.

Next, the minimum cell interval T of the corresponding connection
Is read from the memory 45, added to the theoretical cell arrival time TAT previously read from the memory 42, and then the memory 4
By rewriting to 2, the value of the theoretical cell arrival time TAT is updated.

[0057]

[0058]

The parameters for monitoring the OH generation cell are set in various forms such as: setting in the internal memory of the LSI; setting in the external memory of the LSI; holding as a fixed value inside the LSI. be able to.

[0060]

As described above, according to the present invention, the failure of the polishing arithmetic circuit or the shaping arithmetic circuit is monitored by utilizing the OH generation cells periodically generated. It is possible to exert an effect.

This can be easily realized by extracting a cell for failure monitoring which is periodically input and calculating the corresponding cell by a normal calculation method.

In terms of the circuit, an OH generation cell cycle monitoring unit, a memory device of the previous Tout, a TAT-previous T are added to the existing arithmetic circuit.
It can be realized by only adding an out subtraction circuit and TAT-previous Tout and T comparison circuit. Other than that, it can be realized by using the existing circuit as it is. The failure monitoring method does not increase the circuit scale and can be downsized. Is.

The same method can be used for monitoring regardless of algorithms such as the virtual scheduling method and leaky bucket method.

The method can be commonly used for starting failures of policing and shaping, and this method can be applied whether the policing function or the shaping function is realized by different LSIs or the same LSI.

[Brief description of drawings]

FIG. 1 is a diagram showing a violation monitoring circuit for carrying out a failure monitoring method for an arithmetic circuit according to an embodiment of the present invention.

FIG. 2 is a flowchart showing an example of a UPC algorithm.

FIG. 3 is a flowchart showing an example of a shaping algorithm.

FIG. 4 is a flowchart showing an example when applied to a virtual scheduling algorithm (VSA).

FIG. 5 is a diagram showing a configuration example of a UPC / shape device.

FIG. 6 is a diagram showing a configuration example of a failure monitoring circuit (shaper type UPC circuit) in an arithmetic unit in the apparatus shown in FIG. 5;

FIG. 7 is a diagram showing a configuration example of a UPC / shape device when a failure monitoring circuit is added.

[Explanation of symbols]

1 Cell data storage device 2 Output control section 3 cell detector 4 computing section 5 Memory controller 6 Parameter storage device 7 Computing storage device 8 Memory control storage device 9 Failure monitoring control unit 10 Failure monitoring data storage device 11 Failure determination unit 40 Header detector 41 time counter 42-45, 401 memory 46,402 Difference device 47 adder 48, 49, 403 Comparator 400 OH generation cell cycle monitoring unit

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁷ Identification symbol FI H04M 3/36 H04M 3/36 B H04Q 3/00 H04Q 3/00 (72) Inventor Koji Nishikawa Kamiodatanaka, Nakahara-ku, Kawasaki-shi, Kanagawa 4-1-11 Fujitsu Limited (72) Inventor Ryoichi Iwase 3-19-2 Nishishinjuku, Shinjuku-ku, Tokyo Nihon Telegraph and Telephone Corporation (56) Reference JP-A-6-112969 (JP, A) JP-A-9-214511 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H04L 12/56 400 H04L 12/56 200

Claims (2)

(57) [Claims] 1. When performing traffic control in an asynchronous transfer mode network in which information to be communicated is divided into fixed length cell units and transferred, a violation of the traffic volume with respect to a negotiated parameter is detected, and a violation cell is detected. On the other hand, the failure of the calculation unit of the usage parameter control device or the inter-network usage parameter control device that performs processing such as discarding is determined by a cycle corresponding to the cycle of the OH generation cell with respect to the periodically generated OH generation cell. A failure monitoring method for an arithmetic circuit, in which a policing operation is performed using the monitoring parameters of and the detection is performed based on the determination result of the conformance test. 2. A shaper for reducing cell delay fluctuation and shaping a traffic characteristic into a desired form when performing traffic control in an asynchronous communication mode network in which information to be communicated is divided into fixed length cell units and transferred. If the input and output cell intervals of the OH generation cells that are input to the shaper are compared and the OH generation cells that are periodically generated are compared, the abnormality in the shaping calculation unit has occurred. A failure monitoring method for an arithmetic circuit that is detected by doing so.