JPH0483475A - Synchronizing signal separating circuit - Google Patents

Abstract

PURPOSE:To remove a false synchronizing(SYN) signal due to undershooting by providing this SYN signal separating circuit with an OR means for finding out OR between a SYN signal separated based upon a threshold and a delayed SYN signal. CONSTITUTION:The SYN signal separating circuit is provided with a signal separating means 1A for separating a SYN signal based upon a threshold a delay means 3 for delaying the SYN signal only by a prescribed time and the OR means 4 for finding out OR between the separated SYN signal and the delayed SYN signal. Since OR operation between the signal delayed by a delay line 3 having a delay time corresponding to about 10 to 20% of a picture element period and the output signal of a comparator 2 is obtained by the OR circuit 4, a horizontal SYN signal removing a false horizontal SYN signal due to undershooting can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a synchronization signal separation circuit for hard copy devices and the like.

[Prior Art] The configuration of a conventional example will be explained with reference to FIGS. 3 and 4.

3 and 4 are a circuit diagram showing a conventional synchronization signal separation circuit disclosed in, for example, Japanese Patent Application Laid-Open No. 2-22976, and a block diagram showing an input section of a hard copy device using the synchronization signal separation circuit. It is.

In FIG. 3, a conventional synchronizing signal separation circuit (1) consists of a comparator (2) whose inverting input terminal is connected to an input terminal (10) and whose output terminal is connected to a PLL circuit (11).
It consists of

In FIG. 4, the input section of a hard copy device using a conventional synchronization signal separation circuit (1) includes an input terminal (10),
PLL circuit (11), image memory control circuit (12), input terminal (12), A/D converter (14), image memory (15), PLL lock determination circuit <16>, D/A converter (17), Operation 777 (18), CPU (
20), ROM (21), RAM (22), input port (23), output port (24), standard image memory (25)
) and an address/data bus (26).

A G signal including a synchronization signal of the video signal is input to the input terminal (10), and the PLL circuit (11) is connected to the output side of the synchronization signal separation circuit (1) to generate a sampling clock and control the image memory. The circuit (12) is a PLL circuit (
11) to control the address of the image memory (15).

Further, a video signal consisting of RGB is input to the input terminal (13), and an A/D converter (14) is connected to this input terminal (13) to digitally convert the video signal and output image data. A memory (15) stores the image data.

The PLL lock determination circuit (16) outputs a phase difference pulse between a signal obtained by dividing and reorganizing the sampling clock generated by the PLL circuit (11) by a multiple and the horizontal synchronization signal detected by the synchronization signal separation circuit (1). A D/A converter (17) that determines the PLL lock state, and indicates the PLL lock state when there is no phase difference output.
converts the digital value corresponding to the threshold of the horizontal synchronization signal set from CPtJ (20> to the output port (24)) into an analog value, and the operational amplifier (18) amplifies the analog value to obtain the threshold voltage. as comparator (2)
is supplied to the non-inverting input terminal of

ROM (21) stores programs and tables, and R
A M (22) stores data and inputs (
23) outputs the output of the PLL lock determination circuit (16) to the CPU.
(20), and the output port (24) is the CPU (2
The standard image memory (25) stores the image data of the test pattern, and each is interconnected by an address/data bus (26). ing.

Next, the operation of the conventional example described above will be explained with reference to FIG.

FIG. 5 is a timing chart showing the operation of a conventional synchronizing signal separation circuit.

In FIG. 5, (a) shows the video signal input to the inverting input terminal of the comparator (2), and (b) shows the output waveform of the comparator (2).

In the case of a good video signal whose waveform is not extremely distorted, the threshold of the comparator (2) can be set to the optimal threshold voltage, so the horizontal synchronization signal can be correctly separated by the comparator (2). can do.

That is, by sequentially changing the threshold voltage of the comparator (2), a threshold voltage range in which the PLL lock state occurs is determined, and by further sequentially changing the threshold voltage within this threshold voltage range, the image memory ( The optimal threshold voltage was determined based on the image data in 15).

However, as shown in Figure 5(a), in the case of a video signal with extremely large undershoot (or overshoot), as shown in Figure 5(b), the optimal threshold value of comparator (2) is Unable to determine the voltage, the PLL circuit (11
), and the PLL circuit (11)' is disturbed.

As a result, the output image of the hard copy device becomes distorted.

[Problems to be Solved by the Invention] The conventional synchronizing signal separation circuit as described above has a problem in that when the undershoot is large, the undershoot is detected as a horizontal synchronizing signal.

The present invention was made to solve the above-mentioned problems, and an object of the present invention is to provide a synchronization signal separation circuit that can remove false synchronization signals due to undershoot.

[Means for Solving the Problems] A synchronizing signal separation circuit according to the present invention includes the following means.

[1] Signal separation means for separating synchronization signals based on a threshold value.

[2] Delay means for delaying the synchronization signal by a predetermined time.

[3] OR means for calculating the logical sum of the separated synchronization signal and the delayed synchronization signal.

[Operation] In the present invention, the signal separating means separates the synchronizing signal based on a threshold value.

Further, the synchronization signal is delayed by a predetermined time by the delay means.

Then, the logical sum means performs the logical sum of the separated synchronizing signal and the delayed synchronizing signal.

[Embodiment] The configuration of an embodiment of the present invention will be described with reference to FIG.

FIG. 1 is a circuit diagram showing an embodiment of the present invention, and the comparator (2) is exactly the same as that of the conventional circuit.

In FIG. 1, one embodiment of the present invention has exactly the same circuit as the conventional circuit described above, a delay line (3) connected to the output terminal of the comparator (2), and one input side of the delay line (3) connected to the output terminal of the comparator (2). The OR circuit (4) is connected to the in (3), the other input side is connected to the output terminal of the comparator (2), and the output side is connected to the PLL circuit (11).

Next, the operation of the embodiment described above will be explained with reference to FIG.

FIGS. 2(a), (b), (c) and (d) are timing charts showing the operation of one embodiment of the present invention.

In Figure 2, (a) shows the video signal input to the inverting input terminal of comparator (2), (b) shows the output waveform of comparator (2), and (.) shows the delay line ( 3), and the diagram (d) shows the output waveform of the OR circuit.

2nd G? by comparator (2)? The signal separated by the threshold value shown in I(a) is regarded as a horizontal synchronizing signal even undershoot as shown in FIG. 1(b). Therefore,
When the signal delayed by the delay line (3) having a delay time of about 10 to 20% of the pixel period by the OR circuit (4) and the output signal of the comparator (2) are logically summed, the result shown in FIG. As shown in d), a horizontal synchronization signal from which false horizontal synchronization signals due to undershoot have been removed is obtained.

As mentioned above, one embodiment of the present invention includes the delay line (3) and the OR circuit (4), so the video (
This is a synchronization signal that is a composite of video (image) signals, and it is possible to separate the normal synchronization signal even if the video signal has an undershoot, and produces a good output image when used in a hard copy device. It has the effect that it can be obtained.

Incidentally, in the above description, the case where the present invention is used in a hard copy device has been described, but it goes without saying that it can also be used in other devices such as a CRT device.

[Effects of the Invention] As explained above, the present invention includes a signal separation means for separating a synchronization signal based on a threshold value, a delay means for delaying the synchronization signal by a predetermined time, and a signal separation means for separating the synchronization signal based on a threshold value, a delay means for delaying the synchronization signal by a predetermined time, and a signal separation means for separating the synchronization signal based on a threshold value. Since the synchronization signal is provided with an OR means for calculating the logical sum with the synchronization signal, it is possible to eliminate false synchronization signals due to undershoot.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of this invention, FIG. 2 is a timing chart showing the operation of an embodiment of this invention,
Fig. 3 is a circuit diagram showing a conventional synchronous signal separation circuit, Fig. 4 is a block diagram showing the input section of a hard copy device using the conventional synchronous signal separation circuit, and Fig. 5 is a circuit diagram showing a conventional synchronous signal separation circuit. FIG. 3 is a timing chart diagram showing the operation. In the figure, (IA) ... synchronous signal separation circuit, (2) ...
Comparator, (3)...delay line, (4)...OR circuit. In each figure, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] signal separation means for separating the synchronization signals based on a threshold;
A synchronization signal separation circuit comprising: delay means for delaying the synchronization signal by a predetermined time; and OR means for calculating the logical sum of the separated synchronization signal and the delayed synchronization signal.