JP2766080B2 - Sync separation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sync separation circuit built in a TV receiver or the like.

[0002]

2. Description of the Related Art EDTV (Extended Definition Televi)
In a digital television receiver which has advanced image quality, such as a home video recorder, a clock synchronized with a horizontal synchronizing signal is generated, and a signal based on this clock is generated. Processing is performed. Therefore, in EDTV and the like, how accurately the horizontal synchronizing signal can be separated from the video signal greatly affects the performance.

[0003] Separation of the synchronization signal as described above is conventionally performed through a comparator 21 as shown in FIG. An input video signal is input to the comparator 21 through a video input terminal 22, and a threshold voltage fixed to a predetermined voltage value is supplied to a threshold input terminal 23. As shown in FIG. 5 (a), this threshold voltage is substantially intermediate between the pedestal level P of the input video signal and the lowest sync tip level S 'in the synchronous signal portion Sh having a square wave shape. The output synchronization signal shown in FIG. 4B is output through the synchronization signal output terminal 24 in FIG. 4 in accordance with the input period of the video signal lower than the threshold level.

[0004]

However, the output signal of a home-use VTR or the like has a poor S / N ratio.
V, a problem arises in that the synchronization separation characteristic sufficient to exhibit its performance cannot be obtained. That is, as shown in FIG. 6, the S / N of the video signal is poor and the synchronization signal portion S
When noise of a high frequency is also superimposed on h, as shown in FIG. 7, a shift occurs in the timing of slicing at the threshold value due to the influence of the noise. For this reason, it is impossible to separate the synchronization signal accurately corresponding to the synchronization signal part Sh.

On the other hand, in order to cope with the above-described problem, it is conceivable to provide a low-pass filter (LPF) 32 in a stage preceding the comparator 31 as shown in FIG. However, such a low-pass filter 32 removes noise from a signal on which high-frequency noise is superimposed as shown in FIG. 9 and, at the same time, as shown in FIG. The waveform itself of the signal part Sh is distorted. Conventionally, for a waveform in which such a distortion has occurred, a threshold value accurately corresponding to the original falling and rising edges of the synchronization signal portion Sh cannot be set.
Therefore, even in this case, accurate separation of the synchronization signal cannot be achieved.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned conventional problems, and has as its object to provide a synchronization signal inherently for an input signal having a poor S / N such as an output from a home VTR. Another object of the present invention is to provide a synchronization separation circuit capable of accurately extracting the synchronization timing of the synchronization.

[0007]

SUMMARY OF THE INVENTION Accordingly, the synchronous separating circuit of the present invention provides a signal corresponding to a period between respective intersections where the falling and rising of an input signal having a substantially square wave cross a threshold level. A sync separation circuit provided with an output comparator detects a low-pass filter provided on an input line to the comparator, and detects a pedestal level and a sync tip level of an input signal after passing through the low-pass filter. Pedestal level detecting means and sync chip level detecting means, and an arithmetic expression for obtaining a substantially intermediate level between the pedestal level of the input signal before passing through the low-pass filter and the sync chip level from each detection level of both detecting means Threshold value for performing an operation based on the threshold value and setting the operation result as the threshold level of the comparator. It is characterized by a constant means.

[0008]

According to the above arrangement, an input signal forming a substantially square wave is once input to the comparator through the low-pass filter. Therefore, the noise component is removed at the time of passing through the low-pass filter, and the input signal is input to the comparator as a waveform distorted by removing the harmonic component. However, in the above configuration, an operation for obtaining a substantially intermediate level between the pedestal level and the sync tip level of the input signal before passing through the low-pass filter from the pedestal level and the sync tip level in the waveform in which the distortion has occurred. The formula is set in the threshold setting circuit.

In other words, if a series of synchronization signal portions in an input signal is regarded as a periodic function of a square wave that can be expanded by a Fourier series, a waveform from which a harmonic component after passing through a low-pass filter is removed is a part of the Fourier series. It corresponds to the sum function. Therefore, from the nature of the function of the partial sum near the discontinuity point in the Fourier series, the waveform after passing through the low-pass filter also passes through each intermediate point between the fall and the rise in the original synchronous signal portion before passing, and The predetermined relationship is maintained between the difference between the pedestal level before and after passing through the low-pass filter and the sync tip level. Based on such a relationship, the threshold value for slicing the waveform after passing through the low-pass filter at a timing substantially matching each of the falling and rising points of the synchronization signal section before passing through the low-pass filter. Can be set from the pedestal level and the sync tip level of the waveform after passing through the low-pass filter.

The operation based on the operation expression thus set is automatically performed in the threshold value setting circuit, and the threshold value is set in the comparator based on the result. Even when a video signal with a poor / N is input, accurate synchronization signal separation can be performed without being affected by noise.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to FIGS.

As shown in FIG. 1, a low-pass filter (LPF) 1 is provided in the synchronization separation circuit of the present embodiment, and a video signal is input to the low-pass filter 1 through a video signal input terminal 2. You. The low-pass filter 1 removes high-frequency noise in a video signal input to the low-pass filter 1, and also applies a band limitation to the video signal itself so that its high-frequency component is removed. The output signal from the low-pass filter 1 is input to a comparator 3 and further input to a pedestal level detection circuit (pedestal level detection means) 4 and a sync tip level detection circuit (sync tip level detection means) 5, respectively. Is done.

The pedestal level detection circuit 4 detects the pedestal level in the video signal waveform after passing through the low-pass filter 1, while the sync tip level detection circuit 5 detects the pedestal level in the synchronization signal portion of the video signal waveform. Sync chip level detection is performed. Then, the pedestal level and the sync tip level detected by the two circuits 4 and 5 are input to a threshold setting circuit (threshold setting means) 6. Is performed to generate a threshold voltage. This threshold voltage is
It is input to the comparator 3 as a comparison reference voltage.
In this comparator 3, the low-pass filter 1
A period of a voltage level lower than the above-described threshold voltage is extracted from the video signal input from, and a corresponding signal is output to the synchronization signal output terminal 7 as a synchronization signal during this period.

Next, an arithmetic expression set in the threshold value setting circuit 6 will be described.

This arithmetic expression is obtained by applying the property of the Fourier series. That is, as shown in FIG. 2, when a waveform signal in which the synchronization signal portions 8 in the video signal are connected is regarded as a periodic function of a square wave and is represented by F (t),
(T) can be Fourier-series expanded, and its expression is Becomes Here, in equation (1), when the value of k is cut off at a certain finite value N, the Fourier series has the following properties near the discontinuous point.

(A) The Fourier series converges at the discontinuous point to the average value of the signals on both sides thereof. (B) The partial sum of the Fourier series shows a ripple shape, and the peak value of the amplitude of the ripple does not decrease as N increases, and its magnitude is 18% of the height of the discontinuity (Gibbs's phenomenon).

On the other hand, in the synchronous separation circuit of the present embodiment, the noise component is removed by passing the video signal through the low-pass filter 1. At the same time, the harmonic component is removed from the input video signal. The output waveform is output. This is represented by a function of a partial sum in which the value of k is truncated by a certain finite value in the above equation (1). Therefore, the waveform after passing through the low-pass filter 1 is represented by the above (A) · ( It has the property of B).

That is, as shown in FIG. 3, the signal 11 that has passed through the low-pass filter 1 has a square wave shape before passing through the low-pass filter 1 by removing the harmonic components as described above. Although the waveform becomes blunted with respect to the original synchronization signal section 10, due to the above-described property (A), each of the intermediate points C and C at the falling and rising points which are discontinuous points in the original synchronization signal section 10 is determined. It becomes the waveform which passes each. Therefore, the voltage level at these intermediate points C and C is set as the threshold value X, and the signal 1 after passing through the low-pass filter 1 is set.
By outputting a signal corresponding to the period between the intersections C and C where the falling and rising of 1 intersect the threshold value X, the waveform after passing through the low-pass filter 1 is reduced. Even if this is the case, it is possible to obtain a synchronization signal accurately corresponding to the fall and rise of the original synchronization signal section 10.

According to the characteristic (B), the threshold value X is determined by the signal 11 after passing through the low-pass filter 1.
Can be obtained by the following calculation. That is, if the pedestal level in the signal 11 after passing through the low-pass filter 1 is P, the sync tip level is S, and the sync tip level in the original synchronization signal section 10 is S ′, X = (P + S ′) / 2 Since the relationship of P−S = 1.18 (P−S ′) holds, the threshold value X is obtained by the following equation: X = (1.36P + S) /2.36 (2)

Therefore, an operation based on the above equation (2) is performed by the threshold value setting circuit 6 to generate a voltage obtained as a result of the operation, and this is input to the comparator 3 as the threshold value X. As a result, the comparator 3
Thereafter, based on the threshold value X, a synchronization signal that more accurately matches the original falling and rising timings of the synchronization signal section 10 is output to the synchronization signal output terminal 7.

As described above, in the above-described embodiment, the pedestal level P and the sync tip level S are detected for the signal that has passed through the low-pass filter 1 and has been removed from noise and has a waveform that is distorted. , Both detection levels PS
Thus, the comparator 3 outputs a synchronization signal that more accurately matches the fall and rise of the original synchronization signal section 10 before passing through the low-pass filter 1. That is,
Since the relationship based on the properties (A) and (B) is maintained between the original synchronization signal section 10 and the waveform of the signal 11 after passing through the low-pass filter 1, the waveform after passing through the low-pass filter 1 By a simple calculation based on the pedestal level P and the sync tip level S in the signal 11 of FIG. 1, a synchronization signal that accurately corresponds to the original synchronization signal unit 10 is output without being affected by noise. As a result, for example, ED
By incorporating the above-mentioned sync separation circuit in a TV that has advanced image quality such as a TV, the S / V can be transmitted from a home VTR or the like.
Accurate synchronization separation is performed even in the case where a video signal with a bad N is input, whereby the original performance of the EDTV is sufficiently exhibited, and a good high-quality image can be obtained.

[0022]

As described above, the synchronization separating circuit of the present invention comprises a low-pass filter provided on an input line to a comparator, a pedestal level of an input signal after passing through the low-pass filter, and a sync chip. A pedestal level detecting means and a sync tip level detecting means for respectively detecting a level, and a level substantially intermediate between the pedestal level and the sync tip level of the input signal before passing through the low-pass filter from the respective detection levels of the two detecting means. And a threshold setting means for performing an operation based on an operation expression for calculating the threshold value and setting the operation result as a threshold level of the comparator.

Thus, the signal after passing through the low-pass filter from which noise has been removed and the waveform of which has been distorted substantially matches the falling and rising points of the synchronous signal portion before passing through the low-pass filter. At this timing, a threshold value for slicing the waveform after passing through the low-pass filter is automatically set. As a result, even when a video signal having a poor S / N is input, such as a home VTR, it is possible to accurately separate the synchronization signal without being affected by noise.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a sync separation circuit according to an embodiment of the present invention.

FIG. 2 is a schematic diagram of a waveform of a video signal in which synchronization signal portions are connected.

FIG. 3 is a schematic diagram showing a signal waveform after passing through a low-pass filter by a solid line for explaining a threshold value set in a comparator in the sync separation circuit.

FIG. 4 is a block diagram showing a configuration of a conventional sync separation circuit.

FIG. 5 is a timing chart showing a relationship between an input video signal to the sync separation circuit and a sync signal separated from the signal.

FIG. 6 is an enlarged view of a synchronization signal portion in the input video signal.

FIG. 7 is an enlarged schematic diagram of a portion D in FIG. 6;

FIG. 8 is a block diagram showing a configuration of another conventional synchronization separation circuit.

FIG. 9 is an enlarged view of a synchronization signal portion in an input signal to the synchronization separation circuit.

FIG. 10 is a schematic diagram of a waveform after passing through a low-pass filter in the sync separation circuit.

[Explanation of symbols]

Reference Signs List 1 low-pass filter 3 comparator 4 pedestal level detection circuit (pedestal level detection means) 5 sync tip level detection circuit (sync tip level detection means) 6 threshold setting circuit (threshold setting means)

Claims (1)

(57) [Claims] 1. A synchronizing separation circuit comprising a comparator for outputting a signal corresponding to a period between intersections where the falling and rising of an input signal having a substantially square wave cross a threshold level. A low-pass filter provided on an input line to the comparator, pedestal level detection means and sync tip level detection means for detecting a pedestal level and a sync tip level of the input signal after passing through the low-pass filter, respectively. From each detection level in the detection means, by performing an operation based on an arithmetic expression for obtaining a substantially intermediate level between the pedestal level and the sync tip level of the input signal before passing through the low-pass filter,
And a threshold setting means for setting a result of the operation as a threshold level of the comparator.