JPH0479369A - Nonvolatile semiconductor memory - Google Patents

Abstract

PURPOSE:To obtain a highly integrated EEPROM by composing a memory cell using a memory transistor having a charge storage layer and a control gate by using the sidewall of a columnar semiconductor layer isolated by lattice foirelike grooves. CONSTITUTION:A plurality of columnar p-type silicon layers 2 isolated by lattice foirelike grooves 3 are arranged in a matrix, and the layers 2 are formed in memory cell regions. That is, oxide films 4 are buried in the bottoms of the grooves 3, and floating gates 6 are formed at sidewalls through a tunnel oxide film 5 around the layer 2. A control gate 8 is formed at the outside through an interlayer insulating film 7. The gates 8 are continuously arranged at a plurality of memory cells of one direction as word lines ML. A common source diffused layer 9 of the cell is formed in the bottom of each groove 3, and a drain diffused layer 10 of each cell is formed on the upper surface of the layer 2. Al wirings 12 to become bit lines BL for commonly connecting the layer 10 of a direction crossing the lines ML are arranged.

Description

Detailed Description of the Invention [Objective of the Invention (Industrial Application Field) The present invention relates to an electrically rewritable non-volatile semiconductor memory device (EEFROM) using a memory transistor having a charge storage layer and a control gate. ) regarding.

(Prior art) As an EEFROM memory cell, a MOS has a charge storage layer and a control gate in the gate part, and uses tunnel current to inject charges into the charge storage layer and release charges from the charge storage layer) A transistor structure is known. In this memory cell, the difference in threshold voltage due to the difference in the charge storage state of the charge storage layer is stored as data "0" and "1". For example, using a floating gate as a charge storage layer
In the case of a channel memory cell, to inject electrons into the floating gate, the source, drain diffusion layers, and substrate are grounded and a high positive voltage is applied to the control gate.

At this time, electrons are injected into the floating gate from the substrate side by a tunnel current. This electron injection moves the threshold voltage of the memory cell in the positive direction.

To emit electrons from the floating gate, the control gate is grounded and a high positive voltage is applied to either the source, drain diffusion layer, or substrate. At this time, electrons are emitted from the floating gate to the substrate side by a tunnel current. Due to this electron emission, the threshold voltage of the memory cell moves in the negative direction.

In the above operations, the capacitive coupling relationship between the floating gate, control gate, and substrate is important in order to efficiently perform electron injection and emission, that is, writing and erasing. In other words, the larger the capacitance between the floating gate and the control gate,
The potential of the control gate can be effectively transmitted to the floating gate, making writing and erasing easier. However, with recent advances in semiconductor technology, especially advances in microfabrication technology,
EPROM memory cells are rapidly becoming smaller and larger in capacity. Therefore, an important problem is how to secure a large capacitance between the floating gate and the control gate even though the memory cell area is small.

In order to increase the capacitance between the floating gate and the control gate, it is necessary to thin the gate insulating film between them, increase its dielectric constant, or increase the opposing area between the floating gate and the control gate. It is. However, making the gate insulating film thinner has a limit in terms of reliability. One way to increase the dielectric constant of the gate insulating film is to use, for example, a silicon nitride film instead of a silicon oxide film, but this also poses problems mainly in terms of reliability and is not practical. Therefore, in order to ensure sufficient capacitance, it is necessary to ensure that the overlapping area between the floating gate and the control gate is equal to or greater than a certain value. This becomes an obstacle in increasing the capacity of the EEPROM by reducing the area of the memory cell.

Furthermore, since a high voltage is applied to the memory cells during writing and erasing, it is necessary to ensure element isolation. Therefore, in the normal LOCO5 method, the area of the element isolation region becomes large, which also becomes a cause of hindering the increase in the capacity of EEPROM.

(Problem to be solved by the invention) As mentioned above, in EEPROM, it is difficult to reduce the area occupied by the memory cell and to ensure a sufficiently large capacitance between the floating gate and the control gate. was there.

SUMMARY OF THE INVENTION An object of the present invention is to provide a large-capacity EEFROM with high writing and erasing efficiency that solves these problems.

[Structure of the Invention (Means for Solving the Problem) The EEPROM according to the present invention utilizes the side walls of a plurality of columnar semiconductor layers arranged in a matrix and separated by checkered grooves in a semiconductor substrate. A memory transistor is configured. That is, the memory transistor includes a drain diffusion layer formed on the top surface of each columnar semiconductor layer, a common source diffusion layer formed at the bottom of the trench, and a charge storage layer surrounding at least a portion of the periphery of each columnar semiconductor layer. The semiconductor device is constructed with a control gate, and the control gates are continuously arranged on a plurality of columnar semiconductor layers in one direction to form a control gate line. Also, multiple memory lines in the direction crossing the control gate line
A bit line is provided connected to the drain diffusion layer of the transistor.

In the EEF ROM according to the present invention, the charge storage layer and the control gate of the memory transistor described above are formed under the columnar semiconductor layer, and the charge storage layer and the control gate of the above-mentioned memory transistor are superimposed on the columnar semiconductor layer, and at least part of the periphery thereof is formed on the top of the columnar semiconductor layer. A selection gate transistor having a gate electrode formed so as to surround the portion is provided.

(Function) Since the memory cell of the EEFROM according to the present invention has a charge storage layer and a control gate formed surrounding the columnar semiconductor layer using the sidewalls of the columnar semiconductor layer, the charge storage layer and control gate can be controlled in a small occupied area. It is possible to secure a sufficiently large capacitance between the gates. Further, drain diffusion layers connected to the bit lines of each memory cell are formed on the upper surface of the columnar semiconductor layer, and are completely electrically isolated by a groove. Furthermore, the element isolation region can be made smaller and the memory cell size can be reduced. Therefore, a large-capacity EEFROM that integrates memory cells with excellent write and erase efficiency
can be obtained.

(Example) Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a plan view showing a memory cell array of an EEF ROM according to an embodiment, and FIGS. 2(a) and 2(b) are sectional views taken along line AA' and line BB' in FIG. 1, respectively. . In this embodiment, a p-type silicon substrate 1 is used, on which a plurality of columnar p-type silicon layers 2 separated by checkered grooves 3 are arranged in a matrix, and each of these columnar silicon layers 2 has a memory cell area. It becomes. That is, an oxide film 4 of a predetermined thickness is embedded in the bottom of the trench 3, a floating gate 6 is formed on the side wall via a tunnel oxide film 5 so as to surround the columnar silicon layer 2, and an interlayer insulating film is formed on the outside of the floating gate 6. A control gate 8 is formed through the film 7. As shown in FIGS. 1 and 2(b), the control gates 8 are continuously arranged for a plurality of memory cells in one direction, and are connected to the control gate line, that is, the word line WL (W
LI, WL2,...). At the bottom of the trench 3, a common "source diffusion layer 9" of the memory cells is formed.
A drain diffusion layer 10 for each memory cell is formed on the upper surface of each columnar silicon layer 2 . The substrate of the memory cell thus formed is covered with a CVD oxide film 11,
A contact hole is opened in this, and the bit line BL (BLI) commonly connects the drain diffusion layers 10 of the memory cells in the direction crossing the word line WL.

BL2. ...) is arranged. When patterning the control gate lines, a PEP mask is formed at the position of the columnar silicon layer at the end of the cell array, and a contact portion 14 made of a polycrystalline silicon film continuous with the control gate line is left on the surface of the mask. An) wiring 13, which will become a word line, is brought into contact here with an Afl film formed at the same time as the bit line BL.

A specific manufacturing process example for obtaining such a structure is shown in Part 3.
This will be explained with reference to FIGS. (a) to (e). Figure 3(a)~
(e) is a cross-sectional process diagram corresponding to FIG. 1(a). A p-type silicon layer 2 with a low impurity concentration is epitaxially grown on a p-type silicon substrate 1 with a high impurity concentration, a mask layer 21 is deposited on its surface, and a photoresist pattern 22 is formed by a known PEP process. The mask layer 21 is etched using a etchant (FIG. 3(a)). Then, using the mask layer 21, the silicon layer 2 is etched by a reactive ion etching method to form checkered grooves 3 deep enough to reach the substrate 1. Thereby, the silicon layer 2 is separated into a plurality of islands in a columnar shape. Thereafter, a silicon oxide film 23 is deposited by CVD and left on the side walls of each columnar silicon layer 2 by anisotropic etching. Then, by ion-implanting n-type impurities, a drain diffusion layer 10 is formed on the upper surface of each columnar silicon layer 2, and a common source diffusion layer 9 is formed at the bottom of the trench (see FIG. 3).
b)).

Thereafter, the oxide film 23 around each columnar silicon layer 2 is etched away by isotropic etching, and then channel ions are implanted into the side walls of each silicon layer 2 using oblique ion implantation as required.

Instead of channel ion implantation, an oxide film containing boron may be deposited by CVD and boron diffusion from the oxide film may be utilized. Then, a CVD silicon oxide film 4 is deposited.
This is etched by isotropic etching and embedded in the bottom of the groove 3 to a predetermined thickness. Thereafter, a tunnel oxide film 5 of, for example, about 100 layers or less is formed around each silicon layer 2 by thermal oxidation, and then a first layer polycrystalline silicon film is deposited.

This first layer polycrystalline silicon film is etched by anisotropic etching to form floating gates 6 leaving only on the side walls of each silicon layer 2 (FIG. 3(C)).

Next, an interlayer insulating film 7 is formed on the surface of the floating gate 6 formed around each columnar silicon layer 2. This interlayer insulating film 7
For example, it is assumed that the film is an ONO film. Specifically, floating gate 6
After oxidizing the surface to a predetermined thickness, a silicon nitride film is deposited by plasma CVD and the surface is thermally oxidized to form an ONO film. Then, a second layer polycrystalline silicon film is deposited and etched by anisotropic etching to form a control gate 8 (FIG. 3(d)).
. At this time, by setting the interval between the columnar silicon layers 2 to a predetermined value or less in the vertical direction in FIG. is formed as. At one end of the control gate line, a polycrystalline silicon film is left on the columnar silicon layer as a contact portion 14 with the AΩ wiring using a mask.

Finally, after depositing a CVD oxide film 11 on the entire surface and performing a planarization process if necessary, a contact hole is opened in this and the bit line 11 is connected to the drain diffusion layer 10 of each memory cell.
2, and ρ wirings 12 and 13 are formed to serve as word lines connected to the control gate lines (FIG. 3(e)).

The operation of the EEFROM according to this embodiment will be briefly explained. By applying a positive potential to the selected word line and selected bit line, a channel current flows in the selected memory cell, and hot electrons generated near the drain are injected into the floating gate.

This moves the threshold value of that memory cell in the positive direction. This is, for example, data writing.

To erase data, set the selected word line to 0■, apply a positive potential to the selected bit line, and transfer the electrons of the floating gate to the substrate side (FN)
Pull it out by tunneling. This causes the threshold value of the memory cell to move in the negative direction.

In data reading, "0" and "1'" are determined by applying a predetermined read potential to the word line and determining whether a cell current flows or not.

It is also possible to use FNN tonking for both data writing and erasing. In this case, writing is performed by applying a positive potential to the selected word line, applying OV to the selected bit line, and transferring electrons from the substrate side to the floating gate of the selected memory cell.
Inject by NN tonkung.

According to this embodiment, a memory cell is constructed in which columnar silicon layers are arranged with the bottoms of lattice striped grooves as isolation regions, and floating gates are formed to surround the columnar silicon layers. A highly integrated EEPROM with a small cell occupation area can be obtained. Furthermore, although the area occupied by the memory cell is small, a sufficiently large capacitance between the floating gate and the control gate can be ensured.

In the example, the control gates of each memory cell were formed so as to be continuous in one direction without using a mask. This is only possible if the arrangement of the columnar silicon layers is not symmetrical. In other words, by making the distance between adjacent columnar silicon layers in the word line direction smaller than that in the bit line direction, control gate lines that are separated in the bit line direction and connected in the word line direction can be automatically obtained without a mask. .

On the other hand, for example, if the columnar silicon layers are arranged symmetrically, a PEP process is required.

Specifically, a second layer polycrystalline silicon film is deposited thickly, subjected to a PEP process, and then selectively etched so as to leave it in the areas where it is to be continuous as a control gate line. Next, a third layer polycrystalline silicon film is deposited, and the remaining side walls are etched in the same manner as described in the embodiment. Even if the arrangement of the columnar silicon layers is not symmetrical, continuous control gate lines may not be automatically formed as in the embodiment, depending on the spacing of the arrangement. Even in such a case, control gate lines that are continuous in the direction may be formed by using the mask process as described above.

In addition, although a memory cell with a floating gate structure was used in the example, the charge storage layer does not necessarily have to have a floating gate structure. The present invention is also effective in such cases.

FIG. 4 is a sectional view corresponding to FIG. 2<a) of an embodiment using such a memory cell of MNOS structure. Portions corresponding to those in FIG. 2 are given the same reference numerals and detailed explanations will be omitted. The laminated insulating film 24 serving as a charge storage layer has a laminated structure of a tunnel oxide film and a silicon nitride film, or a structure in which an oxide film is further formed on the surface of the nitride film.

FIG. 1 shows the case where the columnar silicon layer 2 is columnar, that is, the upper surface is circular. The outer shape of this columnar silicon layer does not have to be cylindrical; for example, as shown in FIG. 5, the columnar silicon layer may be formed in a rectangular pattern. However, if the size of the columnar silicon layer is small close to the processing limit, even if the design pattern is a square, the corners will be rounded, resulting in a pattern substantially similar to that shown in FIG. 1.

By the way, in the 1 transistor/1 cell configuration as in the above embodiment, when the memory transistor is in an over-erased state, that is, when the read potential is OV and the threshold value or negative state is reached, a cell current flows even if it is not selected. This is inconvenient. To reliably prevent this, it is desirable to use a selection gate transistor in addition to the memory transistor. Such an embodiment will be described below.

FIG. 6 is a plan view of an EEPROM of such an embodiment, and FIGS. 7(a) and 7(b) are respectively taken along line AA' in FIG.
, is a BB' cross-sectional view. In these figures, parts corresponding to those in the previous embodiment are designated by the same reference numerals as those in the previous embodiment, and detailed description thereof will be omitted. In the plan view of FIG. 6, the selection gate line in which the gate electrodes of the selection gate transistors are continuously formed is not shown because it would be complicated.

As in the previous embodiment, columnar silicon layers 2 are separated by grooves 3 and arranged in an array, with a drain diffusion layer 10 formed on the top surface of each silicon layer 2 and a common source diffusion layer 9 at the bottom of the groove 3. Ru. In the memory cell, a floating gate 6 is formed under such a columnar silicon layer 2 through a tunnel oxide film 5, and a control gate 8 is further formed through an interlayer insulating film 7, as in the previous embodiment. A memory transistor is configured. And on the top of the columnar silicon layer 2,
A gate electrode 32 is disposed via a gate oxide film 31 so as to surround the memory transistor, forming a selection gate transistor. The gate electrode 32 of this transistor, like the control gate 8 of the memory cell, is disposed continuously in the same direction as the control gate line and becomes a selection gate line. In this way, the memory transistor and the selection gate transistor are embedded in the trench in an overlapping state. The control gate line has one end left as a contact part 14 on the surface of the silicon layer as in the previous embodiment, and the selection gate line also leaves a contact part 15 on the silicon layer at the end opposite to the control gate.
These are connected to a word line WL and a control gate line CG, respectively.
The A11 wirings 13 and 16 are in contact with each other.

FIGS. 8(a) to 8(g) are cross-sectional views corresponding to FIG. 7(a) showing the manufacturing process of the EEPROM of this embodiment.

Using a wafer in which a p-type silicon layer 2 is epitaxially grown on a p-type silicon substrate 1, a mask is formed and lattice striped grooves 3 are formed by anisotropic etching, and a drain diffusion layer 10 is formed on the upper surface of each silicon layer 2. ．． The process is the same as the previous example until the common source diffusion layer 9 is formed at the bottom of the trench (
Figure 8(a)(b)). After that, after forming the tunnel oxide film 5, a first polycrystalline silicon film is deposited and etched by anisotropic etching to leave it on the lower sidewall of the columnar silicon layer 2, forming a floating structure surrounding the silicon layer 2. A gate 5 is formed (FIG. 8(C)).

Next, after forming the interlayer insulating film 6 in the same manner as in the previous embodiment,
A second polycrystalline silicon film is deposited and etched by anisotropic etching to form a control gate 8 under the columnar silicon layer 2 (FIG. 8(d)). The control gate 8 is continuous in one direction and becomes a control gate line. After etching and removing unnecessary interlayer insulating film 7 and tunnel oxide film 2 thereunder, CVD silicon oxide film 11
1 is deposited and etched to fill the trench 3 halfway, that is, until the floating gate 7 and control gate 8 of the memory cell are hidden (FIG. 8(e)). Thereafter, a gate oxide film 31 of less than 200 layers is formed by thermal oxidation on the exposed columnar silicon layer 2, and then a third layer polycrystalline silicon film is deposited and etched by anisotropic etching to form a MOS transistor. form the gate electrode 32 (
Figure 8(r)). This gate electrode 32 is also continuously patterned in the same direction as the control gate line to become a selection gate line. Although selection gate lines can also be formed continuously using self-aligned lines, this is more difficult than forming control gates 8 of memory cells. This is because the memory transistor section is 2
This is because the selection gate transistor is a single-layer gate, whereas the selection gate transistor is a single-layer gate, and the gate electrode interval between adjacent cells is wider than the control gate interval. Therefore, in order to ensure that the gate electrode 32 is continuous, it must be made into a two-layer polycrystalline silicon structure, and the first polycrystalline silicon film is left only in the part where the gate electrodes are connected in the masking process.
For the next polycrystalline silicon film, the technique of leaving the sidewalls intact can be used.

Note that the control gate line and the selection gate line have contact portions 1 on the upper surface of the columnar silicon layer at different ends.
A mask is formed during etching of the polycrystalline silicon film so that 4.15 is formed.

Finally, a CVD silicon oxide film 112 is deposited, a contact hole is opened, and A and Q are deposited and patterned.
Aρ wiring 12 which becomes the bit line BL. The AI wiring 13 that will become the control gate line CG and the AII wiring 16 that will become the word line WL are formed at the same time (FIG. 8(g)).

FIG. 9(a) shows one of the EEF ROMs of this embodiment.
The cross-sectional structure of the main part of the memory cell is shown replaced with a planar structure, and FIG. 10B also shows an equivalent circuit.

The operation of the EEFROM of this embodiment will be briefly explained using FIG. 9 as follows. First, when hot carrier injection is used for writing, writing is performed on the selected word line W.
A sufficiently high positive potential is applied to L, and a predetermined positive potential is applied to the selection control gate line CG and the selection bit line BL. As a result, a positive potential is transmitted to the drain of the memory transistor Qc via the selection gate transistor Qs, and the memory
Hot carrier injection is performed by flowing a channel current through the transistor Qc. For erasing, the selection control gate CG is set to Ov, a high positive potential is applied to the word line WL and the bit line BL, and electrons from the floating gate are emitted to the drain side. −
In the case of bulk erasing, a high positive potential can be applied to the common source to cause electrons to be emitted to the source side. The read operation is performed by selecting gate transistor Qs by word line WL.
is opened, a read potential of the control gate line CG is applied, and "0" or "1" is determined based on the presence or absence of current.

When FN tunneling is used for electron injection, a high positive potential is applied to the selection control gate line CG and the selected word line WL, the selected bit line BL is set to OV, and electrons are injected from the substrate to the floating gate.

According to this embodiment, since there is a selection gate transistor, there is no malfunction even in the over-erased state.
A ROM is obtained.

By the way, in this embodiment, as shown in FIG. 9(a), there is no diffusion layer between the selection gate transistor Qs and the memory transistor Qc. This is because it is difficult to selectively form a diffusion layer on the side surfaces of a columnar silicon layer. Therefore, in the structure shown in FIGS. 7(a) and 7(b), it is desirable that the isolation oxide film between the gate portion of the memory transistor and the gate portion of the selection gate transistor be as thin as possible. In particular, when using hot electron injection, the thickness of this isolation oxide film must be approximately 300 to 400 mm or less in order to transmit a sufficient "H" level potential to the drain part of the memory transistor. .

In practice, it is difficult to create such a small interval by only filling the oxide film by CVD as described in the previous manufacturing process. Therefore, there is a method in which the floating gate 6 and control gate 8 are exposed in the CVD oxide film filling process, and a thin oxide film is simultaneously formed on the exposed parts of the floating gate 6 and control gate 8 during the gate oxidation process for the selection gate transistor. desirable.

FIG. 10 shows an embodiment in which the memory transistor in the above embodiment has an MNO6 structure similar to the embodiment of FIG.

FIG. 11 shows an example in which the memory transistor and selection gate transistor are reversed in the above embodiment, that is, an example in which the selection gate transistor is formed at the bottom of the columnar silicon layer 2 and the memory transistor is formed at the top. FIG. 7 is a sectional view corresponding to FIG. 7(a) of FIG. This structure in which the selection gate transistor is provided on the common source side can be adopted when a hot electron injection method is used as the write method.

FIG. 12 shows an embodiment in which a NAND type memory cell is formed on one columnar silicon layer. Portions corresponding to those in the previous embodiment are given the same reference numerals as those in the previous embodiment, and detailed description thereof will be omitted. In this embodiment, a selection gate transistor Qsl is formed at the bottom of the columnar silicon layer 2, and three memory transistors Qcl, Qc2 .
A selection gate transistor Qs2 is formed on top of the transistor Qc3.

This structure is basically obtained by repeating the manufacturing process described above.

FIGS. 13(a) and 13(b) are sectional views corresponding to FIGS. 7(a) and 7(b) of the previous embodiment, respectively. In this embodiment, the control gate 8 of the memory transistor and the gate electrode 32 of the selection gate transistor are formed continuously and integrally.

FIGS. 14(a) to 14(e) are sectional views of the manufacturing process of this embodiment. A trench 3 is etched into a wafer similar to that of the previous example using a mask, a source diffusion layer 9 and a drain diffusion layer 10 are formed, and then a tunnel oxide film 5 is formed.
The steps up to forming the floating gate 6 at the bottom of the columnar silicon layer 2 are the same as in the previous embodiment (Figs. 14(a) to 14).
(C)). Thereafter, the interlayer insulating film 7 on the floating gate 6 and the gate oxide film 31 of the selection gate/transistor section are simultaneously formed, for example, by thermal oxidation, and the control gate 8 is formed by depositing a second layer polycrystalline silicon film and anisotropic etching. part and the gate electrode 32 part are formed continuously (FIG. 14(d)
). Then, the entire surface is covered with a CVD oxide film 11, and a contact hole is opened in this to form an AIJ wiring 12 (FIG. 14(e)).

FIG. 15 shows a cross-sectional structure of a main part of the memory cell of this embodiment, corresponding to FIG. 8(a).

The operation of the EEFROM according to this embodiment is basically the same as that of the previous embodiment. However, since the control gate of the memory transistor and the gate electrode of the selection gate transistor are common, in the erase operation, a positive potential is applied to the common source S, and the word line WL (that is, the control gate line CG) is set to 0.
(2) is performed by emitting electrons from the floating gate to the source diffusion layer side.

This embodiment also provides the same effects as the previous embodiment.

In the embodiment described in FIGS. 13 and 14,
Instead of a floating gate structure as a memory transistor, M
It goes without saying that a NO3 structure can be used.

[Effects of the Invention] As described above, according to the present invention, a memory cell using a memory transistor having a charge storage layer and a control gate can be created by utilizing the side walls of a columnar semiconductor layer separated by a lattice groove. By configuring this structure, it is possible to obtain a highly integrated EEPROM that secures a sufficiently large capacitance between the control gate and the charge storage layer, reduces the area occupied by the memory cell, and achieves high integration.

[Brief explanation of drawings]

FIG. 1 is a plan view of an EEFROM according to an embodiment of the present invention, and FIGS. 2(a) and 2(b) are AA' and B--
B' cross-sectional view, Figures 3(a) to (e) are cross-sectional views showing the manufacturing process, Figure 4 is a cross-sectional view showing an EEFROM of an example using the MNO8 structure, and Figure 5 is a cross-sectional view of another example. FIG. 6 is a plan view showing an EEPROM of another embodiment. FIGS. 7(a) and 7(b) are A-A' and B-B in FIG. 6.
Figure 8(a) to (g) are cross-sectional views showing the manufacturing process, Figures 9(a) and (b) are cross-sectional views and equivalent circuit diagrams showing the planar structure, and Figure 10 is a cross-sectional view. Example EEFROM using MNO5 structure
11 is a sectional view showing an EEFROM of an embodiment in which the arrangement of the memory transistor and the selection gate transistor is reversed; FIG. 12 is a sectional view showing an EEPROM of an embodiment with a NAND structure; 13. Figures (a) and (b) show the EEFR of still another example.
A cross-sectional view showing the OM corresponding to FIGS. 7(a) and (b), FIGS. 14(a) to (e) are cross-sectional views showing the manufacturing process, and FIG. 15 is a cross-sectional view showing the planar structure. It is. (d) 1...p-type silicon layer plate, 2...p-type silicon layer, 3...lattice striped groove, 4...silicon oxide film, 5
...Tunnel oxide film, 6...Floating gate, 7...
Interlayer insulating film, 8... Control gate, 9... Common source diffusion layer, 10... Drain diffusion layer, 11... CVD
Oxide film, 12... All wiring (bit line), 13...
・All wiring (word line), 14. 15--Contact portion, 31--Gate oxide film, 32--Gate electrode, 24--Laminated insulating film. (e) Applicant's representative Patent attorney Takehiko Suzue Figure 3 (C) d) Figure, 10 1° (e) (f) Figure Figure 11 Figure 8 (a) (b) Figure Figure 10 (a) (b) <10 (C) (d) Figure 14 Figure (a) (b) (e) Figure 14

Claims (3)

[Claims] (1) A semiconductor substrate, a plurality of columnar semiconductor layers separated by checkered grooves and arranged in a matrix on the semiconductor substrate, a drain diffusion layer formed on the top surface of each columnar semiconductor layer, and a drain diffusion layer formed at the bottom of the groove. a common source diffusion layer, and a charge storage layer and a control gate surrounding at least a part of the periphery of each columnar semiconductor layer, and the control gate is continuously arranged for the plurality of columnar semiconductor layers in one direction. A nonvolatile semiconductor memory device comprising: a plurality of electrically rewritable memory cells; and a bit line connected to the drain diffusion layers of the plurality of memory cells in a direction crossing the control gate line. . (2) a semiconductor substrate; a plurality of columnar semiconductor layers separated by checkered grooves and arranged in a matrix on the semiconductor substrate; a common source diffusion layer formed at the bottom of the groove; and a lower part of each columnar semiconductor layer. A plurality of electrically rewritable memory transistors each having a charge storage layer and a control gate surrounding at least a portion of the periphery of the memory transistor, the control gate of which is disposed continuously on a plurality of columnar semiconductor layers in one direction. and a drain diffusion layer formed on the top surface of each columnar semiconductor layer;
a plurality of select gate transistors each having a gate electrode surrounding at least a part of the upper part of each columnar semiconductor layer, the gate electrode being arranged continuously in the same direction as the control gate line to serve as a word line; A nonvolatile semiconductor memory device comprising: a bit line connected to drain diffusion layers of a plurality of select gate transistors in a direction crossing the control gate line and the word line. (3) a semiconductor substrate, a plurality of columnar semiconductor layers arranged in a matrix and separated by checkerboard grooves on the semiconductor substrate, a common source diffusion layer formed at the bottom of the grooves, and a common source diffusion layer formed at the bottom of each columnar semiconductor layer; A plurality of electrically rewritable memory transistors having a charge storage layer surrounding at least a portion of the periphery and a control gate, the control gates of which are successively disposed on a plurality of columnar semiconductor layers in one direction; , a drain diffusion layer formed on the top surface of each columnar semiconductor layer;
A gate electrode is formed continuously with the control gate so as to surround at least a part of the upper part of each columnar semiconductor layer, and the gate electrode is continuously arranged about the plurality of columnar semiconductor layers in one direction. A non-volatile device comprising: a plurality of selection gate transistors arranged to serve as word lines; and a bit line connected to the drain diffusion layers of the plurality of selection gate transistors in a direction crossing the word lines. semiconductor memory device.