JP2001077219A - Nonvolatile semiconductor storage device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To highly integrate a nonvolatile semiconductor storage device. SOLUTION: A channel 11 is formed at a semiconductor substrate 10. A source region 12 is formed on the surface side of the semiconductor substrate 10 at the bottom part of the channel 11. A drain region 14 is formed on the surface side of the semiconductor substrate 10 so that no channel 11 is formed. A floating gate 30, which is an electric charge accumulating layer is formed on both sides at the sidewall part inside the channel 11. A memory cell transistor is formed in a solid, so that a nonvolatile semiconductor storage device is integrated highly.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device capable of electrically writing / erasing data and a method of manufacturing the same, and more particularly to a nonvolatile semiconductor memory device in which memory cell transistors constitute a ground cell array. The present invention relates to a nonvolatile semiconductor memory device and a method for manufacturing the same.

[0002]

2. Description of the Related Art FIGS. 14 and 15 show a conventional nonvolatile semiconductor memory device having a ground cell array structure.
Among these figures, FIG. 14 is a perspective view three-dimensionally showing a nonvolatile semiconductor memory device in a state where an interlayer insulating film on a word line formed on a semiconductor substrate is removed. FIG. 15 (a)
FIG. 15 is a plan view of the nonvolatile semiconductor device, and FIG. 15B is a cross-sectional view taken along the line AA.

As shown in FIG. 14, an element isolation region 400 formed by a LOCOS (Local Oxidation of Silicaon) method is formed on the surface of a p-type semiconductor substrate 100 in this nonvolatile semiconductor memory device. An element region 410 is formed between the element isolation regions 400. An n ⁺ type drain region 140 and an n ⁺ type source region 120 are formed below the element isolation region 400. That is, the drain region 140 and the source region 120 are formed as impurity diffusion layers of a conductivity type opposite to that of the semiconductor substrate 100.

[0004] The drain region 140 and the source 120 region are continuously connected to memory cells adjacent in the bit line direction. Then, as can be seen from FIG. 15A, the drain region 140 forms the bit line 141, and the source region 120 forms the source line 121.

As can be seen from FIGS. 14 and 15B, a tunnel oxide film 200 having a thickness of about 100 angstroms is formed on the element region 410, and the tunnel oxide film 200 is made of polycrystalline silicon. Floating gate 3
00 is formed. On the floating gate 300, an insulating film 220 having a thickness of about 150 angstroms including an oxide film, a nitride film, and an oxide film is formed. On the insulating film 220, a bit line 141 and a source line 121 are formed. A control gate 320 intersecting with. The control gate 320 is made of polycrystalline silicon, like the floating gate 300. As can be seen from FIG.
The control gate 320 forms the word line 131.

Next, the operation of the nonvolatile semiconductor memory device will be described. When writing data into the memory cell transistors of such a ground cell array, that is, when injecting electrons into the floating gate 300, for example, the bit line 1
6V is applied to 41, 10V is applied to the word line 131, and the source line 121 is grounded. Thus, a channel current flows through the memory cell transistor, and a part of the channel current is injected into the floating gate 300 as hot electrons. The threshold value of the memory cell transistor after electron injection is about 5 to 6V.

When erasing is performed, for example, the bit line 1
41 is opened, the word line 131 is grounded, and 12 V is applied to the source line 121. Or, the bit line 141
Is opened, -9 V is applied to the word line 131, and 3 V is applied to the source line 121. By doing so, the electrons of the floating gate 300 are emitted to the source line 121 (source region 120). After the discharge, the threshold value of the memory cell transistor becomes about 0 to 2V.

When data is read, for example, 3 V is applied to the bit line 141 and the word line 131,
The source line 121 is grounded. By doing so, 1-bit information “0” and “1” are made to correspond to whether or not a current flows through the source line 121. That is, when writing is performed, the threshold value of the memory cell transistor is about 5 to 6 V, and when erasing is performed, the threshold value of the memory cell transistor is about 0 to 2 V.
Therefore, by applying 3 V to the word line 131, for example,
The case where a current flows from the bit line 141 to the source line 121 is made to correspond to “1”, and
The case where no current flows to 1 corresponds to “0”.

[0009]

As can be seen from the above description, since the floating gate 300 is conventionally formed planarly on the surface of the semiconductor substrate 100, there is a limit even if high integration is attempted. Was.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has been made to achieve high integration of a nonvolatile semiconductor memory device by arranging a source line, a bit line, and a charge storage layer in a three-dimensional manner. Aim. That is, high integration is achieved by forming a groove in a semiconductor substrate, forming a source line or a bit line at the bottom of the groove and a part other than the groove, and forming a charge storage layer on a side wall part inside the groove. It is an object of the present invention to provide a nonvolatile semiconductor memory device that can be implemented.

[0011]

In order to solve the above-mentioned problems, a nonvolatile semiconductor memory device according to the present invention comprises a plurality of memory cell transistors capable of storing charges in a charge storage layer and releasing the stored charges. Is a non-volatile semiconductor memory device constituting a ground cell array, wherein one of the bit line and the source line of the ground cell array is formed at the bottom of a groove formed in the semiconductor substrate with a diffusion layer of a conductivity type opposite to that of the semiconductor substrate. The other is formed on the surface side of the semiconductor substrate other than the bottom of the groove by a diffusion layer of a conductivity type opposite to that of the semiconductor substrate, and the charge storage layer is formed on a side wall portion inside the groove.

A nonvolatile semiconductor memory device according to the present invention comprises:
A first conductivity type semiconductor substrate in which a plurality of grooves are formed in parallel on the front surface side, a second conductivity type first region formed in a bottom portion of the groove, and a surface of the semiconductor substrate other than the groove; A second region of the second conductivity type formed in the portion, a charge storage layer formed in a side wall portion inside the trench, and an insulating film on the charge storage layer, the first region, and the second region. And a plurality of conductive layers formed so as to intersect with the plurality of grooves. In this case, the charge storage layer may be formed of polysilicon doped with an impurity.

[0013] A nonvolatile semiconductor memory device according to the present invention comprises:
A first conductivity type semiconductor substrate in which a plurality of grooves are formed in parallel on the front surface side, a second conductivity type first region formed in a bottom portion of the groove, and a surface of the semiconductor substrate other than the groove; A second region of the second conductivity type formed in the portion, a charge storage layer formed on the surface of the semiconductor substrate, and a plurality of regions formed on the charge storage layer and intersecting the plurality of grooves. And a conductive layer. In this case, the charge storage layer may be composed of a laminated film of two or more types of insulating films.

Further, the first region may constitute a source line, the second region may constitute a drain line, and the conductive layer may constitute a word line.

In a method of manufacturing a nonvolatile semiconductor memory device according to the present invention, a step of forming a groove in a semiconductor substrate of a first conductivity type and a step of forming a first insulating film on a surface of the semiconductor substrate including the inside of the groove. Forming a charge storage layer on the first insulating film in a side wall portion inside the trench, and forming a first conductive type first portion on the bottom of the trench on the semiconductor substrate surface side. Forming a region, forming a second region of the second conductivity type in a portion other than the groove on the surface of the semiconductor substrate, covering the first region, the second region, and the charge storage layer As described above, the method for manufacturing a nonvolatile semiconductor memory device according to the present invention, comprising the steps of: forming a second insulating film; and forming a control gate on the second insulating film, comprises: Forming a groove in a semiconductor substrate of one conductivity type; The surface of the semiconductor substrate including the,
A step of forming a first insulating film, a step of forming a second insulating film on the first insulating film with an insulating film different from the first insulating film, and a step of forming a second insulating film on the bottom of the groove on the semiconductor substrate surface side. Forming a first region of the second conductivity type, forming a second region of the second conductivity type in a portion other than the groove on the surface of the semiconductor substrate, and controlling the second region on the second insulating film. Forming a gate.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS [First Embodiment] A first embodiment of the present invention relates to a ground cell array type nonvolatile semiconductor memory device using polycrystalline silicon for a floating gate. A high integration can be achieved by forming the floating gate on the side wall inside the trench, with the bottom as the drain or source. Hereinafter, the present embodiment will be described in detail with reference to the drawings.

First, the structure of the nonvolatile semiconductor memory device according to the present embodiment will be described with reference to FIGS. FIG.
FIG. 1A is a plan view showing an interlayer insulating film of a nonvolatile semiconductor memory device, and FIG.
It is a B sectional view. FIG. 2 is a perspective view showing a word line portion of the nonvolatile semiconductor memory device three-dimensionally with an interlayer insulating film removed.

As can be seen from FIG. 1B, a groove 11 is formed on the surface of a semiconductor substrate 10 made of a p-type silicon substrate. The semiconductor substrate 10 at the bottom of the groove 11
An n ⁺ type source region 12 is formed on the surface side. That is, the source region 12 is formed of the impurity diffusion layer of the opposite conductivity type to the semiconductor substrate 10.

An n ⁺ -type drain region 14 is formed on the surface of the semiconductor substrate 10 where the groove 11 is not formed. That is, the drain region 14 is formed of an impurity diffusion layer of the opposite conductivity type in the upper portion of the surface of the semiconductor substrate 10 with respect to the bottom of the groove 11, similarly to the source region 12. The source region 12 is continuously connected to cells adjacent in the bit line direction (column direction) to form the source line 2. The drain region 14 is continuously connected to a cell adjacent in the bit line direction to form the bit line 4.

A floating gate 30 made of polycrystalline silicon is formed on a side wall portion inside the trench 11 via a tunnel oxide film 20. That is, the floating gates 30 are formed at both side wall portions inside the groove 11. The floating gate 30 forms a charge storage layer in the present embodiment.

A control gate 3 made of polycrystalline silicon is provided above the floating gate 30 via an insulating film 22 formed of a laminated film (ONO film) of an oxide film, a nitride film, and an oxide film.
2 are formed. The control gate 32 is orthogonal to the source line 2 and the bit line 4 and forms a word line 3.

The memory cell transistor includes a source line 2 provided at the bottom of the groove 11, a bit line 4 provided on the surface of the semiconductor substrate 10, and a floating gate 30 formed between the source line 2 and the side wall of the groove 11. , Control gate 32.

Next, a method of manufacturing the nonvolatile semiconductor memory device according to the first embodiment will be described with reference to FIGS. 3 to 6 are process cross-sectional views illustrating the method for manufacturing the nonvolatile semiconductor memory device according to the first embodiment.

As can be seen from FIG. 3, the surface of the semiconductor substrate 10 made of a p-type silicon
RIE (Re)
active ion etching).

Next, as shown in FIG.
A tunnel oxide film 20 of 0 to 100 angstroms is formed. Subsequently, a polycrystalline silicon layer 30A having a thickness of, for example, 1000 to 3000 Å is deposited on the tunnel oxide film 20. This polycrystalline silicon layer 30A
May be doped with, for example, phosphorus as an impurity, or phosphorus or arsenic may be ion-implanted later.
That is, the polycrystalline silicon layer 30A is formed of a conductive member.

Next, as shown in FIG. 5, the polysilicon layer 30A is etched by RIE to form a polysilicon layer 30B. That is, when the polycrystalline silicon layer 30A is etched by RIE, the polycrystalline silicon on both side walls inside the groove 11 remains without being etched. The polycrystalline silicon remaining on both side walls inside the groove 11 becomes the polycrystalline silicon layer 30B. At this point, the polycrystalline silicon layer 30B is formed continuously in the direction of the groove 11.

Returning to FIG. 5, in this state, an impurity of phosphorus or arsenic is ion-implanted, so that an n ⁺ -type diffusion layer is continuously formed on the bottom of the groove 11 and on the surface of the semiconductor substrate 10. The source region 12 and the drain region 14 of FIG. That is, the groove 1 of the semiconductor substrate 10
A source region 12 is formed at one bottom, and a drain region 14 is formed on the surface side of the semiconductor substrate 10. Then, the source region 12 becomes the source line 2 continuous in the direction of the groove 11, and the drain region 14 becomes the bit line 4 continuous in the direction of the groove 11.

Next, as shown in FIG. 6, an insulating film 22 is formed of a laminated film (ONO film) with a nitride film sandwiched between oxide films.
The insulating film 22 is formed with a thickness of, for example, 120 to 180 angstroms. Subsequently, polycrystalline silicon is deposited on the insulating film 22 to a thickness of 2000 to 3000 angstroms to form a polycrystalline silicon film 32.

Next, as shown in FIG. 1A, a photoresist is applied, and the photoresist is patterned by photolithography so as to be orthogonal to the bit lines 4 and the source lines 2. Then, using this photoresist as a mask, the polycrystalline silicon film 32 is etched by RIE to form the word lines 3. Subsequently, using the photoresist as a mask, the insulating film 22 and the polycrystalline silicon layer 30B are etched by RIE. Thereby, the polysilicon layer 30B is separated in the bit line direction, and the floating gate 30 is formed. That is, at this point, the floating gate 30 separated for each memory cell transistor is formed.

Although omitted in the figure, the word line 3
After the formation of CVD, CVD (Chemical Vapor Deposition)
To form an interlayer insulating film between the word line 3 and the aluminum (Al) wiring or the like.

In the periphery of the memory cell array,
A contact hole is formed at a desired position by RIE in order to electrically connect the bit line 4 and the source line 2 to an aluminum (Al) wiring or the like. Then, aluminum (A
1) Sputtering and patterning to form wiring.

Next, the operation of the nonvolatile semiconductor memory device according to the present embodiment will be described with reference to FIGS. FIG. 7 is an equivalent circuit of the nonvolatile semiconductor memory device shown in FIGS. 1 and 2, and FIG. 8 is a diagram showing the operating conditions in a table.

As shown in FIGS. 7 and 8, when writing to the selected memory cell transistor Tr1, that is, when injecting electrons into the floating gate 30 (see FIG. 2), for example, the bit line 4 ( 6V is applied to 1), the bit line 4 (2) is opened, and 10 V is applied to the word line 3 (1).
V is applied to ground the source line 2 (2). The other word lines 3 (2) and 3 (3) are grounded, and the other source lines 2 (1)
Is applied to the bit line 4 (1) at the same potential as 6V or a voltage higher than the ground potential that does not allow electrons to be injected into the floating gate 30 of the memory cell transistor due to the back bias effect, or is left open.

In this way, a channel current flows only in the selected memory cell transistor Tr1, and a part of the channel current is injected into the floating gate 30 (see FIG. 2) as hot electrons. The threshold value of the memory cell transistor after electron injection is about 5 to 6V.

When erasing is performed on a selected block unit of a certain size (here, the memory cell transistors Tr1 and Tr2), for example, the bit lines 4 (1) and 4
(2) is opened, the word line 3 (1) is grounded, and 12 V is applied to the source line 2 (2). By applying, for example, 12 V to the word lines 3 (2) and 3 (3) of the memory cell transistor not to be erased and opening the source line 2 (1), the word lines 3 (2), 3 (3) and The memory cell transistor connected to the source line 2 (1) is not erased.

By doing so, the floating gates 30 of the selected memory cell transistors Tr1 and Tr2 are
Electrons (see FIG. 2) are emitted to the source line 2 (2). The threshold value of the memory cell transistor after the release is about 0
２2V.

The selected memory cell transistor Tr1
For example, when data is read out, 3 V is applied to the selected bit line 4 (1) and word line 3 (1), the bit line 4 (2) is opened, and the source line 2
(2) is grounded. The word lines 3 (2) and 3 (3) of the unselected memory cell transistors are grounded, and the source line 2
(1) is a voltage higher than the ground potential (for example, 3 V) at which no current flows through the memory cell transistor due to the back bias effect.
Or open.

By doing so, the source line 2 connected to the selected memory cell transistor Tr1
The one-bit information “0” depends on whether or not a current flows in (2).
Corresponds to "1". That is, when writing is performed, the threshold value of the memory cell transistor is about 5 to 6 V, and when erasing is performed, the threshold value of the memory cell transistor is about 0 to 2 V. For this reason,
When a voltage of 3 V is applied to the word line 3 (1), for example, a case where a current flows from the bit line 4 (1) to the source line 2 (2) corresponds to "1", and the bit line 4 (1) Line 2
The case where no current flows in (2) corresponds to “0”.

As described above, according to the nonvolatile semiconductor memory device of the present embodiment, since the floating gates 30 are provided on both side walls inside the groove 11 formed on the semiconductor substrate 10, Compared to the conventional ground cell array type nonvolatile semiconductor device that forms a floating gate
High integration can be achieved, and a large-capacity nonvolatile semiconductor device can be realized.

That is, the source region 12 is formed at the bottom of the groove 11 of the semiconductor substrate 10 and the semiconductor substrate 10
Since the drain region 14 is formed on the front surface side and the floating gate 30 is formed on the side wall of the groove 11, the nonvolatile semiconductor memory device is compared with the conventional case where the floating gate is formed two-dimensionally. Can be reduced in overall area. In other words, as shown in FIG. 2, two memory cell transistors MT1 and MT2 can be formed using one groove 11 in the semiconductor substrate 10, so that the nonvolatile semiconductor memory device can be miniaturized. it can.

Since the depth of the groove 11 becomes the channel length of the memory cell transistor, even if the channel length is increased in order to improve the electric breakdown voltage, the depth of the groove 11 is only increased. . Therefore, the planar area of the memory cell transistor can be prevented from increasing,
High integration in a nonvolatile semiconductor memory device can be achieved.

[Second Embodiment] A second embodiment of the present invention is directed to a semiconductor memory device having a charge storage layer formed of a laminated insulating film composed of two or more layers by using the present invention. This enables a higher density than a memory cell transistor using the formed floating gate as a charge storage layer. Hereinafter, the present embodiment will be described in detail with reference to the drawings.

First, the structure of the nonvolatile semiconductor memory device according to the second embodiment will be described with reference to FIGS. FIG. 9A is a plan view showing the nonvolatile semiconductor memory device according to the second embodiment through the interlayer insulating film.
FIG. 10B is a sectional view taken along line CC in FIG. 9A. FIG. 10 is a perspective view showing a word line portion of the nonvolatile semiconductor memory device three-dimensionally by removing an interlayer insulating film.

As can be seen from FIG. 9B, a groove 51 is formed on the surface side of the semiconductor substrate 50 made of a p-type silicon substrate.
Are formed. At the bottom of the groove 51, an n ⁺ type source region 52 is formed. That is, the source region 52 is formed of the impurity diffusion layer of the opposite conductivity type to the semiconductor substrate 50.

An n ⁺ type drain region 54 is formed on the surface side of the portion of the semiconductor substrate 50 where the groove 51 is not formed. That is, the drain region 54 is formed of an impurity diffusion layer of the opposite conductivity type in the upper portion of the surface of the semiconductor substrate 50 with respect to the bottom of the groove 51, similarly to the source region 52. The source region 52 is continuously connected to cells adjacent in the bit line direction (column direction) to form the source line 5. The drain region 54 is continuously connected to a cell adjacent in the bit line direction to form the bit line 7.

A charge storage layer 66 formed by laminating a lower oxide film 60, a nitride film 62, and an upper oxide film 64 is formed on a side wall portion inside the trench 51. Such a charge storage layer 66
In this case, electrons can be accumulated at the interface between the oxide films 60 and 64 and the nitride film 62 or at the nitride film 62. This charge storage layer 6
A control gate 70 made of a polycrystalline silicon layer is formed on 6. This control gate 70 is connected to an adjacent cell to form word line 6. This word line 6 is orthogonal to the bit line 7 and the source line 5.

The memory cell transistor includes a source line 5 provided at the bottom of the groove 51, a bit line 7 provided on the surface of the semiconductor substrate 50, a charge storage layer 66, a control gate 7
0.

Next, a method for manufacturing a nonvolatile semiconductor memory device according to the second embodiment will be described with reference to FIGS. 11 to 13 are process cross-sectional views illustrating the method for manufacturing the nonvolatile semiconductor memory device according to the second embodiment.

As shown in FIG. 11, a surface of a semiconductor substrate 50 made of a p-type silicon
A groove 51 of 0 to 5000 angstroms is formed by RIE.

Next, as shown in FIG. 12, for example, after forming a lower oxide film 60 having a thickness of 30 to 100 Å, a nitride film 6 is formed on the lower oxide film 60 by CVD.
2 is deposited, for example, with a thickness of 80-150 Å. Thereafter, the upper oxide film 6 is formed on the nitride film 62.
4 is formed with a thickness of, for example, 20 to 100 Å. The stacked film including the lower oxide film 60, the nitride film 62, and the upper oxide film 64 functions as the charge storage layer 66.

Next, an impurity such as phosphorus or arsenic is implanted into the surface of the semiconductor substrate 50 by ion implantation to form a source region 52 and a drain region 54. At this time, the groove 51
By performing ion implantation with the incident angle always set to 90 degrees with respect to the bottom of the groove 51, almost no ions are implanted into the side wall of the groove 51, and the surface of the semiconductor substrate 50 at the bottom of the groove 51 and the other than the groove 51 Part of the semiconductor substrate 50 surface side,
An n ⁺ type diffusion layer is formed. Then, the n ⁺ type diffusion layer becomes the source region 52 and the drain region 54. As shown in FIG. 9A, the source region 52 continuously formed in the direction of the groove 11 becomes the source line 5, and the drain region 54 formed continuously in the direction of the groove 11 becomes the bit line 7.

Next, as shown in FIG.
Then, polycrystalline silicon is deposited on the upper part of the substrate 4 to a thickness of 2000 to 3000 angstroms to form a polycrystalline silicon layer 70A. The polycrystalline silicon layer 70A may have conductivity by being doped with phosphorus or the like and deposited,
Alternatively, conductivity may be imparted by implanting phosphorus or arsenic by ion implantation later.

Next, as shown in FIG. 9, a photoresist is applied, and the photoresist is patterned so as to be orthogonal to the bit lines 7 and the source lines 5. Using this photoresist as a mask, a polycrystalline silicon layer 70A is formed by RIE.
Is etched to form a control gate 70. The control gate 70 is continuously connected to an adjacent memory cell transistor to form the word line 6. Also, using this photoresist as a mask, the upper oxide film 64 is formed.
, Nitride film 62 and lower oxide film 60 are etched by RIE. Thereby, as shown in FIG. 10, the charge storage layer 66 including the upper oxide film 64, the nitride film 62, and the lower oxide film 60 is separated in the direction of the groove 51.

Although omitted in the figure, the word line 6
Is formed, an insulating film is deposited by CVD, and an interlayer insulating film between the aluminum (Al) wiring or the like and the word line 6 is formed.

In the periphery of the memory cell array,
A contact hole is formed at a desired position by RIE in order to electrically connect the bit line 7 and the source line 5 to an aluminum (Al) wiring or the like. Then, aluminum (A
1) Sputtering and patterning to form wiring.

The equivalent circuit and operation of the non-volatile semiconductor memory device according to this embodiment are the same as those of the first embodiment, and a detailed description thereof will be omitted.

As described above, according to the nonvolatile semiconductor memory device of the present embodiment, the charge storage layer 66 is provided on the side wall portion inside the groove 51 formed on the semiconductor substrate 50. Compared with a conventional ground cell array type nonvolatile semiconductor device in which a charge storage layer is formed, a higher integration can be achieved and a large capacity nonvolatile semiconductor device can be realized.

That is, the source region 52 is formed at the bottom of the groove 51 of the semiconductor substrate 50, the drain region 54 is formed on the surface side between the grooves 51 of the semiconductor substrate 50, and the lower oxide film on the side wall portion inside the groove 51 is formed. Since the stacked film including the nitride film 60, the nitride film 62, and the upper oxide film 64 is used as the charge storage layer 66, the nonvolatile semiconductor memory is compared with the conventional case where the charge storage layer is formed two-dimensionally. The overall area of the device can be reduced. In other words, FIG.
As shown in (2), two memory cell transistors MT3 and MT4 can be formed in one groove 51 in the semiconductor substrate 50, so that the nonvolatile semiconductor memory device can be miniaturized.

Since the depth of the groove 51 becomes the channel length of the memory cell transistor, even if the channel length is increased in order to improve the electric breakdown voltage, the groove 51 is only deepened. Therefore, the planar area of the memory cell transistor can be prevented from increasing, and high integration in the nonvolatile semiconductor memory device can be achieved.

In addition, since the stacked film composed of the lower oxide film 60, the nitride film 62, and the upper oxide film 64 is used as the charge storage layer 66, the charge storage layer 66 is made of polycrystalline silicon as in the first embodiment. The charge storage layer can be made thinner than forming a floating gate. For this reason, the width of the groove 51 can be further reduced, and higher integration of the nonvolatile semiconductor memory device can be achieved.

The present invention is not limited to the above embodiment, but can be variously modified. For example, in the first and second embodiments described above, it is also possible to reverse all conductivity types. In the first and second embodiments described above, the source regions 12 and 52 are formed at the bottoms of the grooves 11 and 51, and the drain region 14 is formed between the grooves 11 and 51 on the surface side of the semiconductor substrates 10 and 50. However, both may be reversed. That is, a drain region may be formed at the bottom of the grooves 11 and 51, and a source region may be formed between the grooves 11 and 51 on the surface side of the semiconductor substrates 10 and 50.

In the second embodiment described above,
As the charge storage layer 66, a laminated film composed of three insulating films of the lower oxide film 60, the nitride film 62, and the upper oxide film 64 is used. However, a laminated film composed of two or more insulating films of two or more types is used. It is possible to form a charge storage layer. In the above-described second embodiment, an oxide film and a nitride film are used as two or more types of insulating films. However, the present invention is not limited to this. For example, an oxide film and polysilicon not doped with impurities may be used. May be used.

In the operation of the memory cell transistors according to the first and second embodiments, the erasing operation has been described by applying a voltage to the source lines 2 and 5.
A method of applying a voltage to the gate is also applicable. As described above, in the method of erasing by applying a voltage to the semiconductor substrates 10 and 50, it is necessary to separate a peripheral circuit for operating the ground cell array from a memory cell transistor formation region. Therefore, by forming the memory cell transistor in the well region separated from the peripheral circuit in the semiconductor substrates 10 and 50, it becomes possible to apply a voltage only to the memory cell transistor formation region.

For example, when using the p-type semiconductor substrates 10 and 50, an n-type well is formed, a p-type well is formed therein, and a memory cell transistor is formed in the p-type well. . Further, the n-type semiconductor substrates 10, 5
When 0 is used, a p-type well in which a memory cell transistor formation region and a peripheral circuit region are separated from each other is formed. This makes it possible to apply a voltage only to the memory cell transistor region.

As the applied voltage at the time of erasing, the former is such that the p-type semiconductor substrates 10 and 50 are grounded, and a high voltage, for example, 15 to 20 V is applied to the n-type well and the p-type well. In the latter case, a high voltage, for example, 15 to 20 V is applied to the p-type well region where the n-type semiconductor substrates 10 and 50 and the memory cell array are formed, and erasing is performed by grounding the p-type well region of the peripheral circuit. it can. In both the former and the latter, the conductivity types of the semiconductor substrates 10 and 50 and the well can all be reversed, and in that case, the polarity of the erase voltage is also reversed.

In these cases, similarly, a voltage equivalent to the voltage applied to the well region at the time of erasing is applied to the control gate of the memory cell transistor in a block of a certain size which is not erased. Alternatively, the well region may be divided for each block of a certain size. In this case, blocks not to be erased are grounded.

[0067]

As described above, according to the nonvolatile semiconductor memory device and the method of manufacturing the same of the present invention, the charge storage layer is formed on the side wall inside the groove formed on the surface of the semiconductor substrate. Therefore, high integration of the nonvolatile semiconductor memory device can be realized.

[Brief description of the drawings]

FIG. 1A is a plan view and FIG. 1B is a cross-sectional view of a nonvolatile semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is a perspective view of the nonvolatile semiconductor memory device according to the first embodiment of the present invention.

FIG. 3 is a view showing a part of the manufacturing process of the nonvolatile semiconductor memory device according to the first embodiment of the present invention.

FIG. 4 is a view showing a part of the manufacturing process of the nonvolatile semiconductor memory device according to the first embodiment of the present invention.

FIG. 5 is a view showing a part of the manufacturing process of the nonvolatile semiconductor memory device according to the first embodiment of the present invention.

FIG. 6 is a view showing a part of the manufacturing process of the nonvolatile semiconductor memory device according to the first embodiment of the present invention.

FIG. 7 is a diagram showing an equivalent circuit of the nonvolatile semiconductor memory device according to the first and second embodiments of the present invention.

FIG. 8 is a table showing operating conditions of the nonvolatile semiconductor memory device according to the first and second embodiments of the present invention.

FIG. 9 is a plan view (a) and a cross-sectional view (b) of a nonvolatile semiconductor memory device according to a second embodiment of the present invention.

FIG. 10 is a perspective view of a nonvolatile semiconductor memory device according to a second embodiment;

FIG. 11 is a view showing a part of the manufacturing process of the nonvolatile semiconductor memory device according to the second embodiment of the present invention.

FIG. 12 is a view showing a part of the manufacturing process of the nonvolatile semiconductor memory device according to the second embodiment of the present invention.

FIG. 13 is a view showing a part of the manufacturing process of the nonvolatile semiconductor memory device according to the second embodiment of the present invention.

FIG. 14 is a perspective view of a conventional nonvolatile semiconductor memory device.

15A and 15B are a plan view and a cross-sectional view of a conventional nonvolatile semiconductor memory device.

[Explanation of symbols]

 10, 50, 100 Semiconductor substrate 12, 52, 120 Source region 14, 54, 140 Drain region 20, 200 Tunnel oxide film 22, 220 Insulating film 30, 300 Floating gate 32, 70, 320 Control gate 2, 5, 121 Source Line 4, 7, 141 Bit line 3, 6, 131 Word line 60 Lower oxide film 62 Nitride film 64 Upper oxide film 66 Charge storage layer

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Claims (8)

[Claims] 1. A non-volatile semiconductor memory device comprising a ground cell array including a plurality of memory cell transistors capable of storing charges in a charge storage layer and releasing the stored charges, comprising: Either of the source lines is formed at the bottom of the groove formed in the semiconductor substrate with a diffusion layer of the opposite conductivity type to the semiconductor substrate, and the other is formed on the surface side of the semiconductor substrate other than the groove bottom at the opposite conductivity type to the semiconductor substrate. Wherein the charge storage layer is formed on the side wall inside the trench. 2. A semiconductor substrate of a first conductivity type having a plurality of grooves formed on a front surface side thereof in parallel with each other; a first region of a second conductivity type formed at a bottom of the groove; A second region of a second conductivity type formed on a surface portion other than the groove; a charge storage layer formed on a sidewall portion inside the groove; a charge storage layer, the first region, and the second region A plurality of conductive layers formed thereon with an insulating film interposed therebetween and intersecting the plurality of grooves. 3. The nonvolatile semiconductor memory device according to claim 2, wherein said charge storage layer is formed of polysilicon doped with an impurity. 4. A semiconductor substrate of a first conductivity type in which a plurality of grooves are formed on a front surface side in parallel with each other, a first region of a second conductivity type formed in a bottom portion of the groove, A second region of a second conductivity type formed on a surface portion other than the groove; a charge storage layer formed on a surface of the semiconductor substrate; and a charge storage layer formed on the charge storage layer and intersecting the plurality of grooves. And a plurality of conductive layers formed by: 5. The nonvolatile semiconductor memory device according to claim 4, wherein said charge storage layer is formed of a laminated film of two or more types of insulating films. 6. The semiconductor device according to claim 2, wherein the first region forms a source line, the second region forms a drain line, and the conductive layer forms a word line. Or a non-volatile semiconductor storage device according to any one of the above. 7. A step of forming a groove in a semiconductor substrate of a first conductivity type; a step of forming a first insulating film on a surface of the semiconductor substrate including the inside of the groove; and a side wall inside the groove. On a portion of the first insulating film,
Forming a charge accumulation layer; forming a first region of a second conductivity type at the bottom of the groove on the surface of the semiconductor substrate; forming a second region on the surface of the semiconductor substrate other than the groove; Forming a second region of a conductivity type; forming a second insulating film so as to cover the first region, the second region, and the charge storage layer; and controlling a control gate on the second insulating film. Forming a non-volatile semiconductor storage device. 8. A step of forming a groove in a semiconductor substrate of a first conductivity type; a step of forming a first insulating film on a surface of the semiconductor substrate including the inside of the groove; Forming a second insulating film with an insulating film different in type from the first insulating film; forming a first region of a second conductivity type at a bottom of the groove on the surface of the semiconductor substrate; A step of forming a second region of the second conductivity type in a portion other than the groove on the surface of the semiconductor substrate; and a step of forming a control gate on the second insulating film. A method for manufacturing a semiconductor storage device.