JPH0458226B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a video signal detection circuit for detecting the presence or absence of a video signal in a television receiver or a videotape recorder. In particular, this invention relates to devices that can be easily integrated into one-chip digital integrated circuits (hereinafter referred to as ICs) as part of the digital tuning systems that have recently become popular.

In recent years, electronic tuners have become mainstream in television receivers and video tape recorders.
Furthermore, digital tuning systems having a function of automatically searching for a broadcasting station (hereinafter referred to as a search function) are being developed. The search function referred to here is to automatically sweep the tuning voltage, that is, the tuning frequency, and stop the sweep at a location where the video signal is present. Therefore, a circuit for detecting the video signal becomes necessary. As a conventional video signal detection method, there is a method of ANDing a horizontal synchronizing signal and a flyback signal, and this method will be explained with reference to FIGS. 1 and 2. Figure 1 is a circuit diagram of the conventional method, and Figure 2 is a waveform diagram showing its operating principle. In Figure 1, 1 is a power supply terminal, 2 is a synchronization signal input terminal, and Figure 2
The waveform shown in is input. Reference numeral 3 denotes a horizontal retrace pulse input terminal, into which the waveform shown in FIG. 2a is input.
4 is a video signal detection output terminal, 5 is a resistor whose one end is connected to input terminal 2, 6 is a diode connected between the other end of this resistor 5 and input terminal 3, and 8 is a base whose base is the other end of the resistor 5. The emitter is connected to the emitter DC power supply 7, and the collector is connected in series to the resistor 9,1.
0 respectively connected to power supply terminal 1 through
The resistor 5 and the diode 6, which are NPN type transistors, form a circuit that ANDs the horizontal blanking line and the synchronizing signal. 11 is the above power supply terminal 1
A capacitor is connected between the resistors 9 and 10 connected in series, and constitutes a smoothing circuit with the resistors 9 and 10. 12 is a PNP transistor whose base is connected to the connection point of the series-connected resistors 9 and 10, whose emitter is connected to the power supply terminal 1, and whose collector is connected to the video signal detection output terminal 4; transistor 1
It is a resistor connected to the collector of 2 and the other end is grounded.

Next, the operation of the circuit shown in FIG. 1 will be explained.

First, since the horizontal retrace pulse signal applied to the input terminal 3 has a waveform as shown in FIG. 2a, the diode 6 is off during the horizontal retrace period and on during periods other than the retrace period. Therefore, transistor 8
The base voltage of is set to the forward voltage of diode 6, 0.7V, except during the retrace period, and is always cut off.
The operation of the synchronizing signal from the input terminal 2 is enabled only during the flyback period.

Here, when the synchronization signal is normal, the phase matches the horizontal retrace pulse as shown in FIG. 2b, so the input signal of the transistor 8, that is, the signal applied to the base becomes the signal shown in FIG. 2c.

When the waveform shown in Fig. 2c is applied to the transistor 8, which has a threshold voltage _e1 equal to the sum of the base-emitter potential difference of 0.7V and the emitter power supply 7,
When the horizontal synchronizing signal is normal, the threshold voltage e ₁ of the transistor 8 is applied to the base of the transistor 12 via a smoothing circuit composed of resistors 9 and 10 and a capacitor 11 on the collector side. DC voltage with smoothed pulse components exceeding
e ₃ (shown in Figure 2 d) occurs, and this DC voltage e ₃
exceeds the threshold voltage e ₂ at the base of transistor 12, which is set by appropriate selection of resistor 10 as shown in FIG. 2d, and turns transistor 12 on.

On the other hand, when there is no signal and in the audio signal portion, a thin noise _A1 and a large noise _A2 appear at the input terminal 2 as shown in Figure 2e, and the input signal of the transistor 8 is as shown in Figure 2f. There will be only a thin noise. Therefore, even if this thin noise exceeds the base threshold voltage _e1 of the transistor 8 and generates a DC voltage in the smoothing circuit resistors 9, 10 and the capacitor 11, the DC voltage in the base of the transistor 12 as shown in FIG. It is not necessary to turn on the transistor 12 as shown by the voltage e' ₃ . Therefore, the "H" level is obtained at the video signal detection output terminal 4 only when a video signal is present.

By the way, when the circuit shown in Fig. 1 is used, when there is no signal at the synchronization signal input (Fig. 2 e), a large noise _A2 is generated at the base of the transistor 12 in synchronization with the horizontal retrace pulse shown in Fig. 2 a. resulting DC voltage
It often happens that _e'3 exceeds the threshold voltage _e2 , turning on the transistor 12 and causing the "H" level to appear at the video signal detection output terminal 4.
Furthermore, when the level of the thin noise _A1 becomes too high, an "H" level similarly appears at the video signal detection output terminal 4, causing the circuit to malfunction. In addition, in the circuit shown in Figure 1, a synchronizing signal and a horizontal retrace pulse are always required to detect a video signal, but in a video tape recorder, there is no horizontal retrace pulse, and the video signal is detected. A special circuit had to be added for this purpose, and since it was an analog circuit, it was extremely difficult to incorporate it into a single chip IC as part of a digital tuning system.

Furthermore, as a method for determining whether a video signal is regular without using a horizontal retrace pulse, there is a known technique that determines whether a predetermined number of synchronization signals are present within a certain period of time. However, in order to make accurate judgments, it is necessary to count the synchronization signals more accurately, and the pursuit of this accuracy takes time to produce judgment results. There was a problem. In particular, in the search function, if it takes time to output a judgment result after receiving a video signal, the periodic frequency has already changed by the time the judgment result is obtained, and the video signal with the wrong frequency is converted into a regular one. In the end, it is impossible to determine which frequency of the video signal is the normal one.

The present invention has been made in view of the above points, and is based on a synchronization signal including a vertical synchronization signal pulse, an equalization pulse, and a horizontal synchronization signal pulse of a television signal. The number of pulses is counted during a long fixed period, a judgment is made based on this number of pulses, and a video signal detection output is output. It is also useful in recorders, and since the processing is carried out in a digital circuit, malfunctions are less likely to occur, and it can be easily integrated into a single chip IC as part of a digital tuning system.
Furthermore, the vertical synchronization signal pulse of the television signal,
The object of the present invention is to provide a video signal determination circuit that can quickly determine a television signal after receiving it by counting the number of pulses for synchronization signals including equalization pulses and horizontal synchronization signal pulses. be.

An embodiment of the present invention will be described below with reference to FIGS. 3 to 5. In FIG. 3, reference numeral 21 is an input terminal to which a horizontal synchronization signal input is applied, and 22 is a signal ( (shown in Figure 4a)
The control signal terminal 23 to which is applied is an AND circuit to which the input terminal 21 and the control signal terminal 22 are connected, and allows the horizontal synchronizing signal to pass only when the control signal terminal 22 is at the "H" level. 24 is a counter to which the output of this AND circuit is input and counts horizontal synchronizing signal pulses; 25 is a reset terminal of this counter 24, to which the signal shown in FIG.
When the level is reached, the counter 24 is reset. 2
6 is a latch circuit that holds the data of the counter 24, and 27 is a load signal input terminal from which the latch circuit 26 takes in the data.The signal shown in FIG. At the time, the latch circuit 26 takes in the data of the counter 24, and when the level is "L", the latch circuit 26 holds the data of the counter 24. 28 and 29 are first and second comparison circuits that compare the output value of the latch circuit 26 with predetermined values N ₁ and N ₂ respectively, and when the output value of the latch circuit 26 is larger than N ₁ The output 32 of the second comparison circuit 28 becomes "H" level, and when the output value of the latch circuit 26 is smaller than _N2 , the output 33 of the second comparison circuit 29 becomes "H" level. 31 is an AND circuit to which the outputs 32 and 33 of the first and second comparison circuits 28 and 29 are input; this output becomes the output that appears at the video detection output terminal 34; Circuits 28, 29, and AND circuit 3
1 constitutes a determination circuit.

Next, the operation of the video signal detection circuit configured as described above will be explained using the signal waveform diagram of FIG. 4.

First, at time _t0 , the control signal at the control signal terminal 22 changes from "L" level to "H" level as shown in FIG. 4a, and at time _t1 , it changes from "H" level to "L" level. During the time T until the input terminal 21
Horizontal synchronizing signal pulses input from the counter 24 are counted by a counter 24 via an AND circuit 23. In addition,
At time _t0 , the counter 24 is reset to 0 by the "H" level signal before time _t0 , as shown in FIG. If so, counter 2
4 counts N. Thereafter, at time _t1 , the control signal terminal 22 changes from the "H" level to the "L" level, and at time _t4 , the input of the horizontal synchronizing signal pulse to the counter 24 changes from the "L" level to the "H" level. prohibited until On the other hand, load signal input terminal 2
7 changes from the "L" level to the "H" level at time _t1 and changes from the "H" level to the "L" level at time _t2 , as shown in FIG. 4b.
During this period, the latch circuit 26 outputs the number of horizontal synchronizing signal pulses counted by the counter 24 during the time T from time t ₀ to t ₁ , for example, N.
is read and the value is held until time _t5 when the load signal changes from the "L" level to the "H" level. Further, since a signal from time _t3 to time _t4 is applied to the control signal terminal 25 as shown in FIG. 4c, the counter 24 is reset.
Thereafter, from time _t4 , the above difference will be repeated.

Now, the number of horizontal synchronizing signal pulses, for example N, held in the latch circuit 26 between time t ₁ and t ₂ is inputted to the first and second comparison circuits 28 and 29, and the number N ₁ and N ₂ are input to the first and second comparison circuits 28 and 29. When the data N of the latch circuit 26 is greater than _N1 , the first comparison circuit 2
The output 32 of 8 becomes "H" level, and becomes "L" level at other times. On the other hand, latch circuit 2
When the data N of 6 is smaller than _N2 , the output 33 of the second comparator circuit 29 goes to the "H" level, and otherwise goes to the "L" level. Therefore,
The output of the AND circuit 31, that is, the output appearing at the video signal detection terminal 34 becomes "H" level when the data N of the latch circuit 26 is greater than _N1 and less than _N2 .

By the way, as shown in Figure 5, the horizontal synchronization signal pulse is usually a pulse train with a frequency of 15, 75KHz, but in the vertical synchronization period T ₁ there is a cut pulse, and the equalization period T before and after the vertical synchronization period T ₁ . In ₂ , there is an equalization pulse. Therefore, the horizontal synchronization pulse counting time T (for example, from time t ₀ to t ₁
period) longer than the sum of the vertical synchronization period T ₁ and the equalization period T ₂ and shorter than the vertical synchronization period, for example, 1
When set to msec, the number of pulses for 1 msec will be as explained below.

1 msec excluding vertical synchronization period T ₁ and equalization period T ₂
In between, horizontal sync pulses of 15 and 75KHz are input, so the minimum number of pulses is 15. Considering the loss of one pulse, 13 is appropriate for _N1 . on the other hand,
When a vertical synchronization period T ₁ and an equalization period T ₂ are included in 1 msec, the cut pulse of the vertical synchronization period T ₁ and the equalization pulse of the equalization period T ₂ are compared to the horizontal synchronization pulse of 15, 75 KHz. There will be 9 extra pieces. Therefore, taking this into consideration, it is appropriate to set N ₂ =16+9=25.

Although T=1 msec is used above, the following relationships are generally derived for T: N ₁ =13T, N ₂ =16T+9.

Next, considering the case when there is no signal, a signal consisting of a thin noise _A1 and a large noise _A2 as shown in FIG. 2e is inputted from the horizontal synchronizing signal input terminal 21. Therefore, when the noise level is low, the counter 24 does not count the noise;
The value held in the latch circuit 26 is 0 or N ₁
It becomes a smaller value. Therefore, the output 32 of the first comparison circuit 28 is at the "L" level, and the output from the video signal detection output terminal 34 is at the "L" level. Also, when the noise level is high, this noise is counted by the counter 24 and the latch circuit 2
The value of 6 will be much larger than _N2 . Therefore, the output 33 of the second comparison circuit 29 becomes "L" level, and the output of the video signal detection output terminal 34 becomes "L".
level.

As described above, by setting the time T for counting pulses to be larger than the sum of the vertical synchronization period _T1 and the equalization period _T2 and smaller than the vertical synchronization period, the third
If the value of the number of pulses N counted by the counter 24 in the circuit shown in the figure is limited to 13T<N<16T+9 (1), the video signal can be detected correctly.

By the way, when the time T is increased, considering the time with the vertical synchronization period, vertical synchronization period × M ≦ T < vertical synchronization period × (M + 1) ... (2) (M = 0, 1, 2, ... ), the vertical synchronization period T ₁ and the equalization period T ₂ will occur M times or (M+1) times during the time T. Therefore, as is clear from the above, the data N of the latch circuit 26 is
is 13T+9M<N<16T+9(M+1)...(2).

As described above, a video signal can be detected correctly with a simple digital circuit configuration such as the embodiment shown in FIG. In addition, when implementing the IC as part of a digital tuning system, it is easy to incorporate it as an on-chip digital circuit, and the cost of the system can be reduced.

Note that the horizontal synchronization signal pulse may be missing due to weak electric fields, etc., so it may become smaller than the lower limit of equation (2), or there may be a lot of noise even if a regular synchronization signal is captured.
It may be larger than the upper limit of equation (2). Therefore, the lower and upper limits of N shown in equation (2) are not absolute, and may deviate somewhat from these values in practical use. For example, if we consider that half of the horizontal sync pulses are missing, the lower limit of N is (13T + 9M) x 0.5, and if the same number of noises as the horizontal sync pulses are mixed in, the upper limit of N is {16T
+9(M+1)}×2, and depending on the case, there may be no problem with such lower and upper limits.

As described above, the present invention is based on a synchronization signal including a notch of a vertical synchronization signal pulse, an equalization pulse, and a horizontal synchronization signal pulse of a television signal, for a fixed period T longer than the sum of the vertical synchronization period and the equalization period. _a counter that counts the number _of pulses N during a period of time; By providing a judgment circuit that outputs a video signal detection output when the value is less than ₂ , the video signal can be detected without requiring a horizontal retrace pulse, making it suitable not only for television receivers but also for video tape recorders. It can be used and can be detected by digital processing, so malfunctions are less likely to occur.

Furthermore, since the number of pulses is counted for the synchronization signal including the cut pulse of the vertical synchronization signal of the television signal, the equalization pulse, and the horizontal synchronization signal pulse, the number of pulses is counted before passing through a filter for synchronization separation and waveform. Since the television signal can be used as the determination signal, it is possible to obtain determination results without time delays caused by filters or the like.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a conventional video signal detection circuit, FIG. 2 is a waveform diagram for explaining the circuit operation of FIG. 1, FIG. 3 is a block circuit diagram showing an embodiment of the present invention, and FIG. This figure is a waveform diagram for explaining the circuit operation of FIG. 3, and FIG. 5 is a waveform diagram showing a horizontal synchronizing signal when a video signal is captured. In the figure, 24 is a counter, 26 is a latch circuit, 28 is a first comparison circuit, 29 is a second comparison circuit, and 23 and 31 are AND circuits.

Claims (1)

[Claims] 1. The vertical synchronizing signal pulse, including the notch pulse, the equalizing pulse, and the horizontal synchronizing signal pulse during a certain period T longer than the sum of the vertical synchronizing period and the equalizing period of the television signal. a counter that calculates the number of pulses counted by the counter, and the number N of pulses counted by this counter exceeds a first predetermined number _N1 and is less than a second predetermined number _N2 larger than the first predetermined number _N1; A video signal detection circuit including a determination circuit that outputs a video signal detection output when . 2. The first predetermined number _N1 is determined based on the number of pulses of the horizontal synchronization signal included when the fixed period T is all the horizontal synchronization period, and when the fixed period T is the vertical synchronization period and the equalization period 2. The video signal detection circuit according to claim 1, wherein the second predetermined number _N2 is determined based on the number of included vertical synchronization signal cut pulses and equalization pulses. 3. Set the fixed period T to an integral multiple M times (M=0, 1, 2...) or more and less than (M+1) times the vertical synchronization period,
2. The video signal detection circuit according to claim 1, wherein the first predetermined number N ₁ is 13T+9M, and the second predetermined number N ₂ is 16T+9 (M+1). 4. The judgment circuit is a latch circuit that reads the number of pulses N counted by the counter and outputs the number of pulses N. The output N of this latch circuit is compared with the first predetermined number _N1 , and the output N is A first comparator circuit outputs an "H" level when a predetermined number _N1 is exceeded, and the output N of the latch circuit is compared with a second predetermined number _N2 , and the output N is equal to the second predetermined number N2. “H” when less than ₂
a second comparator circuit that outputs the level;
and an AND circuit that outputs an "H" level when both outputs of the second comparison circuit are at an "H" level. A video signal detection circuit described in .