JPS58219879A - Detecting circuit of video signal - Google Patents

Abstract

PURPOSE:To detect video signal through a digital circuit by counting up the number of horizontal synchronous pulse for a fixed period longer than the sum of a vertical synchronous period and an equivalent period. CONSTITUTION:A horizontal synchronous pulse is impressed to an input 21 of an AND circuit 23 and a control pulse longer than the sum of the vertical synchronous period and the equivalent period is impressed to an input 22. During the period of T, a counter 24 counts up the number of horizontal synchronous pulse. The counted value is latched by a latch circuit 26. The contents of the latch circuit 26 are compared with prescribed values N1 and N2 by the 1st and 2nd comparators 28, 29 respectively. The comparator 28 outputs the ''H'' level when the contents of the latch circuit 26 are >N1 and the comparator 29 outputs the ''H'' level when the contents are <N2. Consequently, a video signal detecting output can be digitally obtained from an AND circuit 31.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a video signal detection circuit for detecting the presence or absence of a video signal in a television receiver or a video tape recorder, and particularly to a video signal detection circuit that enables video signal detection using a digital circuit. In particular, this invention relates to devices that can be easily integrated into C1 chip digital integrated circuits (hereinafter referred to as ICs) as part of the digital tuning systems that have recently become popular.

In recent years, electronic tuners have become increasingly popular in television receivers and video tape recorders, and digital tuning also has functions such as automatically searching for broadcast stations (hereinafter referred to as the search function).

A system is being developed. The search function referred to here is to automatically sweep the tuning voltage, that is, the synchronization frequency, and stop the sweep at a location where the video signal is present. Therefore, a circuit for detecting the C video signal becomes necessary. As a conventional video signal detection method, there is a method of ANDing a horizontal synchronizing signal and a flyback signal, and this method will be explained using FIGS. 1 and 2. Figure 1 is a circuit diagram of the conventional method, and Figure 2 is a waveform diagram showing its operating principle. Figure (b
) is input. (3) is an input terminal for the horizontal retrace pulse, into which the waveform shown in FIG. 2(a) is input.

(4) is the video signal detection output terminal, I5) is a resistor whose one end is connected to the input terminal (2), and (6) is this resistor (5).
A diode connected between the other end and the input terminal (3), (
The base of 8) is connected to the other end of the resistor (6), the emitter is connected to the emitter DC power supply (7), and the collector and collector are connected to the °C power supply terminal 11) through the series-connected resistor (9). The resistor (5) and diode (6) form a circuit that ANDs the horizontal retrace line and the synchronizing signal. C1υ is the above power supply terminal (
1) and the resistor +9) connected in series A capacitor connected between the connection point of 11.1 and the resistor +9) (which constitutes the IQ and smoothing circuit. 0 has the base connected in series. At the connection point of the resistor (9), there is a PNP transistor whose emitter is connected to the power supply terminal (1), and to the video signal detection output terminal (4), respectively. A resistor is connected to the collector of this PNP transistor a, and the other end is grounded.

Next, the operation of the circuit shown in FIG. 1 will be explained.

First, since the horizontal retrace pulse signal applied to the input terminal (3) has a waveform as shown in Figure 2 (a), the diode (6) is off during the horizontal retrace period and is turned off outside the retrace period. Then turn on and Natsu C. Therefore, the base voltage of the transistor (8) is set to the forward voltage of the diode (6), 0.7V, except during the retrace period, and is always cut off, and only during the retrace period, the synchronizing signal from the input terminal (2) operates. becomes possible.

Here, when the synchronization signal is normal, the phase matches the horizontal retrace pulse as shown in Figure 2(b), so the transistor (8
), that is, the signal applied to the base is shown in FIG. 2(c).

When the waveform of Ayu 2 (C) is applied to the transistor (8), which has a threshold voltage el equal to the sum of the base-emitter potential difference 0.7V and the emitter power supply (7), the collector side Through a smoothing circuit consisting of a resistor (9), H, and a capacitor QO, the threshold voltage of the transistor (8) -1 (1st) is applied to the base of the transistor (B). The DC voltage e3 (Fig. 2 (d)
Shown below. This DC voltage e3 is as shown in Fig. 2(d).
By appropriately selecting the resistor (lI'e4) as shown in FIG.

10,000, When there is no signal and in the audio signal part, input terminal (3)
As shown in FIG. 2(e), a thin noise A1 and a large noise A2 appear, and the input signal to the transistor (B) becomes only the thin noise as shown in FIG. 2(f).

Therefore, this thin noise exceeds the base threshold voltage e1 of the transistor (8) and smoothing circuit resistance 19) (
10. Even if a DC voltage is generated by the capacitor a, the DC voltage e1 in Fig. 2 (g) is generated at the base of the transistor (to).
As shown in the figure, it is not necessary to turn on the transistor (2).

Therefore, the 11H'' level is obtained at the video signal detection output terminal (4) only when a video signal is present.

By the way, when using the circuit shown in Fig. 1, there is a large noise A2 in the synchronization signal input when there is no signal (Fig. 2 (e)).
The DC voltage e/3 generated at the base of the transistor 4IaS in synchronization with the horizontal retrace pulse shown in FIG. ) often appears at °1H" level.Furthermore, if the level of fine noise A1 becomes too high, 1 is set at the video signal detection output terminal (4), and "H"L/bevel is also set at the video signal detection output terminal (4). However, in the circuit shown in Fig. 1, in order to detect a video signal, a synchronizing signal and a horizontal retrace pulse are necessarily required. In a video tape recorder, there is no horizontal retrace pulse, and a special circuit must be added for video cheap recording to detect the video signal.Furthermore, since the video tape recorder has an analog circuit configuration, it cannot be used as part of the digital tuning system. (It was very difficult to make it into a 1-F tube IC.

This invention has been made in view of the above points, and is designed to count the number of pulses of the horizontal synchronization signal and output a video signal detection output according to the number of pulses.Video signal detection using only the C1 horizontal synchronization signal It is useful not only for television receivers but also for video table recorders, and since the processing is performed by digital circuits, malfunctions are less likely to occur.
) The purpose is to make it easier to convert some parts into a C1 chip IC.

An embodiment of the present invention will be explained below with reference to FIGS. 8 to 6. In FIG. The control signal terminal to which the signal for controlling the synchronization signal input (shown in FIG. 4(a)) is applied is connected to the control signal terminal by an AND circuit to which these input terminals (2) and the control signal terminal stem are connected. (Foundation)
The horizontal synchronizing signal is passed only when the signal is at "H" level.

(C) is a counter to which the output of this AND circuit is input and counts horizontal synchronizing signal pulses, (C) is this counter (
The signal shown in Fig. 4 (c) is applied to the reset terminal of (c), and the counter eφ is reset when the signal is at H'' level. ) is the load signal input terminal from which this latch circuit (E) takes in data. When the signal shown in Figure 4 (b) is applied and the load signal input terminal (2) is at "H" level, the latch circuit (T) takes in the data of counter←9, and when II is at L” level, the latch circuit (E)
Holds 4 data. @(2) is each a predetermined value N
The first and second comparison circuits compare the magnitude of the output value of the latch circuit (E) and the latch circuit (E).
) is larger than N, the first comparison circuit (2
)'s output (to) becomes "H" level, and the U-Tsuchi circuit (
When the output value of c) is smaller than N2, the second comparison circuit (
The output (to) of 2) becomes 11H” level. 0■ is the first
and a second, comparison circuit ll! This is an AND circuit where the output (2) (to) of (I) is input, and this output becomes the output that appears at the video detection output terminal (to), and the latch circuit (A).
First and second comparison circuit four wheels, and AND circuit (b)
This constitutes a judgment circuit.

Next, in the video signal detection circuit configured in this way, @4
The operation will be explained using the signal waveform diagram shown in the figure.

First, at time to, the control signal terminal slope changes from HL" level to "H" level as shown in FIG. 4(a), and from -H" level to u1. During the time T up to time t1 when the level changes to "level," the horizontal synchronizing signal pulses input from the input terminal (c) are counted by the counter Q4 via the AND circuit. Then, at time 1, the control signal terminal (A) changes from the "H" level to the "L" level, and the input of the horizontal synchronizing signal pulse to the power terminal (C) is switched to 111. . It is prohibited until time t4 when the level changes from It level to °tn'' level.

On the other hand, at the load signal input terminal), as shown in Fig. 4(b), the time
Changed to H9 level, L,, ttH” level wo) and 11L
The latch circuit (E) is at the tlH level until t2 when it changes to the ``tlH'' level.
C) reads the number of horizontal synchronizing signal pulses counted in the time T from time to to tl, for example, N, and the load signal is 6.
The value will be held until time t when the level changes from "L" level to "H" level. Also, the control signal terminal (2)
Since the signal from time t3 to t4 is applied to , as shown in FIG. 4(C), the counter 2 is reset.

Thereafter, from time t4, the above operations are repeated.

For example, N is the number of horizontal synchronizing signal pulses held between time t1 and t2 in the latch circuit).
2, and when the data N of the latch circuit (1) is larger than N1, the output (effectiveness is IIH) of the first comparator circuit
level, and at other times it becomes "L" level.

On the other hand, when the data N on the latch circuit axis is smaller than N2, the output (to) of the second comparator circuit (2) becomes 11H" level, and otherwise becomes +@L' level. Therefore, the AND circuit 0p That is, the output appearing at the video signal detection terminal (2) is the data N of the latch circuit axis.
When is larger than N1 and smaller than N2, it becomes ttHFj level.

By the way, as shown in FIG. 6, the horizontal synchronization signal pulse is normally a pulse train with a frequency of 15.76 KHz, but there is a cut pulse in the vertical synchronization period Tl, and the pulse train is equal in the equalization period T2 before and after the vertical synchronization period TI. There is a pulse. Therefore, the horizontal synchronization pulse counting time T (for example, the period from time to to 11) is set to be longer than the sum of the vertical synchronization period TI and the equalization period T2 and shorter than the vertical synchronization period, for example, 1 m5ec. Then, 1
The number of horizontal synchronization pulses during m5ec will be explained below.

Subtracting the vertical synchronization period Tl and equalization period T2 (for 1 m5ec, a horizontal synchronization pulse of 15.75 KHz is input, so the minimum number of pulses is 15. Considering the loss of one pulse, N1 is 18. Appropriate. On the other hand, 1m5e
If the vertical synchronization period T1 and the equalization period T2 are included between c, the cut pulse of the vertical synchronization period Tl and the equalization period T
The 2 equalization pulses are 9 extra compared to the 16.75 KHz horizontal sync pulse. Considering the above, it is appropriate to set N=16+9=25.

In the above, T = 1 msec, but generally C is N for T.
The following relationships are derived: 1=18T, N2=16T+9.

Next, considering the case when there is no signal, the horizontal synchronization signal input terminal (2) produces a thin noise AI as shown in Figure 2 (e).
A signal is input from the signal and the large noise A2.

Therefore, when the noise level is low, the counter does not count the noise and the value held in the latch circuit (2) becomes 0 or a value smaller than Nl.

Therefore, the 'output (to) of the first comparator circuit (2) is °
IL'' level, and the output of the video signal detection output terminal (b) is at tIL'' level. Further, when the noise level is high, this noise is counted by a counter (c), and the value of the latch circuit (e) becomes much larger than N2. Therefore, the output (to) of the second comparator circuit (2) goes to the 1L" level, and the output of the video signal detection output terminal (b) goes to the "L" level.

As described above, by setting the time T for counting horizontal synchronization pulses to be larger than the sum of the vertical synchronization period T1 and equalization period T2 and smaller than the vertical synchronization period, the horizontal The value of the number of synchronous pulses N is 18T<N<16T+9...11)
If it is limited to , the video signal can be detected correctly.

By the way, if the time T is increased to °C, considering the time with the vertical synchronization period, vertical synchronization period x M ≦ T < vertical synchronization X (M + 1)... (2
) (M = 0.1.2...), the vertical synchronization period T1 and the equivalent period T during the time T
2 will be entered M times or (M+1) times.

Therefore, as is clear from what has been said above, (1)
For the formula, data N of latch circuit (2) is 18T+9M
<N<16T+9(M+1) (2).

As described above, a video signal can be detected correctly with a simple digital circuit configuration such as the embodiment shown in FIG. Further, when implementing IC as part of a digital tuning system, it is easy to incorporate it as an on-chip digital circuit, and the cost of the system can be reduced.

Note that because horizontal synchronization signal pulses are missing due to weak electric fields, etc., the value may become smaller than the lower limit of equation (2), or even if a regular synchronization signal is captured, there is a lot of noise and it becomes larger than the upper limit of equation (2). It is possible. Therefore, it is shown in equation (2). The value of the lower limit of N, J:, is not an absolute value, and may deviate from this value to some extent in practical use. For example, considering that half of the horizontal synchronizing pulses are missing, the lower limit of N is (18T+9M)Xo,5,
If the same number of noises as horizontal sync pulses are mixed in, then N
The upper limit of is (16T+9(M+1))X'! Then,
In some cases, there may be no problem with such lower and upper limits.

As described above, the present invention includes a counter that counts the number of pulses N of a horizontal synchronization signal during a fixed period T longer than the sum of the vertical synchronization morning interval and the equalization period of the synchronization signal of a television signal;
Reading the number of pulses counted by this counter, and when this number of pulses N exceeds a first predetermined number N1 and is less than a second predetermined number N2 that is larger than the first predetermined number N,
Since a judgment circuit is provided to output the video signal detection output, the video signal can be detected using only the horizontal synchronization signal.
It can be used not only in television receivers but also in video tape recorders, and since it can be detected by digital processing, it has the effect of preventing malfunctions from occurring.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a conventional video signal detection circuit, FIG. 2 is a waveform diagram for explaining the circuit operation of FIG. 1, FIG. 8 is a block circuit diagram showing an embodiment of the present invention, and FIG. This figure is a waveform diagram for explaining the circuit operation of FIG. 8, and FIG. 5 is a waveform diagram showing a horizontal synchronizing signal when a video signal is captured. In the figure, (c) is a counter, (to) is a latch circuit, (
(to) is the first comparison circuit, (2) is the second comparison circuit, GI
) is an AND circuit. Agent Makoto Kuzuno - Figure 1 Figure 2 (Maichiichi-----O Figure 3 Figure 4 Figure 5 Procedural amendment (voluntary) ゛1. Case Display of patent application 1981-10j1881
No. 2, Title of the invention Video signal detection circuit 3, Relationship with the case of the person making the amendment Hitoshi Katayama, representative of the patent applicant Department 4, Agent 5, Subject of amendment (υ Scope of claims column of the specification. (2) Column for detailed explanation of the invention in the specification. (3) - Column for brief explanation of drawings in the specification. 6. Contents of amendment (1) The scope of claims in the specification is corrected as shown in the attached sheet. (2) In the 4th line of page 8 of the Specification Toyonaka, the 1 synchronous frequency is corrected to 1 tuning frequency. (3) In the 7th page of the same page, lines 4 to 6, 1 for video tape recorders, (4) On page 9, line 11, correct the line 1 control signal terminal stem to read 1 control signal terminal. (5) On page 10, line 8 of the same page. (6) On page 12, line 18 of the same page, ``signal from AI'' should be changed to ``signal from rb''. Correct. (7) On page 16, line 2 of the same page, rI mail is ' m
C (Correct 1 as Yo.) Claims (1) Count the number of pulses N of the horizontal synchronization signal during a certain period T that is longer than the sum of the vertical synchronization period and the equalization period of the synchronization signal of the television signal. A counter that reads the counted pulse number N of this counter, and when this pulse number N exceeds a first predetermined number Nl' and is less than a second predetermined number N2 that is larger than this first predetermined number N1. , a video signal detection circuit equipped with a determination circuit that outputs a video signal detection output. (2) The fixed period T is an integer M times the superposition synchronization period (M = 0
．． 1.2...) or more and less than (M+1) times, the first predetermined number Nl is 18T + 9M, and the second predetermined number N2
2. The video signal detection circuit according to claim 1, wherein: 16T+9(M+1). (3) The determination circuit is a latch circuit that reads the number of pulses N counted by the counter and outputs the number N of pulses, and the output N of this latch circuit is compared with a first predetermined number N1, and the output N is the first predetermined number N1. A first comparator circuit outputs an "H" level when a predetermined number N1 of 1 is exceeded, and the output N of the latch circuit is compared with a second predetermined number N, and the output N is a second predetermined number N. The second comparator circuit outputs "H" level when the voltage is less than N2, and the outputs of these first and second comparator circuits are both II H".
Claim 1 or 2 is characterized in that the invention is constructed of an AND circuit that outputs an H'' level when the
The video signal detection circuit described in .

Claims (1)

[Claims] +1) A counter that counts the number N of pulses of a horizontal synchronization signal during a certain period T longer than the sum of the vertical synchronization period and the equalization period of the synchronization signal of the television signal; The number of pulses N that has been set is read, and this number of pulses N exceeds a first predetermined number N, and a second number N that is larger than the first predetermined number N is read.
is less than the predetermined number N2, the video signal is detected as an output.
A video signal detection circuit equipped with a determination circuit that outputs C. (2) The fixed period T is an integer M times the vertical synchronization period (M=0
．． 1.2...) or more and less than (M+1) times, the first predetermined number N1 is 18T+9M, and the second predetermined number N is 16T+9 CM+1 ). The video signal detection circuit described in . (3) The determination circuit is a latch circuit that reads the number of pulses N counted by the counter and outputs the number N of pulses, and the output N of this latch circuit is compared with a first predetermined number N1, and the output N is the first predetermined number N1. a first comparator circuit that outputs @tN'' level when the predetermined number N1 of 1 is exceeded, and an output N of the latch circuit and a second
a second comparator circuit that compares a predetermined number N and a second predetermined number N2 and outputs an "H" level when the output N is less than the second predetermined number N2; 3. The video signal detection circuit according to claim 1, further comprising an AND circuit that outputs an IH level when both outputs of the circuit are at an H level.