JPH0434795A - Refresh control circuit - Google Patents

Abstract

PURPOSE:To efficiently access an external circuit to a DRAM by cancelling the refresh operation interrupted by the access of the external circuit together with the termination of the access. CONSTITUTION:When a refresh request signal is outputted from a refresh time generator 20 to a bus arbiter 19, the count number of an updown counter 21 is added, the bus arbiter 19 outputs a refresh execution signal to execute refreshing, and the count number of the updown counter 21 is subtracted. During the access of the external circuit, the count number of the updown counter 21 is added by delaying the output of the refresh execution signal, and the refresh delay is cancelled by outputting the refresh execution signal according to the count number of the updown counter 21 to a dynamic ram 3 in the state of compression together with the termination of the access of the external circuit. Thus, the utilizing efficiency of a bus 5 is improved and the external circuit can be effectively accessed to the dynamic ram 3.

Description

[Detailed description of the invention] Industrial applications The present invention relates to a freshener control circuit.

Conventional technology DRAM (Dynamic Random Access
ss Memory) is widely used as a memory system because of its low power consumption and high operating speed, but it requires refreshing because the stored contents naturally disappear due to discharge. This refresh is an operation of periodically inputting pulses to the DRAM to store data, and various types of refresh control circuits have been proposed for executing this.

Therefore, a first conventional example of such a refresh control circuit will be explained based on FIG. 6. First, in this refresh control circuit 1, a DRAM 3 to which a control circuit 2 that executes refresh is connected is connected to a bus 5 to which a bus arbiter 4 is connected, and this bus 5 has a CPU (Central P ro
cessing Unit) 6 and DMA (Di
rect Memory Access Control
ller) 7 is connected. Here, the control circuit 2 includes a DRAM timing generator 8,
Refresh time generator 9, the CPU 6 and D
Arbiter 10 directly connected to MA7. It is formed by a refresh counter 11, a multiplexer 12, and the like.

In such a configuration, this refresh control circuit 1
When a refresh request signal is output from the refresh time generator 9 of the control circuit 2, the arbiter 10 detects whether there is an access from the CPU 6 or the DMA 7, and if it is determined that there is no access, the refresh time generator 9 outputs a refresh request signal from the refresh counter 11 via the multiplexer 12. Eight refresh addresses are stored in DRAM3. Therefore, the DRAM 3 to which this refresh address is input is refreshed in synchronization with the output timing of the DRAM timing generator 8.

Next, a second conventional example of a refresh control circuit will be explained based on FIG. In this refresh control circuit 13, a refresh time generator 14 directly connected to the DMA 7 is connected to the bus 5, and a control circuit 15 connected to the DRAM 3 is formed by a DRAM timing generator 16 and a multiplexer 17.

In such a configuration, this refresh control circuit 1
3, DM from refresh time generator 14
When direct memory access is requested to A7, control circuit 1 is transferred from DMA7 under the control of bus arbiter 4.
A refresh address is output to the DRAM 3 via the DRAM 3, and the DRAM 3 is refreshed by this refresh address. It should be noted that the refresh control circuit 13 having such a structure is set so that acceptance of a DMA 7 request to the bus arbiter 4 is given top priority.

Problem to be Solved by the Invention In the refresh control circuits 1 and 13 as described above, the eighth
As illustrated in the figure, even while external circuits such as the CPU 6 and DMA 7 are accessing DRAM 3, DRAM 3 is refreshed at regular intervals. During this refresh, external circuits cannot access DRAM 3, so data transfer is interrupted. This will cause work to be delayed.

Means for Solving the Problems The invention as set forth in claim 1 provides a refresh time system in which a bus arbiter that outputs a refresh execution signal is connected to a dynamic RAM connected to a control circuit that executes refresh, and a refresh request signal is output to the bus arbiter. A generator is connected, and the output line from the refresh time generator to the bus arbiter is connected to the addition input, and the output line from the bus arbiter to the dynamic ram is connected to the subtraction input, which outputs the count number in a compressed state to the bus arbiter. Connected the counter.

The invention according to claim 2 provides an up/down counter in which an output line from a refresh time generator to a bus arbiter is connected to an addition input, and an output line from the bus arbiter to a dynamic ram is connected to a subtraction input to output a count number to the bus arbiter. and a refresh cycle timer that periodically outputs a refresh priority command to the bus arbiter in accordance with the refresh cycle of the dynamic RAM.

In the invention according to claim 1, when the refresh request signal is output from the refresh time generator to the bus arbiter, the count number of the up/down counter is added, and the bus arbiter outputs the refresh execution signal to execute the refresh of the dynamic ram. and the count number of the up-down counter is subtracted, and the bus arbiter delays the output of the refresh execution signal according to the access of the external circuit, and the count number of the up-down counter is added.When the access of the external circuit ends, the count of the up-down counter is subtracted. By outputting the refresh execution signal according to the number to the dynamic RAM in a compressed state and eliminating refresh delays, bus usage efficiency is improved and external circuits can effectively access the dynamic RAM. can.

According to the second aspect of the invention, when the refresh request signal is output from the refresh time generator to the bus arbiter, the count number of the up/down counter is added, and when the bus arbiter outputs the refresh execution signal and refresh of the dynamic ram is executed. When the count number of the up-down counter is subtracted and a refresh priority instruction is output from the refresh cycle timer according to the refresh cycle of the dynamic ram, a refresh execution signal according to the count number of the up-down counter is output from the bus arbiter to the dynamic ram. By performing refresh a predetermined number of times during the refresh period, the refresh operation is forcibly performed before the end of the refresh period, thereby preventing the storage contents of the dynamic RAM from being erased.

Embodiment An embodiment of the present invention will be explained based on FIGS. 1 to 5. Note that the same parts as in the conventional example described above are given the same names and numerals, and explanations thereof will be omitted. First, this embodiment is a control circuit 18 according to the invention as claimed in claim 1, and the first
As illustrated in the figure, a bus arbiter 19 is connected to a control circuit 15 connected to the DRAM 3 via a bus 5, and a refresh time generator 20 is connected to the bus arbiter 19 to add up/down counter 21.
Connected via 2. Here, the subtraction input 23 of this bus arbiter 19 is connected to an output line from the bus arbiter 19 to the control circuit 15, and this high-power line is also connected to a refresh counter 24 connected to the control circuit 15. . Further, an output line from the refresh time generator 20 to the bus arbiter 19 is connected to a refresh period timer 25 and a timer circuit 26, which are connected to each other, and a high-power line of the timer circuit 26 is connected to the bus arbiter 19. has been done.

In such a configuration, this refresh control circuit 1
8 will be described in detail below based on the flowchart illustrated in FIG. 2 and the time chart illustrated in FIG. 3.

Note that in this refresh control circuit 18, the DRAM 3
The priority of access requests is CPU6 and DMA7.
The bus arbiter 19 is set so that the external circuits such as the refresh time generator 2o are higher than the refresh time generator 2o.

In this refresh control circuit 18, when a refresh request signal is output from the refresh time generator 2o to the bus arbiter 19, this signal is also input to the addition manual 22, and 1 is added to the count number N of the up/down counter 21. be done. Therefore, bus arbiter 19
When the refresh execution signal is outputted from the DMA 7 to the control circuit 15 and refresh of the DRAM 3 is executed due to the operation of Ru.

In this refresh control circuit 18, as illustrated in FIG. 3, when the bus arbiter 19 delays the output of the refresh execution signal due to an access request from the DMA 7, etc., and the count number N of the up/down counter 21 is added, A refresh execution signal according to this count number is output in a compressed state to the control circuit 15 upon completion of access to the DMA 7 and the like. By doing this, the refresh work that was interrupted by interrupts such as DMA7 is compressed into a short time, and the DRA
The delayed refresh of M3 will be quickly resolved.

In other words, this refresh control circuit 18 can resolve the interrupted refresh work in a short time, so the CPU 6
and DMA 7 can effectively access DRAM 3, the efficiency of use of bus 5 is improved, and it is possible to contribute to speeding up information processing work.

Note that the refresh control circuit 18 of this embodiment
The refresh work interrupted due to access to an external circuit such as 6 or DMA 7 is quickly resolved as soon as the access ends. There is a possibility that the memory contents of the DRAM 3 will disappear if the critical amount is exceeded. Therefore, as in the invention described in claim 2, the DRAM
It is also possible to implement a refresh control circuit in which the refresh period timer 25 periodically outputs a refresh priority command to the bus arbiter 19 in response to the refresh period No. 3, thereby forcibly performing the refresh operation before the end of the refresh period. .

The operation of the device in this case is as shown in the flowchart of FIG. 4. In the normal state, like the refresh control circuit 18 described above, a refresh operation is executed giving priority to access to the DMA 7, but the time-up is increased according to the refresh cycle. Then, the refresh cycle timer 25 outputs a refresh priority signal to the bus arbiter 19. Then, as illustrated in FIG. 5, the bus arbiter 19 to which this signal has been input outputs a refresh execution signal to the control circuit 15 according to the count number of the up/down counter 21, so that the DRAM 3 receives the refresh signal before the end of the refresh cycle. The refresh operation will be performed a predetermined number of times.

Here, conditions for setting numerical values when implementing such a device will be roughly estimated. For example, a 1M bit DRAM is 8.
Since 512 refreshes are required during a refresh period of 2 (ms), the up/down counter 21
A counter that can count up to 512 can be used, and a 11512 counter can be used as the refresh cycle timer 25. From the above values, the refresh interval is approximately 16 (μs), so if the time required for - times of refresh is 1 (μs), it will take 512 (μs) to complete all refreshes. is necessary. Therefore, subtracting the minimum time required for refresh from the refresh cycle: 8.2 (ms) - 512 (μ5) = 7.688 (ms)
Therefore, 7.688 (ms) out of 8.2 (ms) can be used for accessing the external circuit. And 7
, 688 (ms)/16 (us) = 480.5, so the timer circuit 26 that measures a certain period of time is l/4.
80 counters are available.

Effects of the Invention The invention described in claim 1 connects a bus arbiter that outputs a refresh execution signal to a dynamic RAM connected to a control circuit that executes refresh, and connects a refresh time generator that outputs a refresh request signal to this bus arbiter. The output line from the refresh time generator to the bus arbiter is connected to the addition input, and the output line from the bus arbiter to the dynamic ram is connected to the subtraction input to connect an up-down counter that outputs the count number in a compressed state to the bus arbiter. When the refresh request signal is output from the refresh time generator to the bus arbiter, the count number of the up-down counter is added, and when the bus arbiter outputs a refresh execution signal and refresh of the dynamic ram is executed, the count number of the up-down counter increases. When the bus arbiter delays the output of the refresh execution signal according to the access of the external circuit and the count number of the up-down counter is added, the refresh execution signal according to the count number of the up-down counter is added at the end of the access of the external circuit. By outputting to the dynamic RAM in a compressed state and eliminating refresh delays, bus usage efficiency is improved and external circuits can effectively access the dynamic RAM, speeding up information processing operations. It has effects such as being able to contribute to.

The invention according to claim 2 provides an up/down system in which the output line from the refresh time generator to the bus arbiter is connected to the addition input, and the output line from the bus arbiter to the dynamic ram is connected to the subtraction input, so that the bus arbiter receives the count number. A counter is connected, and a refresh cycle timer is connected that periodically outputs a refresh priority command to the bus arbiter in accordance with the refresh cycle of the dynamic RAM. When a refresh request signal is output from the refresh time generator to the bus arbiter, the up/down counter is activated. When the count number is added and the bus arbiter outputs a refresh execution signal to refresh the dynamic ram, the count number of the up/down counter is subtracted, and the refresh priority instruction is output from the refresh cycle timer according to the refresh cycle of the dynamic ram. When this happens, a refresh execution signal is output from the bus arbiter to the dynamic RAM according to the count number of the up/down counter, and refresh is executed a predetermined number of times during the cycle, thereby improving bus usage efficiency. This allows external circuits to effectively access the dynamic RAM, which contributes to speeding up information processing operations.Moreover, since the refresh operation is forcibly performed before the end of the dynamic RAM refresh cycle, external circuits can effectively access the dynamic RAM. This has the effect of preventing the storage contents of the dynamic RAM from being erased due to long circuit accesses.

FIG. 6 is a block diagram showing the first conventional example, FIG. 7 is a block diagram showing the second conventional example, and FIG. 8 is a time chart of the first and second conventional examples.

3...Dynamic ram, 5...Bass, 6,7...
・External circuit, 15... Control circuit, 18...
Refresh control circuit, 19... bus arbiter, 20
... Refresh time generator, 21... Up/down counter, 22... Addition input, 23...
Subtraction input, 25...Refresh cycle timer

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a flow chart of the embodiment of the present invention, FIG. 3 is a time chart of the embodiment of the present invention, and FIG. 4 is a modification of the embodiment of the present invention. A flowchart showing an example, and FIG. 5 is a time chart of a modification of the embodiment of the present invention.
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Claims (1)

[Scope of Claims] 1. A bus arbiter that outputs a refresh execution signal to a dynamic RAM connected to a control circuit that executes refresh, and a refresh time generator that outputs a refresh request signal to this bus arbiter.
An up/down counter whose output line from the refresh time generator to the bus arbiter is connected to an addition input, and whose output line from the bus arbiter to the dynamic ram is connected to a subtraction input to output a compressed count number to the bus arbiter. Therefore, when a refresh request signal is output from the refresh time generator to the bus arbiter, the count number of the up/down counter is added, and the bus arbiter outputs a refresh execution signal to execute the refresh of the dynamic ram. and the count number of the up-down counter is subtracted, and when the bus arbiter delays the output of the refresh execution signal according to the access of the external circuit and the count number of the up-down counter is added, the count number of the up-down counter is subtracted. A refresh control circuit characterized in that a refresh execution signal according to the count number of an up-down counter is output to the dynamic RAM in a compressed state to eliminate refresh delay. 2. A bus arbiter that outputs a refresh execution signal to a dynamic RAM connected to a control circuit that executes refresh, and a refresh time generator that outputs a refresh request signal to this bus arbiter.
an up/down counter having an output line from the refresh time generator to the bus arbiter connected to an addition input, and an output line from the bus arbiter to the dynamic ram being connected to a subtraction input to output a count to the bus arbiter; It consists of a refresh cycle timer that periodically outputs a refresh priority command to the bus arbiter in accordance with the refresh cycle of the dynamic RAM, and when a refresh request signal is output from the refresh time generator to the bus arbiter, the up/down counter starts counting. When the number is added and the bus arbiter outputs a refresh execution signal to execute refresh of the dynamic ram, the count number of the up/down counter is subtracted;
When a refresh priority command is output from the refresh cycle timer according to the refresh cycle of the dynamic RAM, a refresh execution signal according to the count number of the up/down counter is output from the bus arbiter to the dynamic RAM a predetermined number of times during the refresh cycle. A refresh control circuit characterized in that a refresh is executed.