JP2913099B2 - DRAM refresh device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a DRAM refresh device for refreshing a DRAM.

[Problems to be solved by the prior art and the invention]

Conventionally, DRAM refresh methods include a method of refreshing at a fixed time interval using a timer,
How to refresh when accessing other than
There are various methods.

However, in the method of refreshing at a fixed time interval by the above timer, the refresh is surely completed, but the refresh is performed at a fixed time interval regardless of the DRAM access by the CPU. Therefore, there is a problem that the processing time of the CPU is lost.

The method of refreshing when the CPU is accessing a device other than the DRAM is refreshing, for example, when the CPU processes the program on the DRAM or when the program loaded into the cache memory is looped and the external access is not performed for a long time. However, there is a problem that there is a condition that cannot be performed completely.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and provides a DRAM refresh device that eliminates the above problems, has less collision with DRAM access by a CPU, and can surely perform refresh within a fixed time. Is to do.

[Means for solving the problem]

In order to solve the above problems, the present invention provides a DRAM refresh device having the following configuration.

A timer that completes refresh and is reset by timeout of a fixed time, a refresh address counter that generates a refresh address, and a refresh request signal that generates a refresh request signal at a timing from the CPU under conditions that do not conflict with DRAM access by the CPU. A first refresh request generating circuit, a second refresh request generating circuit for generating a refresh request signal at predetermined time intervals at a timing from the CPU irrespective of access to the DRAM by the CPU, and a first refresh request generating circuit And a DRAM timing generation circuit for generating a refresh cycle in response to a refresh request signal from a second refresh request generation circuit, wherein the DRAM generates a refresh request signal from the first refresh request generation circuit while the timer does not time out. Departure The refresh request signal from the second refresh request generating circuit is input to the DRAM while the timer is timed out and is not reset.
The refresh address is input to the timing generation circuit and the refresh address counter, and the refresh address is input to the DRAM timing generation circuit from the refresh address counter.

[Action]

By adopting the above configuration in the DRAM refresh device, when the timer has not timed out, there is still enough time to refresh the DRAM, so that the refresh request signal of the first refresh request generation circuit is sent to the DRAM timing generation circuit. To avoid collision with DRAM access by CPU. On the other hand, when the timer has timed out, the time margin for refreshing the DRAM is reduced, so the refresh request signal of the second refresh request generating circuit is input to the DRAM timing generating circuit, and the DRAM is generated by the CPU. Priority is given to access, and one cycle of refresh is completed in a short time. Therefore, this DRAM
According to the refresh device, the access of the CPU and the refresh of the DRAM are less likely to collide with each other, and the refresh can be surely performed.

〔Example〕

Hereinafter, an embodiment of the present invention will be described with reference to the drawings.
FIG. 1 is a block diagram showing a circuit configuration of a DRAM refresh device of the present invention. As shown in the figure, a timer counter 11 that can set a fixed time (this fixed time is determined by the specification of the DRAM used), a refresh address counter 12 that generates a refresh address, and does not conflict with CPU access. A first refresh request generating circuit 13 for generating a refresh request signal under conditions, a second refresh request generating circuit 14 for generating a refresh request signal prior to CPU access, a DRAM timing generating circuit 15, a NAND gate 16, and This is a circuit configuration including a selector 17.

CPU timings are input to the first refresh request generation circuit 13 and the second refresh request generation circuit 14, respectively. The first refresh request generation circuit 13 receives an access signal from the CPU other than the DRAM.

When the refresh of the DRAM is completed within the fixed time, that is, during the counting of the timer counter 11, when the timer counter 11 times out, both the timer counter 11 and the refresh address counter 12 are reset, and Enter refreshing.

If timer counter 11 times out
If the DRAM refresh has not been completed,
The timer counter 11 stops in a time-out state. When the refresh of the DRAM is completed (when the output CO of the refresh address counter 12 becomes "1"), the timer counter 11 and the refresh address counter 12 are both reset by the output of the NAND gate 16, and the next DRAM is reset. Enter refresh.

One of the two refresh request signals of the first refresh request generating circuit 13 and the second refresh request generating circuit 14 is selected by the selector 17 and is input to the DRAM timing generating circuit 15, and at the same time, the refresh address counter 12 Is input to Further, the refresh address is input from the refresh address counter 12 to the DRAM timing generation circuit 15.

The selection of the refresh request signal is performed depending on whether or not the timer counter 11 is in a time-out state. That is, when the timer counter 11 has not timed out, there is still enough time to refresh the DRAM, so that the refresh request from the first refresh request generation circuit 13 is used to avoid collision with the DRAM access by the CPU. A signal (here, a refresh request signal is generated when the CPU accesses other than the DRAM) is selected by the selector 17.

On the other hand, when the timer counter 11 has timed out, since the time margin for refreshing the DRAM is reduced, it is necessary to complete one kind of refresh in a short time. 14
The selector 17 selects a refresh request signal issued from the CPU irrespective of DRAM access by the CPU. At this time, although not shown, the selector 17 notifies the CPU that the DRAM is being refreshed by the second refresh request generation circuit 14, and the CPU receives the notification and receives the DRAM.
Access is stopped. That is, the refresh request signal of the second refresh request generating circuit 14 is
Give priority to DRAM access by the CPU.

FIG. 2 is a diagram showing the state of the timer counter 11 and the condition of the refresh request. As shown in the figure, in the period A, the refresh is completed before the timer counter 11 has timed out (the refresh address counter 12 reaches a predetermined count value at which the count of the refresh request signal has been completed, and one type of refresh of the DRAM has been completed). Since there is enough time, the refresh request signal of the first refresh request generation circuit 13 is selected by the selector 17 and input to the DRAM timing generation circuit 15. Further, since the period B is a period in which the timer counter 11 has not timed out, the refresh request signal of the first
The signal is input to the AM timing generation circuit 15. In the period C after the timer counter 11 times out, there is no time margin, so the refresh request signal of the second refresh request generating circuit 14 is selected by the selector 17 and input to the DRAM timing generating circuit 15. During the period D, the refresh is completed while the timer counter 11 has not timed out, so that the signal of the first refresh request generation circuit 13 is input to the DRAM timing generation circuit 15 as in the period A.

〔The invention's effect〕

As described above, according to the present invention, the timer is used, and when there is enough time for the refresh, the DRA by the CPU is used.
A refresh request signal from the first refresh request generation circuit that issues a refresh request signal so as not to conflict with the access of M is input to the DRAM timing generation circuit. Since the refresh request signal from the second refresh request generation circuit that issues the request signal is input to the DRAM timing generation circuit, the access and refresh of the CPU are less likely to collide with each other as a whole, and the refresh is reliably completed within a certain time. An excellent effect that such a DRAM refresh device with a small load on the system can be provided is obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a circuit configuration of a DRAM refresh device of the present invention, and FIG. 2 is a diagram showing a state of a timer counter and a condition of a refresh request. In the figure, 11 a timer counter, 12 a refresh address counter, 13 a first refresh request generating circuit, 14 a second refresh request generating circuit, 15 DR
AM timing generation circuit, 16 NAND gate, 17 selector.

Claims (1)

(57) [Claims] A timer resetting upon a timeout of a predetermined time after a complete refresh, a refresh address counter for generating a refresh address,
First, a refresh request signal is generated at a timing from the CPU under conditions that do not conflict with DRAM access by the CPU.
Refresh request generating circuit, a second refresh request generating circuit for generating a refresh request signal at a predetermined time interval at a timing from the CPU irrespective of DRAM access by the CPU, and a first refresh request generating circuit Alternatively, a refresh cycle is generated by a refresh request signal from a second refresh request generation circuit.
A DRAM timing generation circuit, and while the timer does not time out, a refresh request signal from the first refresh request generation circuit is input to the DRAM timing generation circuit and to the refresh address counter; During a time-out period and no resetting, the refresh request signal from the second refresh request generating circuit is sent to the DRAM.
A DRAM refresh device, wherein the refresh address is input to a timing generation circuit and the refresh address counter, and a refresh address is input from the refresh address counter to the DRAM timing generation circuit.