JP2617132B2 - Direct memory access method - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a direct memory access system.

[Conventional technology]

Conventionally, this type of direct memory access method includes a DMA controller LSI in a microcomputer system, and based on a data handling request from I / O,
The MAC outputs a hold request to the μCOM, and when the μCOM enters the hold state, the DMAC occupies the data bus and the address bus of the μCOM system and performs the DMA operation.

[Problems to be solved by the invention]

The conventional direct memory access method has a drawback that the DMA transfer cannot be performed by the μCOM having no hold function because the DMA transfer is performed during the hold state of the μCOM.

[Means for solving the problem]

The direct memory access method of the present invention includes a μCOM having a refresh pulse output function for a dynamic memory, a memory address counter I / O unit, and a timing generator.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

 FIG. 1 is a block diagram of one embodiment of the present invention.

1 is a microcomputer having a refresh pulse output function, 2 is an I / O, 3 is a memory for DMA, 4 is a timing generator, 5 is an address counter for DMA, and 6 is a signal from the μCOM in the normal mode for the DMA memory. Address bus and R / W selector for switching address and R / W from address counter in DMA mode.
A gate for separating the data bus from the I / O and the data bus between the memory for DMA from the COM, an address decoder 8 for selecting the I / O, and a DMA mode 9 for R / W and CS for the I / O. And a selector for switching between those from the DMA timing generator and those from the μCOM in the normal mode and the normal mode.

 The DMA operation of this circuit is as follows.

(1) When DMA transfer is required in I / O A DMA request signal is output from the I / O to the DMA timing generator 4.

(2) When the request signal is input, the DMA timing generator 4 outputs a DAM acknowledge signal at the rising edge of the refresh pulse from μCOM.

(3) Selector / selector of each part by DMA acknowledge signal
At the same time as setting the gate to the DMA mode, the value of the address counter 5 is set to +1.

(4) The DMA timing generation unit 4 outputs an I / O read pulse at the time of an I / O-to-memory transfer and a write pulse to the memory at a timing at which the address is stabilized from the above output timing, and outputs an I-O pulse at the time of a memory-to-I / O transfer. Outputs a write pulse to / O and a read pulse to memory. The timing example at this time is
Shown in the figure.

〔The invention's effect〕

As described above, the direct memory access method of the present invention has a hold function by performing a DMA transfer in the refresh cycle of the μCOM DRAM refresh function, enabling the μCOM DMA transfer, and further holding the μCOM in the hold state. There is an effect that high-speed data transfer can be performed without causing the data transfer.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG. 2 is a time chart showing the operation of the direct memory access system shown in FIG. 1 ... microcomputer, 2 ... I / O section, 3 ... DMA
... DMA timing generator, 5... DMA address counter.

Claims (1)

(57) [Claims] 1. A direct memory access method in a microcomputer system, wherein a direct memory access transfer is performed during a refresh cycle by using a refresh pulse output for a dynamic memory of the microcomputer.