JPH04316279A - Color picture encoder - Google Patents

Abstract

PURPOSE:To encode a sharp picture of less degradation with a high compression rate by discriminating whether each block of a multilevel color signal is an edge part or not and subjecting the edge part to entropy encoding after binarization. CONSTITUTION:A multilevel color picture signal 100 of each color read out from a picture memory 20 is converted to one-bit binary color signals of R, G, and B by binarization processing of each color in a binarizing circuit 21. It is discriminated whether each block of the multilevel color picture signal 100 is an edge part or not by a block edge discriminating part 19. A binarizing signal 101 is selected by a block discrimination signal 111 with respect to the block discriminated as the edge part, and entropy encoding is performed after binarization, thereby encoding the sharp picture of less degradation with a high compression rate.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a color image encoding device used for color image communication and the like.

0002

2. Description of the Related Art Various proposals have been made regarding color still image encoding systems. Furthermore, the target color still images can be roughly divided into the following two types. (1) Red, green, blue, cyan, magenta, yellow, white, black 8
A binary color image that handles colors as binary values.
As a multivalued color image or binary color image encoding method for displaying a million colors, a method using a modified Huffman method, which is a variable length encoding method currently used in facsimiles, etc., for each color has been considered. As another method, a predictive encoding method has been proposed in which a coded pixel is predicted from surrounding pixels. These methods fall under the category of lossless encoding, and data is preserved during encoding and decoding.

On the other hand, as a multilevel color image encoding method, after converting each 8-bit RGB signal into a luminance/chrominance signal, orthogonal transform (discrete cosine transform) is performed, the coefficient values are linearly quantized, and the quantized values are A method of variable length encoding has been proposed. This method basically reduces image data by leaving the low frequency side of the spatial frequency of the image and cutting the high frequency side. This method is a lossy encoding method, and there is a trade-off between compression rate and image quality deterioration.

[0004] Hierarchical encoding of multivalued color images using the trade-off between compression rate and image quality has also been considered. This method reduces a multilevel image by subsampling, quantizes it, encodes it, creates a low-resolution hierarchical image,
This is a method in which a difference image between an original image and a decoded low-resolution image is quantized and then encoded to create a high-resolution hierarchical image. The number of layers may be increased depending on the level of subsampling. In this method, a low-resolution image with a small amount of data is encoded first, so that the image can be grasped at an early stage.

[0005]

However, according to the conventional example described above, a color document image in which a color photograph is embedded in a color document is to be encoded. (1) In the binary color method, even if a color text part can be encoded with a high compression rate, it is not possible to efficiently encode a gradation image in a color photograph part. (2) In the multilevel color method, as the compression rate is increased, the high frequency components of the image are largely cut off, and the image quality deterioration at edges such as text becomes noticeable. Compression rate is not as expected. There are problems such as:

[0006] It is also conceivable to increase the compression rate of low-resolution image parts by using hierarchical encoding of multi-valued color images;
After all, image quality deteriorates significantly for color documents or images containing many edge portions, and there remains a problem in early understanding of the entire image.

[0007]

[Means for Solving the Problems] The present invention has been made in view of the above points, and is capable of handling not only multi-value color images and binary color images, but also multi-value color images and binary color images. The purpose of this method is to encode color images well as well.

The present invention classifies a color image into edge portions and non-edge portions for each component in M×N blocks, and compresses edge portion blocks using the binary color method described in (1) above. This preserves the image quality of color text, etc. Furthermore, for blocks in non-edge areas, high compression is achieved by using the multi-value color method described in (2) above.

[0009] At the same time, by further performing binary color image hierarchical encoding on the blocks in the edge portion, it is possible to realize an image with less deterioration in the edge portion at an early stage.

0010

EXAMPLES The present invention will be explained below using preferred examples.

FIG. 1 shows the configuration of an embodiment of a code section to which the present invention is applied.

The image memory 20 stores red (R), green (G), and blue (B) images representing full-color images input from a color still image input means such as a color scanner (not shown).
) Thus, an 8-bit multivalued color image signal is stored.

The multivalued color image signal 100 of each color read out from the image memory 20 is converted into two signals for each color by a binarization circuit 21.
It is subjected to value processing and converted into a binary color signal of 1 bit each for R, G, and B.

Furthermore, the multivalued color image signal 100 is subjected to a block edge determination section 19 that determines whether or not each block is an edge portion. In this embodiment, an 8×8 image is used as a block to determine whether it is an edge portion or a non-edge portion.

The signal binarized by the binarization circuit 21 is masked by a mask signal 110 by a selector section 28 for each block.

That is, for a block determined to be an edge portion by the block edge determination circuit 19, the binary signal 101 is selected by the block determination signal 111. Furthermore, for blocks determined to be non-edge parts, the mask signal 0
is selected. Therefore, only the edge image of the binarized image is stored separately for each color in the binary image memory 22 via the line 102.

The binary color signal 108 read from the binary memory 22 is encoded by an encoder A for encoding a binary color signal, and a code word 105 is output. This encoder A
The encoding process is the first encoding process.

Next, the same color image signal that has been subjected to the first encoding process described above is read out from the image memory 20. This color signal encodes parts other than the binary edge image encoded by the first encoding. The binary edge image is input from line 102 to level converter 29 . Here, the binary signal is converted from 0.1 to 0.255 (8 bits).

The level-converted binary image 104 is subtracted from the multi-value color signal 112 by a subtractor 23. The difference signal is stored in the difference multi-value memory 24 via 107 for each color R, G, and B. The multi-value color signal 109 in the differential multi-value memory 24 is encoded by an encoder B for multi-value color signal encoding, and a code word 106 is output. The above encoding process by encoder B is the second encoding process.

The block edge determining section 19 uses the following determination in this embodiment. FIG. 2(a) shows an example. For each block (in this example, 8
(×8 pixels is defined as one block, but the block unit is not limited to this) Edge detection is performed for each of RGB.

As a method for detecting this edge, FIG. 2(a) shows the difference P=L between the maximum value MaxL and the minimum value MinS in the block.
-S is calculated, and if P is equal to or greater than a certain value (T=70, but the overall level is 256), an edge exists.

[0022] It can also be realized using a method as shown in FIG. 2(b).

In FIG. 2(b), DCT transform is performed for each 8×8 block, and the sum of the absolute values of the AC portions excluding DC among the transformed coefficients is determined.

[0024]

[Example 1] If S is a certain value or more, it is determined that it is an edge portion. In this method, the sum of the AC coefficients is shown in the shaded area, but it is also possible to make a determination using only some of these coefficients.

FIG. 3 shows the relationship between the multivalued color image signal, the binary edge image, and the differential multivalued image read out from the image memory 20.

In this embodiment, edge determination is performed in units of 8×8 pixel blocks, and FIG. 3 shows an example when an 8×8 pixel block is viewed one-dimensionally. For blocks determined to be edges, a multivalued color image signal M (Fig. 3 (
The image a)) is binarized using the threshold TH, and the image after level conversion (0.255) is the binary edge image B as shown in FIG. 3(b).

The differential multivalued image S shown in FIG. 3(c) is composed of M and B.
The absolute value of the difference, that is, S=|M−B
It is obtained by |

In this embodiment, the absolute value of the difference is taken in order to avoid negative differences. This portion is indicated by diagonal lines in FIG. 3(c). As a result, it is possible to divide the image into a binary edge image B containing high frequency components and a differential multivalued image S containing low frequency components. The threshold TH for binarization is TH.
>128 (for 8 bits) is preferred. This is because if TH is small, high frequencies tend to remain in the differential multivalued image.

In this embodiment, the image quality of the edge portion is maintained by completely preserving the binary edge image using entropy encoding, and the difference image, which is a low frequency component, is encoded using a multi-level data code with high encoding efficiency. By doing so, highly efficient and good encoding can be achieved.

Furthermore, by sending a binary color image with a small amount of data in the first stage, the receiving side decodes and displays only the first stage, so that the received image can be checked at an early stage.

[0031] Subsequently, in the second stage, a differential multivalued image is sent and decoded on the receiving side, and the second layer is decoded by adding the difference multivalued image to the binary edge image decoded in the first stage. This is to realize the realization of

[0032] The differential multivalued image can be encoded by various well-known block encoding methods. In this embodiment, a method is adopted in which DCT transform is performed for each 8×8 pixel block and the transform coefficients are Huffman encoded.

FIG. 4 shows an example of the differential multivalued image encoders 25 and 26 in this embodiment.

The image signal 109 read from the difference memory 24 in FIG. 1 is converted from an RGB signal to a luminance/color difference signal 900 in a color converter 55. The following formula is generally used for this conversion. Y=0.299R+0.587G+0.114BCr=
0.713 (RY) Cb=0.564 (B-Y) However, R, G, B, Y, Cr, and Cb shown here are standardized values.

Next, the orthogonal transform circuit 56 transforms the image of each 8×8 pixel block into transform coefficients (intensities) for each frequency by discrete cosine transform. The transform coefficients shown in Figure 5 are also 8x8 blocks, and the transform values range from 1 to 6.
Number it 4. Coefficient number 1 indicated by 500 indicates the DC component. In addition, coefficient number 2 indicated by 501 and 502
, 3... indicate alternating current components, and as the number increases, it indicates alternating current components from low frequency to high frequency.

The transform coefficient signal 901 is quantized to, for example, 8 bits by the linear quantizer 57. This linear quantizer 5
In No. 7, the quantization steps are determined so that the quantization steps for direct current and low frequencies are fine, and the quantization steps for high frequencies are coarse.

In the Huffman encoding unit 62, a DC component (coefficient number 1 in FIG. 5) and an AC component (coefficient number 2 in FIG.
~64) are each encoded separately. Further, in these encodings, the DC component and the AC component are Huffman encoded in the order of Y, Cr, and Cb, respectively.

As for the DC component, a DPCM Huffman code is used in which a Huffman code is assigned to the difference from the DC component of the previous block.

Regarding the DC component, the coefficient numbers 2 to 64 are scanned in a zigzag manner for each block as shown in FIG.
This is a method of assigning a Huffman code based on the statistics of the run where the coefficient is 0 and the next coefficient value.

As described above, the image is encoded into a differential multivalued image and an output 106 is obtained.

In this embodiment, early recognition of the image is possible by encoding a binary color image with a small amount of data in the first stage, but the binary color image in the first stage further encodes the image in a hierarchical manner. It is even more efficient to grasp the entire image by digitizing the image.

FIG. 6 is an example in which the binary color image encoding section (encoder A25 in FIG. 1) is realized by hierarchical encoding. The blocks in FIG. 6 are adapted to each of the color components (R, G, B, three colors in this embodiment). Therefore, as the input in Fig. 6, the binary image memory) 2
2, images are input for each color.

[0043] 402 to 404 are 1/2 and 1/4, respectively.
, a frame memory for storing a 1/8 reduced image;
405 to 407 are reduction units that generate 1/2, 1/4, and 1/8 reduced images, respectively, and 408 to 411 are 1/2, 1/4, and 1/8 reduction units, respectively.
This is an encoder that encodes reduced images of /8, 1/4, 1/2, and 1.

The reduction unit 405 reduces the image from the binary image memory 22 to 1/2 in both the main scanning and sub-scanning directions using a method such as subsampling, generates a 1/2 size image, and stores the image in the frame memory 402. Store. Furthermore, the 1/2 size image is reduced by the reduction unit 406 to create a 1/4 size image and stored in the frame memory 403, and similarly, the reduction unit 407 creates a 1/8 size low resolution image, and the frame The data is stored in the memory 404.

[0045] By sequentially transmitting codes starting from low-resolution images, a rough overall image can be quickly grasped.

[0046] In this embodiment, the binary hierarchical encoding has four levels, but any number of levels can be used.

In the example shown in FIG. 6, the image is reduced to 1/2, 1/4, and 1/8 in both the main scanning and sub-scanning directions, and the encoding is reduced to 1/8.
In this example, images are transmitted in the order of 8, 1/4, 1/2, and 1 (original size image). To encode a 1/8 image, the 1/8 images stored in the frame memory 404 are sequentially scanned, and the encoder 409 performs entropy coding such as arithmetic coding with reference to the pixel of interest to be encoded and surrounding pixels. For 1/4 image, frame memory 404
Encoding is performed by the encoder 409 by referring to the surrounding pixels of the pixel of interest from the frame memory 404 and the surrounding pixels of the 1/8 image from the frame memory 404, thereby increasing the coding efficiency. Similarly, for the 1/2 image in the frame memory 402, the 1/4 image in the frame memory 403 is
The original size image 01 is encoded by encoders 410 and 411, respectively, with reference to the 1/2 image in the frame memory 402.

[0048] By performing such binary image hierarchical encoding for each color, transmitting it sequentially, and decoding it sequentially on the receiving side, it is possible to realize color hierarchical encoding that allows a more rough overall image to be grasped quickly. .

FIG. 7 shows the configuration of an embodiment of a decoding section to which the present invention is applied.

The code word 105 of the binary color image is sent to the decoder A.
30, each color is restored to a dot image and stored in binary memory 3.
3 is stored. This dot image completely restores the binary signal stored in the binary memory 22 of FIG.

[0051] Furthermore, the code word 106 of the differential multivalued color image
is restored to multivalued image data for each color by the decoder B31 and stored in the difference memory 34. The data stored in the differential memory 34 corresponds to the differential multilevel signal stored in the differential memory 24 in FIG.

In the synthesizer 35, R from the binary memory 33
The image obtained by level-converting the 1-bit signal 713 for each GB and the difference signal 714 from the difference memory 34 are combined to form a signal 715.
is obtained and stored in the image memory D36. As shown in FIG. 14, image synthesis in the synthesizer 35 combines the binary edge decoded image (A) and the differential multi-value decoded image (B) to obtain a multi-value color decoded image as shown in (C).

FIG. 8 is a block diagram of a decoder that hierarchically decodes the binary color decoder A30 of FIG. 7.

The binary color image hierarchically decoded for each color is input to 105 for each color (R, G, B). First, the 1/8 reduced image decoded by the gate unit 251 is input to the decoder 252 from the line 201 and decoded.

The decoded image is stored in the frame memory 25
It is stored in 6. Next, the encoded 1/4 image is similarly input from the gate section 251 to the decoder section 253 via the line 202. To decode a 1/4 image, the decoder unit 253 refers to the surrounding pixels that have already been decoded and the surrounding pixels of the 1/8 image that has been decoded and stored in the frame memory 256. is memorized.

Similarly, in the case of 1/2 image, the decoder 254
For the 1 (binary original image) image, the decoder 255
The images are decoded by referring to the surrounding pixels in the 1/4 image and 1/2 image, respectively, and the surrounding pixels that have already been decoded.

The decoded 1/2 image is stored in frame memory 2.
58. One decoded image is stored in the binary memory 33 of FIG. 3 from line 711.

Since the decoded 1/8, 1/4, and 1/2 images are encoded hierarchically, the results are stored in the video memory 2.
59 and can be viewed on a monitor 260. Therefore, early understanding of the decoded image becomes possible. Furthermore, among the images hierarchically encoded in this way, the lowest resolution image (1/8 image in this embodiment) has a small amount of data and is small in size, so it can be used as an icon image for image search. In other words, by combining only this image at the time of search, the entire image can be understood.

For decoder B31, encoder B in FIG.
It can be easily decoded by performing the inverse transformation of . That is, decoding is possible by decoding the Huffman codes of the DC and AC components, configuring DCT coefficients for each 8×8 pixel block, and then performing inverse DCT transformation.

In the encoding of the binary image, a dynamic arithmetic code is used in this embodiment, the details of which are described below. Figure 4
The encoder A in FIG. 6 is the encoder 409, 410,
411 details. Since each encoder operates in the same way, encoder 411 will be explained.

The binary data of the image to be encoded from the binary memory 22 enters the prediction state determination circuit 50 of FIG. 4 via 108. At the same time, a 1/2 reduced image of the encoded image is input from the frame memory 402 in FIG. 6 to the prediction state determining circuit 50.

[0062] The prediction state determination circuit 50 outputs a prediction state signal S914 composed of surrounding encoded pixels including the reduced image regarding the pixel of interest. It also outputs encoded pixel data ×915 in synchronization with S116, and both signals are input to the dynamic arithmetic encoder 53 and encoded.

FIG. 9 is a block diagram of the predicted state determination circuit 50. An encoded image and a reduced image are input to 108 and 102, respectively. A coded image is an image to be coded in binary image hierarchical coding,
The reduced image is an image obtained by reducing the encoded image to 1/2 vertically and horizontally, and is an image that has already been encoded.

Reference numeral 661 is a line memory for storing the pixel state in order to refer to the line one line before the encoded pixel, and 662 is a line memory for storing the line before the line corresponding to the encoded pixel in the reduced image.

Numerals 663 to 670 are latches for storing surrounding states of encoded pixels, and latches 671 and 672 are latches for storing surrounding pixel states in a reduced image. The encoded image and the reduced image have pixel clocks φ602 and φ, respectively.
2 603, line memories and latches are shift controlled.

[0066] Also, horizontal synchronization H1604, H2
Line control is performed by 605. Here, since the reduced image is 1/2 both vertically and horizontally of the encoded image, the pixel clock frequency and horizontal synchronization frequency are controlled by the following relationship.

φ1=2φ2H1=2H2

The encoded pixel is the pixel value stored in the latch 664 x9
15, it is input to the dynamic arithmetic unit (53 in FIG. 4) and encoded.

At this time, as for the surrounding pixel states necessary for encoding, seven pixels around the encoding pixel are referred to as the values of the line memory 661 and latch outputs 665 to 670.

For the reduced pixel, the line memory 6 which is the same pixel as the reduced position pixel value 201 of the encoded pixel position
The output of 62 and the values of a total of four pixels of latches 671 and 672 are referred to.

The state of these 11 reference pixels in total is S9.
16 to the dynamic arithmetic unit 53 for state prediction.

FIGS. 10(a) and 10(b) are diagrams showing surrounding reference pixels for these state predictions. encoded image,
The reduced images refer to surrounding 7 pixels and 4 pixels, respectively. One reference pixel in the reduced image corresponds to four reference pixels in the encoded image.

FIG. 11 is a block diagram of the dynamic encoder 53 shown in FIG.

Before explaining FIG. 11, the arithmetic codes used in this embodiment will be explained.

As is conventionally known, the arithmetic code is
This is a method in which a code is formed by arithmetic operations so that the input signal string becomes a code expressed in binary decimal numbers. This method is described in the paper “Compression of Black/Wh” by Langdon and Rissanen et al.
ite Images With Arithm
etic Coding", IEEE Tran
Com. Published in COM-29, 6, (1981.6), etc. According to this document, the already encoded input signal sequence is S, the probability that a least-likely symbol (LPS) will appear is q, and the arithmetic register A is
When ugend is A(S) and the code register is C(S), the following arithmetic operation is performed for each input signal.

A(S1)=A(S)×q≒A(S)×2−Q…(1)
A(S0)=〈A(S)−A(S1)〉l…(2)〈
〉l represents truncation in significant digits C(S0)=
C(S)…(3) C(S1)=C(S)+A(S0)…(4)

0077
]Here, if the encoded data is a dominant symbol (MPS: 0 in the above example), A(S0) and C(S0) are used to encode the next data. Furthermore, in the case of a less-likely symbol (LPS: 1 in the above example), A(S1) and C(S1) are used to encode the next data.

The new value of A is multiplied by 2s (S is an integer greater than or equal to 0) and falls within the range of 0.5<A<1.0. This processing corresponds to shifting the calculation register A S times in hardware. The code register C is also shifted the same number of times, and the shifted out signal becomes the code. The above process is repeated to form a code.

Furthermore, as shown in equation (1), the LPS appearance probability q is approximated by a power of 2 (2-Q: Q is a positive integer), thereby replacing the multiplication calculation with a shift calculation. To make this approximation even better, let q be changed to, for example, (5
) is approximated by a polynomial of a power of 2. This approximation improves the worst point of efficiency.

[0080]q≒2-Q1+2-Q2...(5)

008
1] Furthermore, since the arithmetic code allows the value of Q to be switched for each encoded data, the probability estimation section can be separated from the encoding.

In this embodiment, as described above, a dynamic method is used in which the probability is estimated while performing encoding.

The encoder 53 of FIG. 4 performs the above arithmetic coding.
The block diagram will be explained below.

The state signal S916 from the predicted state determination circuit 50 in FIG. 4 is input to the counter memory 73 and the encoding condition memory 74.

The encoding condition memory 74 stores the status signal S9.
For each state represented by 16, a dominant symbol MPS 308, which is a symbol that is likely to appear, and an index 1307 indicating a coding condition including the probability of occurrence of LPS of an arithmetic code, which will be described later, are stored.

The MPS 308 read from the encoding condition indicator 74 according to the color and state of the image to be encoded is input to the predictive conversion circuit 77, where the serial pixel signal X117 from 50 in FIG. MPS30
A YN signal 301 which becomes 0 when it matches 8 is created.

The YN signal 301 is input to the update circuit 75, and the update circuit 75 increments the count of the corresponding state among the count values stored in the counter memory 73 when the YN signal is 0.

Then, the count value C306 stored in the counter memory 73 is stored in the count table ROM 72.
If it matches the set value MC305 from , the index I307 is updated in the direction of increasing (in the direction of decreasing the LPS appearance probability q). (The MPS is not inverted.) The count table ROM 72 updates the number MC305 of MPS shown in Table 1, which is determined corresponding to the index I representing the probability q of appearance of the LPS, by the update circuit 7.
Supply to 5.

Furthermore, in the update circuit 75, when the MPS 308 and the pixel signal direction). Also, if a YN signal with a value of 0 comes when the index is 1, the MPS is inverted (0 → 1 or 1 → 0
).

Output I'309 of update circuit 75, MPS'
310 is the updated index value, which is stored again in the encoding condition memory 74.

The encoding parameter determining circuit 76 sets the encoding parameter Q311 of the arithmetic code in the arithmetic encoder 78 based on the value of the index I307. In this arithmetic encoder 78, the YN signal 3 from the predictive conversion circuit 77 is
01 is arithmetic encoded using parameter Q311 and code 3
Get 02.

Note that static encoding can be easily realized by providing initial values to the encoding condition memory 74 and not updating I and MPS.

FIG. 12 is a block diagram of the predictive conversion circuit 77. Serial pixel signal X915 and MPS308 are EX
- The YN signal 301 is inputted to the OR circuit 79 and becomes 0 when the serial pixel signal X915 and the MPS 308 match, and becomes 1 when they do not match, according to the logical formula shown in Table 2.

FIG. 13 is a block diagram of the update circuit 75. When the YN signal 301 is 0, the count value C306 from the counter memory 73 is incremented by +1 by the adder 81 and becomes the signal C'312. This value is compared with MC305 from count table ROM 72 in comparator 83, and if the value of C' matches the value of MC, update signal U
Set PA313 to 1.

Furthermore, the YN signal 301 is the update signal UPB31.
4, and UPA and UPB are index change circuits 85
to go into. In addition, UPA and UPB are logically outputted by an OR circuit 97.
R is taken, and the output signal 315 of the OR circuit 87 becomes a switching signal for the selector 82.

When the signal 315 is 1, the selector 82 outputs a 0 signal 319 to reset the value of the counter memory 73.
Otherwise, the output signal C'312 of the adder 81 is selected and outputted as the counter update signal C''316, which is stored in the counter memory 73. Therefore, if the serial pixel signal X115 and MPS308 do not match, When the matching state continues a predetermined number of times, the counter memory 73
The count value will be reset.

The index change circuit 85 receives a signal d317 (standardly d=1) for controlling the index update step, and the current index I307 from the UPA 313, UPB 314, and encoding condition memory 74.

Table 3 is a table showing the index update method in the index change circuit 85 (Table 3 shows cases where the update increments are d=1 and d=2.) This table is used as the current index I, Update step condition d
, UPA, and UPB to determine the updated index I'.

Furthermore, when I=1 and UPB=1 (when serial pixel signal X115 and MPS308 do not match), E
Set the X signal 318.

When the EX signal 318 is 1, the inverter 86 inverts the symbol of the current MPS 308 (0→11 or 1→0) to obtain an updated MPS' 310. Furthermore, when the EX signal is 0, MPS' is not changed. updated I
'309 and MPS'310 are encoding condition memory 74
index I and MPS for next processing
used as.

Note that the updating method shown in Table 3 can be configured as a table using a ROM or the like, or it can be configured as a logic using an adder/subtractor.

As described above, when MPSs as many as the number of MPSs determined according to the value of the index I representing the appearance probability q of an LPS approximated by a polynomial of a power of 2 are generated, add d to the index I, LP used for arithmetic codes
The appearance probability q of S is made small, while when an LPS occurs, the index I is subtracted by d to make the appearance probability q of the LPS used for the arithmetic code larger. Furthermore, if an LPS occurs in a state where the LPS appearance probability q is 0.5 (a state where index I is 1), M
Invert PS.

[0103] In this way, by adaptively updating the index I and MPS to the input image, arithmetic coding with high coding efficiency can be achieved.

FIG. 14 is a coding efficiency curve of the arithmetic code used in this embodiment. Hereinafter, the value of index I will be indicated by a lowercase letter i. This curve is expressed by equation (6), where q is the probability of appearance of LPS, and qei is the approximate probability at the time of encoding. Then, indexes I are sequentially assigned as 1, 2, 3, etc. from the larger value of the LPS appearance probability q to the smaller value.

[0105]

(2) Here, the numerator is entropy, and qei is the value shown by formula (7).

qei=q1+q2 (7) The values of q1 and Q2 are polynomial approximation values of powers of 2 and are given in Table 4. For example, it is shown by (8) to (10).

qei'=2-1...(8) qe2'=2-
1 -2-4...(9) qe3'=2-2+2-3...(
10) In this probability, the peak point qei at which the efficiency η becomes 1.0 is called the effective probability. Furthermore, the intersection point of the efficiency curves is called the boundary probability qbi, and it is clear that the efficiency is improved by encoding using the adjacent effective probability at this point.

In this example, as shown in equation (5), 2
The effective probability q shown in Table 4 is calculated from the probability that can be approximated by two terms.
I am choosing ei. Furthermore, Q1, Q2, and Q3 in Table 4 are parameters Qc311 sent to the arithmetic encoder 78. That is, Q1 and Q2 are shift amounts given to the shift register, and a power of 2 calculation is performed by this shift operation. Further, Q3 indicates a coefficient of the second term, and switches between + and -.

The values of MC in Table 1 are determined as follows.

[0110] That is, the number of LPS is NL, and the number of MPS is N.
When M is assumed, the probability of LPS occurrence is given by equation (11).

[0111]

[Outer 3] Solving this equation using NM gives equation (12).

[0112]NM=“NL(1/q-1)”…(12)
However, "x" represents rounding up to the nearest whole number. Formula (1
By giving qbi shown in FIG. 11 to q in 2), the number NMi of dominant symbols (MPS) at the moment is calculated. Therefore, it is calculated from the MC wave equation (13).

MCi=NMi+1-NMi (13)

[
[0114] The values of MC in Table 1 are expressed by equations (11), (12),
It is calculated from (13) with NL=2.

In this way, each boundary probability qb as shown in FIG.
The number NMi of dominant symbols MPS corresponding to each index I is determined based on i, and the difference in the dominant symbols NM between adjacent indices is calculated as M corresponding to each index I.
Let it be C.

[0116] Then, the value of this MC and the number of generated dominant symbols MPS are compared as described above, and if the value of MC and the number of dominant symbols MPS match, the state is determined by the code using the neighboring index I. It is determined that the situation is suitable for
Change index I. As a result, the index I can be changed at a good timing based on the number of occurrences of dominant symbols MPS, and encoding using the optimum index I can be adaptively achieved.

FIG. 15 is a block diagram of arithmetic encoder 78.

Of the control signals Q311 (Table 4) determined by the code parameter determination circuit 76, Q1 is input to the shift register A90, Q2 to the shift register B91, and Q3 to the selector 92. Q1 and Q2 are AS Augend signals for shift registers A and B, respectively.
Indicates how many bits to shift 323 to the right. The shifted results become output signals 322 and 331.

The signal 331 is complemented by the inverter 96, and the selector 92 selects the signal 331 or the output signal of the inverter 96 by the control signal Q3, and outputs the output signal 3.
Get 32.

Adder 93 adds signal 322 from shift register A90 and signal 332 from selector 92, and outputs AS1 signal 324. The subtracter 94 subtracts the AS1 signal 324 from the AS signal 323, and
Obtain S0 signal 325.

[0121] In the selector 95, the AS0 signal 325 and the AS
1 signal 324 is selected by the YN signal 301. That is, when the YN signal is 1, the AS0 signal becomes the A' signal 326, and when the YN signal is 0, the AS1 signal becomes the A' signal 326.

In the shift circuit 89, the MSB of the A' signal is 1.
A shift process to the left is performed until the AS' signal 327 is obtained. The shift signal 332 corresponding to the number of shifts enters the code register 99, and the code register 99 outputs bits of the number corresponding to the number of shifts in order starting from the MSB.
becomes 0.

[0123] The code data 330 is processed by a bit processing method (not shown) so that the number of consecutive bits is within a finite number, and is transmitted to the decoder 14 side.

[0124] Also, the contents of code register 99 CR32
8 is added to the AS0 signal 325 in an adder 97 and enters the select 98. In addition, the signal CR328 that is not added to the AS0 signal 325 also enters the selector 98, and when the YN signal 301 is 1, CR'=CR, and when the YN signal is 0, CR'=CR+AS0. Output. The shift processing described above regarding code register 99 is also performed on the CR' signal.

[0125]

[Table 1]

[0126]

[Table 2]

[0127]

[Table 3]

[0128]

[Effects of the Invention] As explained above, according to the present invention,
For each block of the multivalued color signal, it is determined whether or not it is an edge part, and after binarizing the block that is an edge part,
By entropy encoding, a sharp image with little deterioration can be encoded at a high compression rate for binary colors at the edges of characters, lines, etc. Furthermore, for multivalued color images with few edges, such as color photographs, encoding is performed on low-frequency images excluding the edge portions, making it possible to encode at a high compression rate.

Furthermore, by hierarchically encoding the binary color image at the edge, an image with less deterioration can be encoded that preserves the edge, etc., even though the amount of data is small, and the entire image can be encoded at an early stage. It is something that realizes understanding.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a color image encoding device.

FIG. 2 is a diagram showing block edge determination.

FIG. 3 is a diagram showing differential operation.

FIG. 4 is a block diagram of an encoder.

FIG. 5 is a diagram showing conversion coefficients.

FIG. 6 is a block diagram of layered encoding.

FIG. 7 is a block diagram of a decoding device.

FIG. 8 is a block diagram of a decoding device.

FIG. 9 is a block diagram showing pixel references.

FIG. 10 is a diagram showing reference pixels.

FIG. 11 is a block diagram of an encoder.

FIG. 12 is a block diagram of a predictive conversion circuit.

FIG. 13 is a block diagram of an update circuit.

FIG. 14 is a diagram showing a coding efficiency curve.

FIG. 15 is a block diagram of an arithmetic encoder.

FIG. 16 is a diagram showing a decoding operation.

[Explanation of symbols]

20 Image memory 21 Binarizer 22 Binary memory 23 Subtractor 24 Differential memory 25 Encoder A 26 Encoder B

Claims (3)

[Claims] 1. A color image encoding device for encoding a multi-valued color image, characterized in that the image is separated into a binary color image and a multi-valued color image, and the binary color image is hierarchically encoded. Color image encoding device. 2. In the color image encoding device according to claim 1, it is determined for each M×N (M and N are natural numbers of 2 or more) pixel block whether the block includes an edge portion or not; Binarize the blocks containing , and mask (set to 0) the other blocks.
A color image encoding device that separates a binary color image into a multivalued color image obtained by taking a difference between the original image and the binary color image. 3. The color image encoding apparatus according to claim 1, wherein the multivalued color image is encoded independently of the binary color image.