JP3119373B2 - Image coding device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image encoding apparatus for efficiently encoding a multi-valued image such as a photograph and a binary image such as a character.

[0002]

2. Description of the Related Art Conventionally, various proposals have been made regarding a color still image coding system. Further, the target color still images are roughly classified into the following two.

[0003] Red, green, blue, cyan, magenta, yellow,
A binary color image that treats eight colors of white and black as binary A multi-valued color image that displays 16.7 million colors of red, green, and blue with, for example, 256 gradations

As a binary color image encoding method, a method using a modified Huffman method, which is a variable length encoding method currently used in facsimile and the like, for each color is considered.

[0005] As another method, a prediction coding method for predicting a coded pixel from surrounding pixels has been proposed.

[0006] These methods fall into the category of reversible coding, and data is preserved in coding and decoding.

On the other hand, as a multi-valued color image encoding method, after converting each of the RGB 8-bit signals into luminance / color difference signals, coefficient values subjected to orthogonal transformation (discrete cosine transformation) are linearly quantized, and the quantized values are calculated. Has been proposed to perform variable-length coding on. This method is basically a method in which the low-frequency side of the spatial frequency of an image is left and the high-frequency side is cut to reduce image data.

This method is an irreversible encoding method, and there is a trade-off relationship between the compression ratio and image quality deterioration.

[0009] Hierarchical encoding of a multi-valued color image using a trade-off between a compression ratio and image quality has been considered.

In this method, an image obtained by reducing a multi-valued image by subsampling or the like is quantized and then encoded to obtain a low-resolution hierarchical image, and a difference image between the original image and the decoded low-resolution image is quantized. After that, it is a method of encoding and encoding to obtain a high-resolution hierarchical image. The number of layers may be large depending on the subsampling level. According to this method, a low-resolution image with a small amount of data is encoded first, so that an image can be grasped at an early stage.

[0011]

However, in the case of encoding a color document image in which a color photograph is embedded in a color sentence according to the above conventional example.

In the binary color system, even if the color text portion can be encoded with a higher compression ratio, it is not possible to efficiently encode the gradation image of the color photographic portion.

In the multi-valued color system, as the compression ratio is increased, the high-frequency components of the image are largely cut, and the image quality of the edges of characters and the like deteriorates conspicuously. Compression ratio cannot be expected. There are problems such as.

It is conceivable to increase the compression ratio of a low-resolution image portion by using hierarchical coding of a multi-valued color image.
After all, the image quality of a color document or an image containing a large number of edges is greatly degraded, and a problem remains in grasping the entire image at an early stage.

[0015]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned prior art, and when encoding an original image into which an edge image is mixed, the encoding is performed as high as possible without deteriorating the image quality of the edge image. The main purpose is to encode at a compression rate.

In particular, in order to achieve the above object, the edge image and another difference image are separately coded.
At that time, an object is to perform efficient encoding in consideration of the property of the difference image.

[0017]

[0018]

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to preferred embodiments.

FIG. 1 shows the configuration of an embodiment of a coding section to which the present invention is applied.

The image memory 20 has a multi-valued 8-bit color image of each of red (R), green (G), and blue (B) representing a full-color image input from a color still image input unit such as a color scanner (not shown). The signal is stored.

The multi-valued color image signal 100 of each color read from the image memory 20 is binarized by a binarizing circuit 21 for each color.
It is converted to a binary color signal of 1 bit for each of R, G, and B by performing a value conversion process.

In the multi-valued color image signal 100, the block edge judging section 19 judges for each block whether or not the block is an edge portion. In this embodiment, it is determined whether an image is 8 × 8 as a block unit and whether it is an edge portion or a non-edge portion.

The signal binarized by the binarizing circuit 21 is masked by the mask signal 121 by the selector unit 28 for each block.

That is, the block judged to be an edge by the block edge judgment unit 19 is a block judgment signal 1
11, the binary signal 101 is selected. The mask signal 0 is assigned to a block determined to be a non-edge portion.
Is selected. Therefore, of the binarized images, only the edge images are stored in the binary image memory 22 through the 102 for each color.

The binary color signal read from the binary memory 22 is encoded by the encoder A for encoding a binary color signal, and the code word 105 is output. The encoding process by the encoder A is a first encoding process.

Next, the same color image signal as the one subjected to the above-described first encoding processing is read from the image memory 20.

This color signal is for encoding a portion other than the binary edge image encoded by the first encoding.

The binary edge image is input from the selector 102 to the level converter 29. Here, the binary signal is 0.
It is converted from 1 to 0.255 (8 bits).

The level-converted binary image 104 is subtracted from the multi-level color signal 112 by the differentiator 23, and becomes a differential multi-level R, G, B signal 107.

Next, the RGB signal is converted into a luminance / color difference signal 108 by the color conversion section 27. The following equation is generally used for this conversion.

Y = 0.299R + 0.587G + 0.114B Cr = 0.713 (RY) Cb = 0.564 (BY) However, R, G, B, Y, Cr and Cb shown here are This is a normalized value.

The color-converted differential multi-valued YCrCb signal 10
8 is coded after being stored in the difference multilevel memory 24.

In this embodiment, the differential multi-valued YCrCb signal is further hierarchically encoded. First, low-pass filter 2
8, the differential multi-valued YCrCb signal is smoothed and encoded by the encoder B26.

The low-pass filter 28 uses, for example, the filter coefficients shown in FIG. In actual filtering, each coefficient is standardized, that is, multiplied by 1/36.

The encoding process by the encoding B26 is the second encoding process, and generates the code word 106. In addition, the second codeword 106 is decoded by the encoder B26 and the decoder B30 which is an inverse transform for the hierarchical encoding process, and the difference multi-valued YCrC
It is decoded into a b signal 114.

Next, by inverse color conversion 36, the difference multi-valued RGB
The signal can be restored. This conversion may be performed by performing the inverse conversion of Expression 1 described above.

The inversely converted difference multi-valued RGB signal 120 is decoded by the inverse differencer 31 as a compressed image in which the difference multi-valued RGB signal 120 and the binary color signal 115 are combined. This image has a first codeword 105 and a second codeword 10
6 is restored to a hierarchical RGB image.

This RGB restored image 117 is again subjected to color conversion 3
3 is converted into a YCrCb restored image 118. This transformation is also Equation 1.

On the other hand, the original image signal 100 stored in the image memory 20 is also converted into a YCrC
The color conversion is performed on the b original image signal 116.

YCrCb original image signal 116 and YCrCb
The difference restored image signal 118 is subjected to a calculation for subtracting the difference restored image from the original image by the subtractor 35 to generate an original image difference image signal 119, and the encoder B32 performs a third encoding process. Create codeword 110.

Here, the encoder B32 and the encoder B26 perform the same encoding process. The third encoding process is the difference between the first and second encoding processes and the original image, and is the third hierarchical encoding.

In the present embodiment, the following judgment is used in the block edge judgment section 19. FIG. 3A shows an example.

For each block (in this embodiment, 8 × 8 pixels are taken as one block, but the unit of the block is not limited to this)
Edge detection is performed for each of RGB. As a method of detecting the edge, in FIG. 3A, the difference between the maximum value MaxL and the minimum value MinS in the block, P = LS, is obtained.
If P is equal to or greater than a certain value (T = 70, but the entire level is binary), an edge exists.

Further, it can also be realized by using a method as shown in FIG.

In FIG. 3B, DCT is performed every 8 × 8 block.
The conversion is performed, and the sum of the absolute values of the AC part of the converted coefficients excluding DC is obtained. If S is equal to or more than a certain value, it is determined that the edge portion.

In this method, the sum of the AC coefficients is a shaded portion. However, it is possible to make a determination by using only some of the coefficients.

FIG. 4 shows the relationship between the multivalued color image signal M read from the image memory 20, the binary edge image B, and the differential multivalued image S.

In this embodiment, the edge judgment is performed in units of 8 × 8 pixel blocks. FIG. 4 shows an example in which the 8 × 8 pixel blocks are viewed one-dimensionally. For the block determined to be an edge, the multi-valued color image signal M is binarized at the threshold TH and level-converted (0.255) to obtain a binary edge image B.

The multi-valued difference image S is obtained by taking the absolute value of the difference between M and B, that is, S = | M−B |.

In the present embodiment, the absolute value of the difference is used to avoid a negative difference. In FIG. 4C, a hatched portion is this portion. As a result, it can be divided into a binary edge image B containing a high-frequency component and a differential multi-value image of a low-frequency component.

The threshold value TH for binarization is TH>
128 (for 8 bits) is preferred. This is because if the value is small, the high frequency tends to remain in the multi-valued difference image.

The difference method of this embodiment is applied to the difference unit 23 shown in FIG. In addition, the inverse difference unit 31 in FIG. 1 can restore a multi-valued color image signal by performing a process reverse to the difference absolute value process, that is, calculating M = | S−B |.

FIG. 5 shows the configuration of an embodiment of a decoding unit to which the present invention is applied.

The code word 105 of the binary color image is
At 40, a binary image is restored to a dot image for each color.
3 is stored. This dot image completely corresponds to the binary signal stored in the binary memory 22 of FIG.

The decoded data is a binary image 1 of the first layer.
Form 50.

Next, the code word 106 of the second-level difference multi-valued color image is converted into a component signal YCrC by a decoder B41.
It is restored to the b signal.

The YCrCb signal is converted to an RGB difference signal by the inverse color converter 44 via 154. The RGB difference signal 155 and the 2nd of the first layer stored in the binary memory 43
The value image 150 is subtracted by the inverse differentiator 46 to form a multi-level restored image 151 of the second hierarchy.

Further, the code word 110 of the differential multi-valued color image of the third hierarchy is similarly decoded into a YCrCb signal by the decoder B42.

The difference signal 157 is obtained by converting the second hierarchical decoded image 151 into a component signal YCr
The signal converted to Cb is combined with the adder 48 to form a third-layer decoded image YCrCb. This YCr
The Cb signal is formed into an RGB signal by the inverse conversion unit 47, and a decoded image 152 of the third hierarchy is obtained.

In this embodiment, the following hierarchical coding can be realized. That is, in the first stage, a binary color image having a small amount of data but extracting the features (edges) of the image is coded and transmitted by complete restoration type erythropy coding, and the receiving side decodes and displays only the first stage. Thereby, the whole image of the received image having relatively high image quality can be grasped at an early stage.

Next, in the second stage, the multi-valued difference image between the original image and the binary color is converted into an image having only low-frequency components by smoothing processing or the like, so that D is efficient for encoding the low-frequency image.
Compression efficiency is increased using CT Huffman coding or the like.

Further, in the third stage, an image having a desired compression rate and image quality can be encoded by the DCT Huffman encoding or the like for the multi-valued difference image between the original image and the second stage image.

The differential multi-valued image of this embodiment can be encoded by various known block encodings. In this embodiment, 8 ×
DCT transform is performed for every eight pixel block, and a transform coefficient is Huffman-encoded.

FIG. 6B shows an example of an encoder for a multilevel differential image in this embodiment.

The image signals input to the encoders B26 and B32 in FIG. 1 are signals YCrC which are color-converted by the equation (1).
b. This signal is input to encoder B110 in FIG. 6B and input to orthogonal transform section 456.

The orthogonal transform circuit 456 converts the image into a transform coefficient (intensity) for each frequency for each 8 × 8 pixel block by discrete cosine transform. The transform coefficients shown in FIG. 7 are also 8 × 8 blocks, and the transform values are 1 to 6
Number 4 A coefficient number 1 indicated by 500 indicates a DC component. The coefficient numbers 2, 3... Shown by 501 and 502 indicate AC components, and as the numbers increase, they indicate AC components from a low frequency to a high frequency.

The transform coefficient signal 401 is converted to a linear quantizer 457.
Is quantized to, for example, 8 bits. The quantization steps of the linear quantizer 457 are determined so that the DC and low frequency quantization steps are fine and the high frequency quantization step is coarse.

The Huffman encoder 462 includes a DC component (coefficient number 1 in FIG. 7) and an AC component (coefficient numbers 2 to 6).
4) are separately encoded. In these encodings, a DC component and an AC component are Huffman encoded in the order of Y, Cr, and Cb, respectively.

For the DC component, a DPCM Huffman code in which a Huffman code is assigned to the difference from the DC component of the previous block is used.

As for the AC component, coefficient numbers 2 to 64 are scanned zigzag for each block as shown in FIG.
In this method, Huffman codes are assigned based on statistics of a line having a coefficient of 0 and the next coefficient value.

As described above, the differential multi-valued image is encoded to obtain the output 106.

The decoder B (41, 42 in FIG. 5) can be easily decoded by performing the inverse conversion of the encoder B in FIG. 6 (B). In other words, decoding can be performed by decoding the Huffman code of the DC component and the AC component, forming DCT coefficients for each 8 × 8 pixel block, and then performing inverse DCT transform.

FIG. 6A shows the details of the encoder A25 in FIG. In the present embodiment, the dynamic arithmetic code is executed. However, in the arithmetic code, the same processing is performed for both encoding and decoding, so that only the details of the encoding unit will be described.

The binary data of the image to be coded read out from the binary memory 22 of FIG. 1 is shown in FIG.
The operation enters the predicted state determination circuit 450 shown in FIG.

The prediction state determination circuit 450 outputs a prediction state signal S206 composed of the coded pixels around the target pixel. Also, the coded pixel data X217 synchronized with S116 is output, and both signals are input to the dynamic arithmetic coder 453 and coded.

FIG. 8 is a block diagram of the prediction state determination circuit 450, and FIG. 9 shows a pixel position for each color referred to for state prediction.

That is, FIG. 9A shows reference pixels of the first color of encoding (R in this embodiment), and refers to seven encoded pixels around the encoded pixel indicated by *. It represents that.

FIG. 9B shows reference pixels of the second color of encoding (G in this embodiment), and is a combination of seven pixels similar to FIG. 9A and pixels at the same position of the first color. Means that eight pixels are referred to.

FIG. 9C shows reference pixels of the third color (B in the present embodiment). The same seven pixels as in FIG. 9A and each of the same positions of the first and second colors are shown. 9 pixels together
This refers to referring to a pixel.

In the configuration of FIG. 8, the state of each color is determined by referring to a plurality of pixels at the reference pixel position for each color shown in FIGS. 9 (a) to 9 (c). Hereinafter, the operation of FIG. 8 will be described.

The signal 103, which is a 3-bit signal consisting of 1 bit for each of R, G, and B, is input to the latch groups 67 to 69 as RGB data 200 to 202, and is also input to the line memories 61, 62, and 63. The line memories 61 to 63 hold RGB data delayed by one line. Latches 67a to 67h and latches 68a to 6
8h and the latches 69a to 69h hold data delayed for each pixel clock.

In the latch group 67, the latches 67a, 67b, 67c, 67 to which the output of the line memory 61 is input
By referring to d and the output of the line memory 61, it is possible to refer to the data of five pixels on the previous line of the encoding line.
Also, the output of the latches 67g and 67h allows reference to two encoded pixels on the encoding line. The data of these seven pixels are combined to form a reference pixel signal 210 for determining the state of R, which is the first color to be encoded. Also, the latch 67
From f, the R data 211 of the coded pixel is output for determining the states of the other colors G and B.

Latch group 6 having the same configuration as latch group 67
8 and 69 are provided for the data G201 and B202. From the latch groups 68 and 69, the same seven-pixel data as the latch group 67 is output from the reference pixel signal 21.
2, 214.

The G data 213 of the encoded pixel is output from the latch 68f in the latch group 68 for determining the B state.

The selector 64 switches the reference pixel signal in accordance with a 2-bit color instruction signal 219 indicating a color corresponding to the output of each of the RGB color data. That is, when the color instruction signal 219 is R, the reference pixel signal 210 and the 2-bit zero signal are selected. In the case of G, the reference pixel signal 212, the R signal 212, and the zero signal 1 bit are selected. In the case of B, the reference pixel signal 214 and the R signal 2
11, the G signal 213 is selected.

The 9-bit selection signals 215 and 2 bits
Of the color instruction signal 219 by the packing circuit 65
The state signal S206 is collected into an 11-bit signal. Therefore, the state signal S ₁ indicates the color of the pixel to be coded and the surrounding state, and 2 ⁷ , 2 ⁸ , 2 for each of the R, G, B colors.
Shows ⁹ states.

The selector 64 outputs a pixel signal X217 to be coded in synchronization with the state signal S206 of the surrounding pixels.
Is output.

FIG. 10 is a block diagram of the dynamic encoder 453 of FIG.

Before explaining FIG. 10, the arithmetic codes used in this embodiment will be described.

As is conventionally known, the arithmetic code is
In this method, a code is formed by an arithmetic operation so that an input signal sequence becomes a code represented by a decimal binary number. This method is described in the publication "Compression of Black / Whi" by Langdon and Rissanen et al.
te Images With Arithmetic
Coding ", IEEE Tran Com. CO
M-29, 6, (1981.6).
According to this document, the input signal sequence already encoded is S, the probability of occurrence of a less-probable symbol (LPS) is q, and the operation register A
The following arithmetic operation is performed for each input signal when u.sub.end is A (S) and the sign register is C (S).

A (S1) = A (S) × q ≒ A (S) × 2− ^Q (1) A (S0) = <A (S) −A (S1)> _l (2) <> _l represents a truncation by ₁ significant bit C (S0) = C (S) (3) C (S1) = C (S) + A (S0) (4)

Here, the coded data is set to the dominant symbol (M
PS: A (S0) and C (S0) in case of 0) in the above example
Is used to encode the next data. In addition, the inferior symbol (LP
S: In the above example, in case of 1), A (S1), C (S1)
Is used to encode the next data.

The new value of A is multiplied by 2 ^s (S is an integer of 0 or more), and is set in a range of 0.5 < A <1.0.
This processing corresponds to shifting the operation register A S times in hardware. The same number of shifts are performed on the code register C, and the shifted-out signal becomes a code. The above processing is repeated to form a code.

Further, as shown in the equation (1), the multiplication calculation is replaced by a shift operation by approximating the appearance probability q of LPS by a power of 2 (2 ^-Q : Q is a positive integer). In order to further improve this approximation, q is approximated by a power-of-two polynomial, for example, as in equation (5).
This approximation improves the worst efficiency.

[0096] ^{q ≒ 2 -Q1 +2 -Q2 ... (} 5)

Further, since the arithmetic code can switch the value of Q for each encoded data, the probability estimating unit can be separated from the encoding.

In this embodiment, as described above, a dynamic method of estimating a probability while performing encoding is employed.

A description will be given of a block diagram of the encoder 453 shown in FIG.

The state signal S206 from the predicted state determination circuit 450 shown in FIG.
It is input to the encoding condition memory 74.

The encoding condition memory 74 stores the status signal S2
For each state represented by 06, a dominant symbol MPS 308, which is a symbol that is likely to appear, and an index 1307 indicating an encoding condition including an appearance probability of an LPS of an arithmetic code described later are stored.

The MPS 308 read out from the coding condition memory 74 according to the color and state of the image to be coded is input to the predictive conversion circuit 77, and the predictive conversion circuit 77 receives the serial number from the predictive state determination circuit 450 in FIG. Pixel signal X
A YN signal 301 that becomes 0 when 217 matches the MPS 308 is generated.

The YN signal 301 is input to the update circuit 75, and when the YN signal is 0, the count of the corresponding state among the count values stored in the counter memory 73 is incremented. Then, if the count value C306 stored in the counter memory 73 matches the set value MC305 from the count table ROM 72, the index I307 is updated in the direction of increasing (the direction of decreasing the appearance probability q of LPS) (MPS). Is not inverted.)

Incidentally, the count table ROM 72 stores the LP
The number MC305 of MPSs shown in Table 1 determined corresponding to the index I representing the appearance probability q of S is supplied to the updating circuit 75.

In the updating circuit 75, when the MPS 308 does not match the pixel signal X217, that is, when the YN signal from the predictive conversion circuit 77 is 1, the index I307 decreases (the appearance probability q of the LPS increases). Direction). When the index is 1, the value is 0
, The MPS is inverted (0 → 1 or 1 →
0) is performed. Output I'30 of update circuit 75
9. MPS ′ 310 is the value of the updated index, which is stored again in the encoding condition memory 74.

The coding parameter determination circuit 76 sets the coding parameter Q311 of the arithmetic code in the arithmetic coder 78 based on the value of the index I307. In the arithmetic encoder 78, the YN signal 3 from the prediction conversion circuit 77
01 is arithmetically coded using parameter Q311 and code 3
02 is obtained.

Incidentally, static encoding can be easily realized by giving initial values to the encoding condition memory 74 and not updating I and MPS.

FIG. 11 is a block diagram of the prediction conversion circuit 77. EX is the serial pixel signal X217 and MPS308.
The YN signal 301 is input to the OR circuit 79, and is 0 when the serial pixel signal X217 matches the MPS 308 according to the logical formula in Table 2, and becomes 1 when they do not match.

FIG. 12 is a block diagram of the updating circuit 75. When the YN signal 301 is 0, the count value C306 from the counter memory 73 is incremented by +1 in the adder 81 to become a signal C'312. This value is compared with the MC 305 from the count table ROM 72 by the comparator 83, and if the value of C 'matches the value of MC, the update signal U
PA313 is set to 1.

The YN signal 301 is the update signal UPB31
4 and UPA and UPB are index change circuits 85
to go into. UPA and UPB are logically ORed by an OR circuit 87.
R is taken, and the output signal 315 of the OR circuit 87 becomes a switching signal of the selector 82.

When the signal 315 is 1, the selector 82 resets the value of the counter memory 73 so that the 0 signal 319
Otherwise, the output signal C ′ 312 of the adder 81 is selected and output as the counter update signal C ″ 316, which is stored in the counter memory 73. Therefore, when the serial pixel signal X115 and the MPS 308 do not match, and When the coincidence state continues for a predetermined number of times, the counter memory 73
Is reset.

The index change circuit 85 receives a signal d 317 (normally d = 1) for controlling the index update interval, the UPA 313, the UPB 314, and the current index I 307 from the encoding condition memory 74.

Table 3 is a table showing an index updating method in the index changing circuit 85 (Table 3 shows a case where the update interval is d = 1 and d = 2).
The updated index I 'is determined by referring to this table with the current index I, the update interval condition d, UPA, and UPB.

When I = 1 and UPB = 1 (when the serial pixel signal X115 and the MPS 308 do not match), E
The X signal 318 is set. When the EX signal 318 is 1, the inverter 86 inverts the symbol of the current MPS 308 (0 → 1 or 1 → 0) to obtain an updated MPS′310.
When the EX signal is 0, MPS 'is not changed.

Updated I'309 and MPS'31
0 is stored in the encoding condition memory 74 and is used as the index I and MPS for the next processing. Table 3
The updating method described in (1) can be constituted by a table using a ROM or the like, or can be constituted by logic using an adder / subtractor.

As described above, when the number of MPSs equal to the number of MPSs determined according to the value of the index I representing the appearance probability q of the LPS approximated by a power-of-two polynomial has occurred, the index I is added by d. LP used for arithmetic code
The occurrence probability q of S is reduced, while when an LPS occurs, the index I is subtracted by d, and the occurrence probability q of the LPS used for the arithmetic code is increased. Further, when LPS occurs in a state in which the appearance probability q of LPS represents 0.5 (state in which index I is 1), M
Invert PS.

As described above, by updating the index I and the MPS adaptively to the input image, arithmetic coding with high coding efficiency can be achieved.

FIG. 13 is an encoding efficiency curve of the arithmetic code used in this embodiment. Hereinafter, the value of the index I is indicated by a small letter i. This curve is represented by equation (6), where the appearance probability of LPS is q, and the approximate probability _qei at the time of encoding is _qi . Then, the indexes I are sequentially assigned as 1, 2, 3,... From the larger value of the appearance probability q of the LPS to the smaller value.

[0119]

(Equation 1) Here, the numerator is entropy, and q _ei is a value represented by Expression (7).

Q _ei = q ₁ + q ₂ (7) The values of q ₁ and q ₂ are power-of-two polynomial approximations and are given in Table 4. For example, they are shown in (8) to (10).

Q _ei ′ = 2 ⁻¹ (8) q _e2 ′ = 2 ⁻¹ −2 ^-4 (9) q _e3 ′ = 2 ⁻² +2 ^-3 (10), and the efficiency η at this probability _Here , q _ei , which is the peak point at which is 1.0, is referred to as the effective probability. Also, it is clear that the efficiency is improved by coding the intersection point of the efficiency curve as the boundary probability q _bi and using the adjacent effective probability with this probability as a boundary.

In this embodiment, as shown in the equation (5), 2
Effective probability q shown in Table 4 from the probability that can be approximated by two terms
_ei is selected. Further, Q ₁ , Q ₂ , and Q _{3 in} Table 4 are parameters Q _c 311 to be sent to the arithmetic encoder 78. That is,
Q ₁ and Q ₂ are shift amounts given to the shift register, and the power of 2 is calculated by this shift operation. Q ₃ indicates the coefficient of the second term, and switches between + and-.

The values of MC in Table 1 are determined as follows.

That is, the number of LPS is N _L and the number of MPS is N _M
, The probability of LPS occurrence is given by equation (11).

[0125]

(Equation 2) Solving this equation with N _M gives equation (12).

N _M = “ _NL (1 / q−1)” (12) where “x” represents rounding up after the decimal point. Equation (1
By giving q _bi shown in FIG. 13 to q in 2), the number N _Mi of dominant symbols (MPS) there is calculated. Therefore, it is calculated from the MC wave equation (13).

MCi = N _{Mi + 1} −N _Mi (13)

The value of MC in Table 1 is obtained by the equations (11), (12),
This is calculated from (13) with N _L = 2.

As described above, the boundary probabilities q _{bi as} shown in FIG.
Symbol M corresponding to each index I based on
The number N _Mi of PSs is obtained, and the difference between the dominant symbols N _M between adjacent indexes is set as MC corresponding to each index I.

The value of MC and the number of generated superior symbols MPS are compared as described above. If the value of MC matches the number of superior symbols MPS, the state is determined by the code using the next index I. Judging that it is suitable for
Change the index I. As a result, the index I is changed at a favorable timing based on the number of occurrences of the dominant symbols MPS, and the optimal index I
Can be adaptively achieved.

FIG. 14 is a block diagram of the arithmetic encoder 78.

[0132] The Q ₁ to the shift register A90 of the code parameters determining circuit control signal as determined by the 76 Q311 (Table 4), Q ₂ in the shift register B91, Q ₃ is input to the selector 92. Q ₁ and Q ₂ are A _s 323 which are Augend signals for the shift registers A and B, respectively.
Indicates how many bits to shift to the right. The shifted result is output signals 330 and 331.

[0133] signal 331, complement is taken by inverter 96, the selector 92 selects the output signal of the signal 331 or the inverter 96 by the control signal Q _3, the output signal 3
Get 32. In the adder 93, the signal 322 from the shift register A90 and the signal 332 from the selector 92 are added, and an _AS1 signal 324 is output. The subtractor 94 subtracts the A _S1 signal 324 from the A _S signal 323 to _obtain A _S0
A signal 325 is obtained.

The selector 95 selects one of the A _S0 signal 325 and the A _S1 signal 324 based on the YN signal 301.
That is, when the YN signal is 1, the A _S0 signal becomes the A 'signal, and when the YN signal is 0, the A _S1 signal becomes the A' signal 326.

In shift circuit 89, the MSB of A 'signal is 1
The processing of shifting to the left is performed until the A _s ' signal 327 is obtained. The shift signal 332 corresponding to the number of shifts enters the code register 99, and the number of bits corresponding to the number of shifts are output from the code register 99 in order from the MSB, and the code data 330
become.

The code data 330 is processed by a bit processing method (not shown) so that the continuation of bit 1 is within a finite number and transmitted to the decoder side.

The contents CR32 of the code register 99 are
8 is an adder 97, which is added to the A _S0 signal 325 at 97 and enters the select 98. The signal CR 328 not added to the A _S0 signal 325 also enters the selector 98, and the YN signal 3
CR '= CR when 01 is 1, C when YN signal is 0
It is output as a CR 'signal 329 that _satisfies R' = CR + A _S0 . The shift processing described above for the code register 99 is also performed for the CR 'signal.

As described above, it is determined whether or not a multi-valued color signal is an edge portion for each block. The block which is an edge portion is binarized and then information-save-encoded by a dynamic arithmetic code. For a binary color at an edge portion of a line image or the like, a sharp image with little deterioration can be realized at a high compression ratio.

Further, with respect to multi-valued colors having few edges such as color photographs, the difference image obtained by subtracting the binary image of the edge portion from the original image, that is, the low-frequency image is hierarchically DCT-Huffman-coded to achieve a high compression ratio. Can be encoded.

Further, both the binary color image and the multi-valued color image have little deterioration in image quality and realize a high compression ratio, and at the same time, preserve the edges and the like which are the characteristics of the early transmission image in the hierarchical coding, so that the entire image can be saved. It is intended to realize early grasp of the situation.

[0141]

[Table 1]

[0142]

[Table 2]

[0143]

[Table 3]

[0144]

As described above, according to the image encoding apparatus of the present invention, the first generating means for generating a binary signal representing an edge image from an original image, and the binary encoding of the binary signal. First-stage encoding means, second generation means for generating a differential multi-value signal representing a difference between the original image and the edge image,
A smoothing means for performing a smoothing process on the difference multi-valued signal; a second-stage coding means for performing multi-level coding on the smoothed signal obtained by the smoothing process; And a third-stage encoding unit for generating an interpolation signal based on a difference between the image restored and the original image and a multi-level encoding of the interpolation signal. When encoding an original image into which an image is mixed, encoding can be performed at a compression rate as high as possible without deteriorating the image quality of the edge image. Further, according to the present invention, the edge image and another difference image (multi-valued difference signal)
When encoding separately, the difference image is likely to have an edge, and the difference image is subjected to a second-stage encoding by performing a smoothing process once,
Since another additional interpolation signal is coded and output, the coding efficiency in the second stage is very good, and the decoding side can quickly summarize the image composed of the coded data up to the second stage. You can know.

[Brief description of the drawings]

FIG. 1 is a block diagram of an encoding unit.

FIG. 2 is a diagram illustrating an example of a low-pass filter.

FIG. 3 is a diagram illustrating an example of determining a block edge;

FIG. 4 is a diagram illustrating an operation example of a differentiator.

FIG. 5 is a block diagram of a decoding unit.

FIG. 6 is a block diagram of an encoder.

FIG. 7 is a diagram showing conversion coefficients.

FIG. 8 is a block diagram of a state prediction determination circuit.

FIG. 9 is a block diagram illustrating reference pixel positions.

FIG. 10 is a block diagram of a dynamic encoder.

FIG. 11 is a block diagram of a prediction conversion circuit.

FIG. 12 is a block diagram of an update circuit.

FIG. 13 is a diagram showing an encoding efficiency curve.

FIG. 14 is a block diagram of an arithmetic encoder.

[Explanation of symbols]

 Reference Signs List 20 image memory 21 binarization circuit 25 encoder A 23 differencer 26 encoder B

Claims (4)

(57) [Claims] A first generation unit configured to generate a binary signal representing an edge image from an original image; a first stage encoding unit configured to binary-code the binary signal; Second generating means for generating a differential multi-valued signal representing the difference between: a smoothing means for performing a smoothing process on the differential multi-valued signal; and multi-level encoding of the smoothed signal obtained by the smoothing process A second stage encoding unit; a third generation unit that generates an interpolation signal based on a difference between the image restored based on the smoothed signal and the edge image and the original image; And a third-stage encoding unit. 2. The image encoding apparatus according to claim 1, wherein in the second-stage encoding, the smoothed signal is orthogonally transformed, and a transform coefficient is quantized and then encoded. 3. The image encoding apparatus according to claim 1, wherein in the third-stage encoding, the interpolation signal is orthogonally transformed, and after transform coefficients are quantized, encoding is performed. 4. The image encoding apparatus according to claim 1, wherein the first-stage encoding arithmetically encodes the binary signal.