JP2872334B2 - Color image encoding device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a color image encoding apparatus in a color facsimile apparatus or the like for communicating a color image.

[Conventional technology]

Conventionally, various proposals have been made regarding a color still image coding method. The symmetrical color still images are roughly classified into the following two.

(1) Red, green, blue, cyan, magenta, yellow, white and black 8
Binary color image that handles colors in binary (2) Multi-valued color image that displays 16.7 million colors of red, green, and blue with, for example, 256 gradations Each binary color image encoding method is currently used in facsimile machines and the like. A method has been considered in which a demodulated Huffman method, which is a variable-length coding method, is used for each color. As another method, a prediction coding method for predicting a coded pixel from surrounding pixels has been proposed. These methods fall into the category of lossless coding, and data storage in coding / decoding is performed.

On the other hand, as a multi-valued color image encoding method, RGB
A method has been proposed in which, after converting a t signal into a luminance / color difference signal, coefficient values subjected to orthogonal transform (discrete cosine transform) are linearly quantized, and the quantized values are subjected to variable-length coding. This method is basically a method in which the image data is reduced by cutting the high frequency side while leaving the low frequency side of the spatial frequency of the image. This method is an irreversible encoding method, and the compression ratio and the image quality degradation have a trade-off relationship.

[Problems to be solved by the invention]

However, in the case of encoding a color document image in which a color photograph is embedded in a color sentence according to the above conventional example.

(1) In the binary color method, even if a color text portion can be encoded with a higher compression ratio, it is not possible to efficiently encode an image with gradation in a color photographic portion.

(2) In the multi-valued color method, as the compression ratio is increased, the high-frequency components of the image are greatly cut, and the image quality of the edge portion of the character becomes more conspicuous. The rate cannot be expected.

There are problems such as.

[Means for solving the problem]

SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and it is an object of the present invention to satisfactorily encode not only a multi-valued color image and a binary color image but also a color image in which a multi-valued color image and a binary color image are mixed. A binarizing unit for binarizing a multi-level color signal, and removing a line signal (or an edge component) from the multi-level color signal based on the binary color signal from the binarizing unit. Removing means;
It is an object of the present invention to provide a color image coding apparatus having coding means for coding a value color signal and a multivalued color signal from which a line signal (or an edge component) has been removed by the removal means. Still further, the removing means provides a color image coding apparatus comprising a difference means for taking a difference between a binary color signal and a multi-valued color signal, and the removing means comprises a binary color signal. A color image encoding apparatus comprising a mask means for masking a multi-valued color signal by a signal, and a conversion means for converting an output of the binarization means into a specific value. The present invention provides a color image coding apparatus, wherein the coding means is a common coding means for sequentially coding a binary color signal and a multi-valued color signal. It is an object of the present invention to provide a color image encoding apparatus that encodes and transmits a multi-level color signal after encoding and transmitting a binary color signal.

〔Example〕

 Hereinafter, the present invention will be described using preferred embodiments.

FIG. 1 shows an embodiment of a coding unit to which the present invention is applied.

The image memory 20 stores 8-bit multi-valued color image signals of red (R), green (G), and blue (B) representing a full-color image input from a color still image input unit such as a color scanner (not shown). I have.

The image signal 100 of each color read from the image memory 20 is
The binarization circuit 21 performs a binarization process for each color, and outputs R, G,
B is converted into a 1-bit binary color signal, and then stored in the binary memory 22 for each color. The binary color signal 103 read from the binary memory 22 is encoded by the encoder A for encoding a binary color signal, and a code word 105 is output. The encoding process by the encoder A is a first encoding process.

Next, the same color image signal as that subjected to the above-described first encoding process is read from the image memory 20. In the subtractor 23,
An R, G, B 8-bit signal 100 from the image memory 20 and a signal (0 → 0, 1 → 255) 102 obtained by level-converting the output from the binary memory 22 into an 8-bit signal are input. Subtraction processing is performed for each color. The difference signal 104 is stored in the difference memory 24 for each color. Multi-valued color signal of difference memory 24
Reference numeral 110 denotes an encoding process performed by an encoder B for encoding a multi-level color signal, and outputs a codeword 106. The above-described encoding processing by the encoder B is the second encoding processing.

As shown in Table 5, the mode setting section 29 outputs a control signal 107 corresponding to the code mode to the mask signal generator 28 and the encoder 27, and controls them as follows.

(1) In the binary mode, the target of the binarization processing by the binarization circuit 21 is set to the entire area, and the encoding processing executes only the first encoding processing by the encoder A25.

(2) In the multi-value mode, the mask generator 28 generates a mask signal for the entire area so that the binarization processing by the binarization circuit 21 is not performed, and the contents of the binary memory 22 are all zero. So that The encoding process is performed by the second encoder B.
Only the encoding process of

(3) In the region designation mode, the binarization process by the binary circuit 21 is performed on the region of the region multivalued color image designated by the region designation signal 108 from the region designation unit 19 for designating the multivalued color region. The mask generator 28 outputs a mask signal 109 so as to perform the masking. FIG. 15 is a diagram showing a mask area in the area designation mode, and shows that the area A2001 and the area B2002 in the entire image area 2000 are masked by the binarization processing.

The area specifying unit 19 may automatically determine the multi-valued color image area by the monitor of the color image and output the area specifying signal 108, or output the signal 108 according to the manual area specification using a keyboard, a digitizer, or the like. May be.

In the encoding process in the area designation mode, a first encoding process for encoding and transmitting the contents of the binary memory 22 is performed using the encoder A25 as a first stage, and an encoder B26 is executed as a second stage. A second encoding process for encoding and transmitting the contents of the difference memory.

(4) In the automatic mode, the entire area is binarized by the binarization circuit 21, the binarization result is stored in the binary memory 22, the first encoding process is performed by the encoder A25, and the binary encoding is performed. Encodes and transmits color still images. Next, a second encoding process is performed using an encoder B26 on the difference image 110 obtained by subtracting the original image from the image obtained by level-converting the binary image obtained by the subtractor 23, and is encoded and transmitted. .

FIG. 16 shows the line data 203 read from the image memory.
Is binarized by the threshold value Th206 in the binarization circuit 21, and further, the level-converted signal 204 and the signal
A difference signal 205 obtained by subtracting 203 is shown. In this manner, the line signal (or edge signal) in the multi-valued color image is removed by the subtractor 23. In this manner, multi-valued data from which edge components have been removed is formed, and the multi-valued data is encoded. Therefore, bleeding, blurring, and the like of an edge portion caused by performing multi-value color coding on edge components are removed. Thus, good encoding can be achieved.

Further, by transmitting a binary color image with a small amount of data in the first stage, the receiving side can decode and display only the first stage, so that the received image can be confirmed at an early stage.

 FIG. 2 is a block diagram of the binarizing circuit 21.

The comparator 40 compares the threshold value Th206 with the original image signal D100. If D ≧ Th, the signal 113 is set to 1;
To 0. When the mask signal is true by the gate circuit 41, the signal 101 is forcibly set to 0, and in other cases, the input signal 113 is passed.

In the present embodiment, the binarization is simply performed by the comparator, but the binarization processing is not limited to this.

As described above, the signal 101 can be forcibly set to the specific value, that is, 0 by the gate circuit 42. Therefore, when the second encoding process for the multi-valued color image is required over the entire screen, The gate circuit 41 may set the signal 101 to 0 over the entire screen. Further, when the second encoding process for the multi-valued color image is required for the screen and the desired portion, the signal 101 is output by the gate circuit 41 in accordance with the desired portion.
May be set to 0.

In this way, according to the coding mode specification and area specification,
By controlling the operation of the gate circuit 41, it is possible to arbitrarily execute an encoding process suitable for an image to be encoded.

FIG. 3 is a configuration diagram showing a decoding unit applied to the present embodiment.

The code word 105 of the binary color image is restored to a dot image for each color by the decoder A30 and stored in the binary memory 33. This dot image corresponds to the binary signal stored in the binary memory 22 shown in FIG. Further, the codeword 106 of the multivalued color image is restored to multivalued image data for each color by the decoder B31, and is stored in the difference memory 34. The data stored in the difference memory 34 corresponds to the difference signal stored in the difference memory 24 in FIG.

In the synthesizer 35, the RGB 1-bit signals 113 from the binary memory 33 are output.
And the difference signal 11 from the difference memory 34.
4 are synthesized to obtain a signal 115, which is stored in the image memory D36.
The image synthesis in the synthesizer 35 is performed in the reverse process of the subtractor 23 shown in FIG. 1, that is, a method of subtracting the signal 205 from the signal 204 in FIG. 16 to obtain the original signal 203.

 FIG. 4 is a block diagram of the encoder 27 shown in FIG.

The binary color encoder A25 includes a prediction state circuit A50 and a delay circuit
The input and output are switched by selectors 52 and 54 which are constituted by A51 and a dynamic encoder 53 and operated by a control signal 107. Also, the multi-valued color encoder B26
Are a color conversion circuit 55, an orthogonal conversion circuit 56, a linear quantizer 57, and first to sixty-fourth page memories 58-1 to 58-64, a selector 59, a prediction state determination circuit B60, a delay circuit B61, and a dynamic code. The input and output are switched by selectors 52 and 54 operated by a control signal 107 similarly to the encoder A25.

Here, the dynamic encoder 53, which is the central part of the encoder 27, is configured to be shared by the encoders A and B, and the hardware configuration can be simplified in this part. Hereinafter, the processes of the encoder A and the encoder B will be described in order.

 First, the encoder A will be described.

The output 103 from the binary memory 22 enters the prediction state circuit A50. Predicted state circuit A50 with respect the pixel of interest, and outputs the composed prediction state signal S ₁ 114 from its surroundings code Kasumi pixel. Also, 1 synchronized with the prediction state signals S ₁ in the delay circuit A51
The pixel signal X ₁ 115 of bit is output, and both signals S ₁ 114 and X ₁ 115 are input to the selector 52.

FIG. 5 is a block diagram of the predicted state determination circuit A50.
FIG. 6 shows a pixel position for each color referred to for state prediction.

That is, FIG. 6 (a) shows the reference pixel of the first color of encoding (R in this embodiment), and refers to the encoded seven pixels surrounding the encoded pixel indicated by *. It represents.

FIG. 6 (b) shows reference pixels of the second color (G in this embodiment) of encoding, and 7 pixels similar to (a) and 8 pixels at the same position of the first color are combined. This refers to referring to a pixel.

FIG. 6C shows reference pixels of the third color (B in the present embodiment), which are the same as those of FIG.
This indicates that a total of nine pixels of the pixels at the same position of the color and the second color are referred to.

In the configuration shown in FIG. 5, by referring to a plurality of pixels at the reference pixel position for each color shown in FIGS. 6 (a) to 6 (c),
The state of each color is determined. Hereinafter, the operation of FIG. 5 will be described.

The signal 103, which is a 3-bit signal composed of 1 bit for each of R, G, and B, is an RGB signal.
The data 200 to 202 are input to the latch groups 67 to 69 and also to the line memories 61, 62, and 63, and the line memories 61 to 63 hold RGB data delayed by one line. The latches 67a to 67h, the latches 68a to 68h, and the latches 69a to 69h hold data delayed for each pixel clock.

With the latches 67a, 67b, 67c, 67d to which the output of the line memory 61 is input and the output of the line memory 61 in the latch group 67, it is possible to refer to the data of five pixels on the previous line of the coding line. In addition, the output of the latches 67g and 67h allows reference to two encoded pixels on the encoding line. The data of these seven pixels is combined to form a reference pixel signal 210 for determining the state of R, which is the first color to be encoded. Further, from the latch 67f, the R data 211 of the coded pixel is changed to the other color G,
Output to determine the state of B.

Latch groups 68 and 69 having the same configuration as this latch group 67 are data G
Provided for 201 and B202.
Data of 7 pixels similar to those of the latch group 67 are output as reference pixel signals 212 and 214 from 8,69, respectively.

Also, the G of the encoded pixel is obtained from the latch 68f in the latch group 68.
Is output for determining the state of B.

The selector 64 switches the reference pixel signal in accordance with a 2-bit color instruction signal 219 indicating a color corresponding to the output of each color data of RGB. That is, when the color instruction signal 219 is at R, the reference pixel signal 210 and the zero signal 2 bits are selected.
In the case of G, the reference pixel signal 212, the R signal 212 and the zero signal 1 bit are selected. In the case of B, the reference pixel signal 214
And the R signal 211 and the G signal 213 are selected. The 9-bit selection signal 215 and the 2-bit color instruction signal 219 are combined into an 11-bit signal by the packing circuit 65, and the state signal S ₁ 206
become. Therefore, the state signals S ₁ indicates the state of the color and the surrounding pixels to be coded, shown R, R, B 2 ^7, 2 _8, 2 ⁹ states for each color.

 Next, the encoder B shown in FIG. 4 will be described.

The image signal 110 read from the difference memory 24 shown in FIG.
Is the luminance / color difference signal 400 from the RGB signal in the color converter 55.
Is converted to The following equation is generally used for this conversion.

Y = 0.299R + 0.587G + 0.114B Cr = 0.713 (RY) Cb = 0.564 (BY) where R, G, B, Y, Cr, and Cb are standardized values.

Next, the orthogonal transform circuit 56 performs the discrete cosine transform to
The pixels in each × 8 pixel block are converted into a conversion coefficient (intensity) for each surrounding number. The conversion coefficient shown in FIG.
It is a block of × 8, and assigns a number from 1 to 64 to the converted value. A coefficient number 1 indicated by 500 indicates a DC component. The coefficient numbers 2, 3,... Shown by 501, 502 indicate AC components. As the numbers increase, they indicate AC components from a low frequency to a high frequency.

The transform coefficient signal 401 is quantized by the linear quantizer 57 to, for example, 8 bits. In the linear quantizer 57, quantization steps are determined so that DC and low frequency quantization steps are fine, and high frequency quantization steps are coarse. The 64 quantized values constituting the above-described 8 × 8 block are stored in 64 first to 64th page memories 58-1 to 58-64, respectively. That is, 8 is stored in the first page memory 58-1.
The quantized value of the DC component corresponding to the coefficient number 1 of the × 8 block is stored in the 64th page memory 58-64.
The quantized value of the AC component of the maximum high frequency corresponding to the coefficient number 64 of the block is stored. Therefore, each page memory 58
-1 to 58-64 include a plurality of 8
The quantized value at the same position of the × 8 block is stored.

The data of the first to 64th page memories 58-1 to 58-64 are
The signal passes through the selector 59 and is input to the prediction state determination circuit B60 and the delay circuit B61. This data transmission method is as follows: after transmitting all the contents of the first page memory 58-1, the second page memory 58-1
-2 data is transmitted for each page memory, and this is performed in order, and finally the 64th page memory 58-64
Is sent out. This is performed by controlling switching of the selector 59 by a switching signal 406 output from a central controller (not shown).

FIG. 13 is a block diagram of the prediction state determination circuit B60. Basically, the method is the same as the reference method shown in FIG. Coding starts from the most significant bit plane,
The n-th bit plane is the already encoded first to n-1th bits
Reference the pixel of the plane. Further, the n-th bit plane refers to the already encoded 7 bits around.

FIG. 14 shows a pixel position for each bit referred to for state prediction.

That is, FIG. 14A shows the first bit D ₁ (MSB) of the encoding.
Indicates that reference is made to seven coded pixels around the coded pixel indicated by *.

Further, FIG. 14 (b) shows the reference pixels of the encoded second bit second D _2, referring to the 8 pixels together the positions of the pixels of the same seven pixels and one bit (a) and Is represented.

Further, FIG. 14 (c) shows the reference pixels of the third bit th D _3, 9 pixels together for each pixel in the same position in the same seven pixels and the first bit and second bit and (a) Is referred to.

FIG. 14 (d) shows a reference pixel at the eighth bit D ₈ (LSB), and includes the same seven pixels as in FIG.
This indicates that a total of 14 pixels are referred to for each pixel at the same position in the seventh bit.

In the configuration shown in FIG. 13, the state of each bit plane is determined by referring to a plurality of pixels at the reference pixel position for each bit shown in FIGS. 14 (a) to (d). Below, the thirteenth
The operation of the figure will be described. In FIG. 13, circuits for the fourth to sixth bits are omitted in order to prevent the drawing from being complicated.

The signal 110, which is an 8-bit signal, is input to the latch groups 521 to 528 as bit plane data 501 to 508, and is also input to the line memories 511 to 518. The plane data is held. Also, the ratchet groups 521 to 528 have the fifth
Similarly to the illustrated latch groups 67 to 69, data delayed for each pixel clock is held.

In the group of latches 52, the four latches to which the output of the line memory 511 is input and the output of the line memory 511 make it possible to refer to the data of five pixels on the line preceding the coding line. In addition, the output of the two subsequent latches of the four latches to which the data 501 is directly input allows the user to refer to the encoded lines on the encoding line. The combined data of 7 pixels and the reference pixel signal 551 for state determination data D ₁ is a first bit th coding. The data 561 of D ₁ of the encoding pixel is output for the state determination of the other bits plane from latch group 521.

Latch groups 522, 523 to 52 having the same configuration as this latch group 521
₇ and 528 are provided for the data D ₂ , D _{3 to} D ₇ and D _{8. From} these latch groups 522 to 528, data of seven pixels similar to the latch group 521 are respectively referred to as reference pixel signals 561, 562, 563 to 55.
Output as 7,558.

The data 562 of D ₂ encoded pixel is output for the state determination of the bit planes of the three bits to eighth bits counted from the latch group 522.

The selector 530 switches the reference pixel signal according to a 3-bit bit instruction signal 570 indicating a bit corresponding to the output of data for each bit plane. That is, when the bit indication signal 570 is in the first bit D _1, the reference pixel signal 551
And 7-bit zero signal are selected. Further, the zero signal 6bit reference pixel signals 552 and D ₁ signal 561 when the second bit D ₂ is selected. Also, the reference pixel signal 558 and D when the eighth bit D _8
1 signal 561, D ₂ signal 562, D ₃ signal 563～D ₇ signal 567 is selected. This 14-bit selection signal 215 and 3-bit color indication signal
Reference numeral 219 is collected into a 17-bit signal by a packing circuit 540 to become a state signal S ₂ 404. Accordingly, the state signal S ₂ indicates the state of the bit planes and the surrounding pixels to be coded.

This output signal S ₂ 404 is input to the selector 52 shown in FIG. The delay circuit B61 is to a reference signal S ₂ and the VFO output signal X ₂ 405.

The above signals S ₁ , X ₁ and S ₂ , X ₂ are selected as signals S 116, X 117 by the selector 52 operating according to the control signal 107 output from the central controller (not shown). This signal is encoded by the dynamic encoder 53, and the signal 11
8 is switched by the selector 54 operating according to the control signal 107 and output as the code word 106.

FIG. 7 is a block diagram of the dynamic encoder 53 shown in FIG.

Before explaining FIG. 7, the arithmetic codes used in this embodiment will be described.

As conventionally known, the arithmetic code is a method in which a code is formed by an arithmetic operation so that an input signal sequence becomes a code represented by a decimal number. This method is Langdo
n and Rissanen et al., “Compression of Black /
White Images With Arithmetic Coding "IEEE Tran Com.
COM-29, 6, (1981.6). According to this document, the input signal sequence already encoded is S, the probability of occurrence of a less-probable symbol (LPS) is q, and the arithmetic register Augend is A.
(S) When the code register C (S) is used, the following arithmetic operation is performed for each input signal.

A (S1) = A (S) × q ≒ A (S) × 2− ^Q (1) A (S0) = <A (S) −A (S1)> _l (2) <> _l is valid C (S0) = C (S)... (3) C (S1) = C (S) + A (S0)... (4) where the encoded data is a dominant symbol (MPS: In the case of 0) in the example, A (S0) and C (S0) are used for encoding the next data. Further, in the case of a less-probable symbol (LPS: 1 in the above example), A (S1) and C (S1) are used for encoding the next data.

The new value of A is multiplied by 2 ^S (S is an integer greater than or equal to 0), and 0.5
A is within the range of 1.0. This processing corresponds to shifting the operation register A S times in hardware. The same number of shifts are performed on the code register C, and the shifted-out signal becomes a code. The above processing is repeated to form a code.

Also, by approximating the appearance probability q of LPS by a power of 2 (2 ^−Q : Q is a positive integer) as shown in the equation (1),
Multiplication calculation is replaced by shift operation. In order to further improve this approximation, q is approximated by a power-of-two polynomial, for example, as in equation (5). This approximation improves the worst efficiency.

q ≒ 2− ^Q1 + 2− ^Q2 (5) Further, since the arithmetic code can switch the value of Q for each encoded data, the probability estimating unit can be separated from the encoding.

In the present embodiment, a dynamic method of estimating a probability while performing encoding as described above is employed.

The block diagram of the encoder 53 of FIG. 7 for performing the above arithmetic coding will be described.

The state signal S116 from the selector 52 shown in FIG. 4 is input to the counter memory 73 and the encoding condition memory 74.

The encoding condition memory 74 stores, for each state represented by the state signal S116,
An MPS 308 and an index 1307 indicating an encoding condition including an appearance probability of an LPS of an arithmetic code described later are stored. The MPS 308 read from the encoding condition memory 74 according to the color and state of the image to be encoded is input to the prediction changing circuit 77, and the prediction conversion circuit 77 converts the serial pixel signal X117 from the selector 52 shown in FIG. YN that becomes 0 when matched
Make signal 301. The YN signal 301 is input to the update circuit 75, and when the YN signal is 0, the count of the corresponding state among the count values stored in the counter memory 73 is incremented. Then, the count value C306 stored in the counter memory 73 is stored in the count table ROM7.
If it matches the set value MC305 from 2, the index I3
Update is performed in a direction in which 07 increases (in a direction in which the appearance probability q of LPS decreases). (The inversion of the MPS is not performed.) The count table ROM 72 supplies the update circuit 75 with the number MC305 of the MPS shown in Table 1 which is determined in correspondence with the index I indicating the appearance probability q of the LPS. .

In the updating circuit 75, when the MPS 308 does not match the pixel signal X117, that is, when the YN signal from the prediction changing circuit 77 is 1, the index I307 decreases (the LPS appearance probability q increases). Update. When a YN signal with a value of 0 comes when the index is 1, the MPS is inverted (0 →
1 or 1 → 0). The outputs I'309 and MPS'310 of the updating circuit 75 are the updated index values and are stored again in the coding condition memory 74.

In the coding parameter determination circuit 76, the index I307
The arithmetic parameter Q311 of the arithmetic code is set in the arithmetic coder 78 based on the value of. The arithmetic encoder 78 arithmetically encodes the YN signal 301 from the prediction change circuit 77 using the parameter Q311 to obtain a code 302.

Note that an initial value is given to the encoding condition memory 74, and I, MP
By not updating S, static encoding can be easily realized.

FIG. 8 is a block diagram of the prediction changing circuit 77. The serial pixel signal X117 and the MPS 308 are input to the EX-OR circuit 79, and the YN signal 301 becomes 0 when the serial pixel signal X115 and the MPS 308 match according to the logical formula in Table 2, and becomes 1 when they do not match.
Is output.

FIG. 9 is a block diagram of the updating circuit 75. YN signal 30
When 1 is 0, the count value C306 from the counter memory 73 is incremented by +1 in the adder 81 to become a signal C'312. This value is calculated by the comparator 83 as M from the count table ROM72.
Compared to C305, if the value of C 'matches the value of MC,
The update signal UPA313 is set to 1. The YN signal 301 becomes the update signal UPB314, and UPA and UPB are index change circuits.
Enter 85. In addition, a logical OR of UPA and UPB is obtained by an OR circuit 87, and an output signal 315 of the OR circuit 87 becomes a switching signal of the selector 82. When the signal 315 is 1, the selector 82 selects the 0 signal 319 to reset the value of the counter memory 73, and otherwise selects the output signal C'312 of the adder 81 and outputs it as the counter update signal C "316. This is the counter memory 7
Store it in 3. Therefore, the serial pixel signal X115 and MPS30
When 8 does not match, and when the matching state continues a predetermined number of times, the count value of the counter memory 73 is reset.

The index change circuit 85 includes a signal d317 (typically d = 1) for controlling the index update interval and the UPA31.
3. The current index I307 is input from the UPB 314 and the encoding condition memory 74.

Table 3 is a table showing an index updating method in the index changing circuit 85 (Table 3 shows a case where the update interval is d = 1 and d = 2). This table is updated with the current index I and the update. Step condition d, UPA, U
The updated index I 'is determined by referring to the PB. Also, I = 1 and UPB = 1 (serial pixel signal X11
In the case of (5 and MPS 308 do not match), the EX signal 318 is set. When the EX signal 318 is 1, the inverter 86 inverts the symbol of the current MP 308 (0 → 1 or 1 → 0) and updates the MPS ′ 310
Get. When the EX signal is 0, MPS 'is not changed. The updated I'309 and MPS'310 are stored in the encoding condition memory 74, and the index I and MP for the next processing are stored.
Used as S. The update method shown in Table 3 is based on ROM
For example, it can be configured as a table, or can be configured as logic using an adder / subtractor.

As described above, when MPSs equal to the number of MIPs determined according to the value of the index I representing the appearance probability q of the LPS approximated by a power-of-two polynomial are generated, the index I
Is added, and the appearance probability q of the LPS used for the arithmetic code is decreased. On the other hand, when the LPS occurs, the index I is subtracted by d and the appearance probability q of the LPS used for the arithmetic code is reduced.
To make it bigger. Further, in a state where the appearance probability q of the LPS represents 0.5 (a state where the index I is 1), the LPS
When MPS occurs, the MPS is inverted.

In this way, the index I and MP are adaptively applied to the input image.
By updating S, arithmetic coding with good coding efficiency can be achieved.

FIG. 10 is an encoding efficiency curve of the arithmetic code used in this embodiment. Hereinafter, the value of the index I is indicated by a small letter i.
This curve shows the appearance probability of LPS as q and the approximate probability at the time of encoding _qei
Is given by equation (6). Then, the indexes I are sequentially assigned as 1, 2, 3,... From the larger value of the appearance probability q of the LPS to the smaller value.

Here, the numerator is entropy, and q _ei is a value represented by Expression (7).

q _ei = q ₁ + q ₂ (7) The values of q ₁ and q ₂ are power-of-two polynomial approximations and are given in Table 4. For example, they are shown in (8) to (10).

q _e1 '= 2 ^-1 ... (8) q _e2 ' = 2 ^-1 -2 ^-4 ... (9) q _e3 '= 2 ^-2 +2 ^-3 ... (10) The peak point q _ei is hereinafter referred to as an effective probability. In addition, it is clear that the efficiency is improved when the intersection of the efficiency curves is called a boundary probability q _bi and coding is performed using the adjacent effective probability with this probability as a boundary.

In the present embodiment, the effective probability shown in Table 4 is selected as q _ei from the probabilities that can be approximated by two terms as shown in Expression (5). Q ₁ , Q ₂ , Q _{3 in} Table 4 are parameters Q _c 311 to be sent to the arithmetic encoder 78. That is, Q ₁ and Q ₂ are shift amounts given to the shift register.
Power calculation. Q ₃ indicates the coefficient of the second term, and switches between + and-.

 The value of MC in Table 1 is determined as follows.

That is, when the number of LPS N _L, the number of MPS was N _M, the probability of LPS is given by equation (11).

Solving this equation with N _M gives equation (12).

Represents rounding up after the decimal point. Q in equation (12)
Is given the q _bi shown in FIG. 10, and the number N _Mi of dominant symbols (MPS) there is calculated. Therefore,
Calculated from MC wave equation (13).

MCi = N _Mi + 1−N _M1 (13) The value of MC in Table 1 is obtained from the formulas (11), (12), and (13) using N _L =
It is calculated as 2.

Thus, the number N _Mi of symbol MPS was based on each boundary probability q _bi of as the tenth shown corresponding to each Indetsukusu I
The calculated, the difference between the dominant symbol N _M between adjacent Indetsukusu and MC for each Indetsukusu I.

The value of MC is compared with the number of dominant symbols MPS to be generated as described above. If the value of MC matches the number of dominant symbols MPS, the state is suitable for encoding using the adjacent index I. Then, the index I is changed. As a result, the index I is changed at a good timing based on the number of occurrences of the dominant symbol MPS, and the encoding using the optimal index I can be adaptively achieved.

 FIG. 11 is a block diagram of the arithmetic encoder 78.

Code parameter decision circuit control signal determined by 76 Q311 the Q ₁ to the shift register A90 of the (Table 4),
Q ₂ is input to the shift register B 91 and Q ₃ is input to the selector 92. Q ₁ and Q ₂ are Augend for shift registers A and B, respectively.
It indicates whether to shift the A _s 323 is a signal to what bit right.
The shifted results are output signals 330 and 331.

The signal 331 is complemented by the inverter 96 and
2 selects the output signal of the signal 331 or the inverter 96 by the control signal Q _3, to obtain an output signal 332. In the adder 93, the signal 330 from the shift register A90 and the signal from the selector 92
332 is added, and an _AS1 signal 324 is output. Subtractor 9
In 4 subtracts the A _S1 signal 324 from the A _S signal 323, A _S0 signal 325
Get. One of the selector 95 A _S0 signal 325 and A _S1 signal 324 selected by the YN signal 301. That is, A _S0 signal when the YN signal is 1, also the A _S1 signal when the YN signal is 0. A '
The signal becomes 326. The shift circuit 89 performs a process of shifting to the left until the MSB of the A 'signal becomes 1, and an As' signal 327 resulting from this shift is obtained. The shift signal 332 corresponding to the number of shifts enters the code register 99, and the number of bits corresponding to the number of shifts is output from the code register 99 in order from the MSB to become code data 330.

The code data 330 is converted to bit 1 by a bit processing method (not shown).
Are processed so as to be within a finite number, and are transmitted to the decoder 14 side.

The contents CR328 code register 99 by the adder 97 A _S0
The signal 325 is added to the signal 325, and the selector 98 is added. Also, the A _S0 signal
The 325 unadded signal CR328 also enters the selector 98,
CR '= CR when YN signal 301 is 1, CR' when YN signal is 0
= Is output as CR 'signal 329 which is a CR + A _SO. The shift processing described above for the code register 99 is also performed for the CR 'signal.

[Other embodiments]

In the embodiment described above, a binary color image obtained by binarizing the original color image and a multi-valued color image obtained by taking the difference between the binary color image and the original color image are obtained. The multi-valued color image is encoded and transmitted. That is, by converting the difference between the binary color image and the original color image into a multi-valued color image, by encoding and transmitting a multi-valued color image that does not include edge information,
This has enabled good code transmission and decoding of multi-valued color images.

The formation of multi-valued color information that does not include edge information
In addition to the method of obtaining the difference, there is a method of masking the original color information with the binary color information.

FIG. 17 shows an embodiment of an encoding unit to which this masking method is applied. The blocks having the same functions as those of the encoder shown in FIG.

The image memory 20 stores red (R), green (G), and blue (B) 8-bit color image signals representing a full-color image input from a color still image input unit (not shown).

The image signal 100 of each color read from the image memory 20 is
The binarization circuit 21 performs a binarization process for each color, and outputs R, G,
B binary memory after converted to 1-bit binary color signal
22 is stored for each color. The binary color signal 103 read from the binary memory 22 is subjected to encoding processing by an encoder A25 for encoding a binary color signal, and a code word 105 is output.

Next, the same color image signal as described above is read from the image memory 20 again. And R, G, B8bi from the image memory 20.
The t signal 100 and the output of 22 from the binary memory are input to the determination unit 600. The determination unit 600 performs a process of masking a signal from the image memory 20 over a period when the output of the binary memory 22 is at one level. The output signal 601 of the judgment unit 600 is stored in a difference
Store in 24. The multi-level color signal 110 in the difference memory 24 is coded by the multi-level color coding encoder B26 in the same manner as described above, and the code word 106 is output.

FIG. 18 shows the line data 703 read from the image memory 20.
Is converted into a binary value by using a threshold Th702, and a converted signal 705 obtained by masking the signal 703 with the signal 704 and the signal 704 whose level has been converted is shown. As a result, a line signal (or edge signal) which is a high-frequency component in the multi-valued color image is removed. Therefore, since the multi-valued color image includes the edge component, the encoding process does not cause blurring or blurring.

[Effects of the Invention] As described above, according to the present invention, by encoding a binary color signal obtained by binarizing a multi-valued color signal and a multi-valued color signal from which edge components have been removed, characters, For a binary color image including edge information such as lines, it is possible to perform encoding at a high compression ratio with little deterioration, and for a multi-valued color image such as a color photograph, there is no deterioration due to an edge portion. Encoding with a high compression ratio becomes possible.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration example of a coding unit to which the present invention is applied, FIG. 2 is a block diagram of a binarization circuit, FIG. 3 is a diagram showing a configuration example of a decoding unit, and FIG. FIG. 5 is a block diagram of a prediction state determination circuit A, FIG. 6 is a diagram showing reference pixel positions, FIG. 7 is a block diagram of a dynamic encoder, FIG. 8 is a block diagram of a prediction conversion circuit, FIG. 9 is a block diagram of the updating circuit, FIG. 10 is a diagram showing a coding efficiency curve, FIG. 11 is a block diagram of an arithmetic encoder, FIG. 12 is a diagram showing transform coefficients, and FIG. FIG. 14 is a block diagram of a circuit B, FIG. 14 is a diagram showing a reference pixel position, FIG. 15 is a diagram showing an example of area designation, FIG. 16 is a diagram showing an operation example of a subtractor, and FIG. FIG. 18 is a diagram showing another configuration example, and FIG. 18 is a diagram showing an operation example of the determiner. 20 is an image memory, 21 is a binarizer, 22 is a binary memory, 23 is a subtractor, 24 is a difference memory, 25 is an encoder A, 26 is an encoder B
It is.

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H04N 1/40-1/419 H04N 1/46-1/64

Claims (7)

(57) [Claims] A binarizing means for binarizing a multi-valued color image; a removing means for removing an edge component from the multi-valued color signal based on the binary color signal from the binarizing means; An encoding apparatus for encoding a color image, comprising encoding means for encoding a binary color signal from a value encoding means and a multi-valued color signal from which an edge component has been removed by said removing means. 2. A color image encoding apparatus according to claim 1, wherein said removing means comprises a difference means for calculating a difference between a binary color signal and a multi-valued color signal. Image encoding device. 3. A color image encoding apparatus according to claim 1, wherein said removing means comprises mask means for masking a multi-level color signal with a binary color signal. Encoding device. 4. A color image encoding apparatus according to claim 1, further comprising a conversion unit for converting an output of said binarization unit into a specific value. apparatus. 5. The color image coding apparatus according to claim 1, wherein said coding means is a common coding means for sequentially coding a binary color signal and a multi-valued color signal. An apparatus for encoding a color image. 6. A color image encoding apparatus according to claim 1, wherein after encoding and transmitting the binary color signal,
An apparatus for encoding a color image, which encodes and transmits a multi-valued color signal. 7. A binarizing means for binarizing a multi-valued color image, a removing means for removing a line signal from the multi-valued color signal based on the binary color signal from the binarizing means, An encoding apparatus for encoding a color image, comprising encoding means for encoding a binary color signal from a value encoding means and a multi-valued color signal from which a line signal has been removed by said removing means.