JPH04245893A - Self diagnosis device for digital signal processing circuit - Google Patents

Abstract

PURPOSE:To self-diagnose a timing pulse system circuit pattern while a digital signal processing circuit is operated by providing plural detection means detecting timing pulses supplied to a digital signal processing part. CONSTITUTION:While a TV camera is in an operation state, the pulse detection circuits 410, 510 and 610 always operate. When respective D-FF 411-611 and 612 detect the rise of the respective pulses of a synchronism system timing signal Sts and a color synchronizing system timing signal Stc, they output '1' to terminals 413, 513, 614 and 615. When any of respective timing pulses is not detected, a detection flag corresponding to any of the terminals 413-615 is not raised and '0' is outputted. MPU 71 reads the detection flag leaving appropriate time from a CLR and judges the presence or absence of the supply of the corresponding timing pulse by the presence or absence of the detection flag. Thus, it is self-diagnosed whether the circuit pattern of the timing pulse system is normal or not.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a self-diagnosis device for digital signal processing circuits suitable for digital television cameras and the like.

0002

2. Description of the Related Art A conventional television camera mainly includes an imaging section 10, a video signal processing section 20, and a control section 30, as shown in FIG. 4, for example. The output of the imaging device (CCD) 11 of the imaging section 10 is converted into three primary color video signals of R, G, and B by the imaging signal processing circuit 12 and supplied to the video signal processing section 20 .

Preprocessing circuit 2 of video signal processing section 20
1, shading correction of the three primary color signals R, G, and B, clip level adjustment, etc. are performed, and the mask processing section 22m of the process circuit 22 performs processing such as skin tone adjustment in the case of portrait photography. , the image enhancer section 22i performs signal processing such as edge enhancement. Further, a delay line 23 for edge enhancement etc. is connected between the preprocessing circuit 21 and the processing circuit 22. On the other hand, in the encoding circuit 24, a luminance signal processing section 24y and a color signal processing section 24c convert the three primary color signals R, G, and B that have been subjected to the process processing described above into a composite video signal, a so-called composite signal CMS. Also, a so-called component signal consisting of a luminance signal Y and color difference signals RY and BY is formed.

The control section 30 includes a system control circuit 31, a control panel represented by operation keys 32, and a timing signal generation circuit 33 that generates various timing signals Sts and Stc for synchronization and color synchronization. The timing signals Sts and Stc are supplied to each circuit 21 to 23 of the video signal processing section 20, respectively.

[0005]

[Problem to be Solved by the Invention] In the above-mentioned television camera, because of analog signal processing, when delicate adjustments are required, for example, for skin tone in a portrait,
Otherwise, there were problems such as variations in the adjustment state easily occurring, and skin tones differing slightly from camera to camera.

Incidentally, in recent years, circuit technology and semiconductor technology have made remarkable progress, and it has become possible to digitize and integrate a video signal processing section as shown in FIG. 4 mentioned above. This results in
By using several large-scale integrated circuits (LSI) to process digital signals,
The problem of variations in the adjustment state as described above is solved.

Generally, LSIs equipped with various signal processing circuits
are attached to a test jig, and only those that pass a predetermined test are mounted on a printed wiring board. For example, a scan path test method is used to test a single LSI, and in a test mode, appropriately set input data is supplied from the outside, and output data is observed to determine pass/fail.

However, even when the above-mentioned digital video signal processing circuit is constructed using a printed wiring board on which a tested LSI is mounted, for example, bridges between wiring patterns (so-called bridges) with solder may occur. Malfunctions may occur due to various causes, such as failure or poor connection of connectors, which cannot be detected until the equipment is actually operated, resulting in malfunction.

[0009] When a failure occurs, in order to investigate the cause, it is necessary to examine the video signal processing circuit as described above, but due to digitalization and LSI, circuit configurations have become more complex and detailed. , a problem arises in that it becomes even more difficult to find the location of the failure.

[0010] In view of the above, an object of the present invention is to provide a self-contained system for a digital signal processing circuit that can perform predetermined tests while the digital signal processing circuit is in operation, and that can easily discover failure points. The company provides diagnostic equipment.

[0011]

[Means for Solving the Problems] The present invention provides a self-contained digital signal processing circuit having a digital signal processing section 110 and a timing pulse generation section 33 that supplies a plurality of predetermined timing pulses Sts to the digital signal processing section. This diagnostic device is a self-diagnosis device for a digital signal processing circuit, which is provided with timing pulse detection means 410 and 71 for detecting a plurality of timing pulses supplied to a digital signal processing section.

0012

According to the present invention, during the actual operation of the digital signal processing circuit, a test is performed to determine the presence or absence of timing pulses, that is, the pulse system circuit pattern, and a failure location can be easily discovered.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment in which a self-diagnosis device for a digital signal processing circuit according to the present invention is applied to a video signal processing section of a television camera will be described below with reference to FIGS. 1 to 3. The overall configuration of an embodiment of the present invention is shown in FIG. 3, and the configuration of main parts is shown in FIGS. 1 and 2. In FIG. 3, parts corresponding to those in FIG. 4 are given the same reference numerals and redundant explanation will be omitted.

In FIG. 3, reference numerals 100, 200, and 300 are LSIs, in which the aforementioned preprocessing circuit, process circuit, and encoding circuit are each mounted in a digitalized manner. The digital preprocessing circuit 110 is connected to the imaging unit 10 (
For example, 10-bit parallel data corresponding to the three primary color signals R, G, and B from (see FIG. 4) is supplied. On the other hand, from the digital encoder circuit 310, D-
A composite signal CMS, component signals (Y, RY, BY), etc. are outputted via the A converter 35, and a test signal TST is outputted in a predetermined test mode.

In addition, a RAM 220 for the digital process circuit 210 is mounted on the LSI 200, and a RAM 1 for the preprocess circuit 110, which has a relatively large capacity, is mounted on the LSI 200.
20 is provided outside the LSI 100. Note that control data is derived from the preprocess circuit 110 to an input/output port (not shown).

Test circuits 400, 500, and 600 include a preprocess circuit 110, a process circuit 210,
Each LSI 10 corresponds to the encode circuit 310.
It will be installed on 0,200,300. A diagnostic microprocessor (MPU) 71 is connected to each of the test circuits 400, 500, and 600 via a bus 72.

Each test circuit 400, 500, 600 is
In cooperation with the diagnostic MPU 71, the preprocessing circuit 110
, the process circuit 210, the encode circuit 310, and the supply pulses are tested in the actual operating state in a predetermined mode. Each test circuit 400, 500,
The test functions of 600 are, for example, as follows. (1) Timing pulse detection (2) Circuit pattern check (EXT mode) (3)
) Check inside each LSI (SMP mode) (4)
Check inside each LSI (INT mode) (5) Each R
AM check

In FIG. 1, 410 and 510 are pulse detection circuits included in the test circuits 400 and 500 (see FIG. 3), respectively.
For example, a D flip-flop circuit (D-FF) 411,
511 and AND gates 412 and 512,
A clear pulse CLR is supplied to the D-FFs 411 and 511 via the AND gates 412 and 512, respectively.

Data input terminals of the D-FFs 411 and 511 are respectively connected to the power supply Vcc. The clock terminal of the D-FF 411 is supplied with HD, VD, BLK, and CLP among the synchronous timing signals Sts of the signal generation circuit 33 (see FIG. 3) through the input terminal 13ip, and
, VD, BLK are the delay line 131, latches 132, 23
1 and is supplied to the clock terminal of the D-FF 511. Furthermore, the area detection signal AD generated within the preprocessing circuit 110 is supplied to the clock terminal of the D-FF 511 via the input terminal 23ia. And latch 23
HD and VD from 1 are led out to the output terminal 23op through a delay line 232 and a latch 233.

Note that the delay lines 131 and 232 compensate for the delay time of the digital video signal in the preprocessing circuit 110 and the processing circuit 210, respectively. In addition, HDd1 and VD on each output side of the delay lines 131 and 232
d1; HDd2 and VDd2 are used for generating test timing signals, etc.

In FIG. 2, the pulse detection circuit 610 includes:
It is included in the test circuit 600 (see FIG. 3), and is composed of, for example, D-FFs 611 and 612 and a common AND gate 613, as described above. Pulse CL
R is supplied.

HD, V from the output terminal 23op (see FIG. 1) of the process circuit 210 is input to the first input terminal 33ia.
D is supplied to the second input terminal 33ib,
Among the synchronous timing signals Sts from the signal generation circuit 33 (see FIG. 3), FLD1, CHR, CHRG, SYNC
is supplied. These six signals are supplied to the encoder circuit 310 via the latch 331, and one D
-Supplied to the clock terminal of FF611. Further, the above-mentioned area detection signal AD is supplied to the clock terminal of the D-FF 611 via the input terminal 33ic. In addition, CHR
is a character signal, and CHRG is a character gate signal.

The fourth input terminal 33id is supplied with non-delayed drive signals HDex and VDex from the signal generation circuit 33, and the fifth input terminal 33ie is supplied with various timing signals Stc (BFG, BFG, LALT, SCP
H) is supplied. These signals are supplied to the encode circuit 310 via the latch 332, and are also supplied to the clock terminal of the other D-FF 612. In addition, B
FG is a burst flag, LALT is a line alternate signal, and SCPH is a 10-bit color subcarrier phase signal.

Next, a pulse detection operation according to an embodiment of the present invention will be explained. When the television camera is in operation, the pulse detection circuits 410, 510, 610 are always operating, and the D-FFs 411, 511, 611,
612 is a synchronous system timing signal Sts (HD, VD, etc.) or a color synchronous system timing signal Stc (BFG, L
When detecting the rising edge of each pulse (ALT, etc.), it outputs "1" to each terminal 413, 513, 614, 615 (sets a detection flag).

When any one of the timing pulses is not detected, the corresponding detection flag is not set at one of the terminals 413 to 615, and "0" is output. Note that the detection flag is set to "0" (cleared) by a CLR pulse of a predetermined period, and is reset when the power is turned on.

The MPU 71 reads the above-mentioned detection flag after an appropriate time from the CLR pulse, and determines whether or not the corresponding timing pulse is supplied based on the presence or absence of the detection flag. In other words, in this embodiment, a self-diagnosis is performed as to whether or not the timing pulse system circuit pattern is normal.

[0027]

[Effects of the Invention] As detailed above, according to the present invention,
Since the timing pulse detection means for detecting a plurality of predetermined timing pulses supplied to the digital signal processing section is provided, the presence or absence of timing pulse supply, that is, the pulse system circuit pattern, is detected during the actual operation of the digital signal processing circuit. A self-diagnosis device for a digital signal processing circuit is obtained, which can perform self-diagnosis regarding self-diagnosis.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of essential parts of an embodiment of a self-diagnosis device for a digital signal processing circuit according to the present invention.

FIG. 2 is a block diagram showing the configuration of other main parts of an embodiment of the present invention.

FIG. 3 is a block diagram showing the overall configuration of an embodiment of the present invention.

FIG. 4 is a block diagram for explaining the invention.

[Explanation of symbols]

33 Timing signal generation circuit 71 Test microprocessor

Claims (1)

[Claims] 1. A self-diagnosis device for a digital signal processing circuit, comprising a digital signal processing section and a timing pulse generation section that supplies a plurality of timing pulses to the digital signal processing section, the timing pulse generation section supplying a plurality of timing pulses to the digital signal processing section. A self-diagnosis device for a digital signal processing circuit, comprising timing pulse detection means for detecting the plurality of timing pulses.