KR100470250B1 - Method and apparatus for detecting faults between circuits - Google Patents

Abstract

Methods and apparatus have been provided for diagnosing or detecting failures or defects in or between circuits, such as signal processing circuits of video camera systems. The predetermined test pattern data is generated on the first or transmitting side (circuit), and the discrimination pattern data having a data pattern substantially the same as the test pattern data may be generated on the second or receiving side (circuit) in synchronization with the test pattern data. have. The test pattern data and the discrimination pattern data may be compared. The fault or point of failure in or between the circuits can be determined according to the result of such a comparison.

Description

Method and apparatus for detecting faults between circuits

The present invention relates to a method and apparatus for diagnosing or detecting a fault in a circuit, such as a signal processing circuit of a video camera system.

In a digital signal processing circuit of a system such as an electronic device or a digital video camera system, an analog image sensing signal obtained from a charge-coupled device (CCD) image sensor or the like is converted into a digitized form to generate a video signal. A number of nonlinear signal processings are performed for this purpose. In particular, in such a digital video camera system, the image sensing light obtained from the object by the color image sensing units (CCD image sensor, etc.) is composed of three primary color light components, namely red (R) light component, green (G) light component and blue ( B) decomposes or separates into light components. The tri-color image sensing signal is converted into digital image sensing data by an analog-to-digital (A / D) converter and supplied to the preprocessing circuit, which performs pixel defect compensation and pixel shading compensation in the preprocessing circuit. May be Thereafter, the three primary color image sensing data signal may be supplied to the processing circuit, and linear matrix processing, gamma correction, knee correction, aperture correction, or the like may be performed. Such a processing circuit may generate brightness or luminance data and color difference data from the processed three primary color image sensing data signal. Such luminance data and chrominance data may be converted into analog luminance and chrominance signals by a digital-to-analog (D / A) converter. Thereafter, the composite video signal may be generated and supplied from the encoder based on such luminance signal and chrominance signal. In addition, the luminance data and the chrominance data are supplied to a speed conversion circuit, for example, the clock rate may be converted to a clock rate corresponding to a video tape recorder electrically connected to the video camera system. The signal with the converted rate may be recorded in a video tape recorder.

The processing operation, processing circuit and rate conversion circuit of the preprocessing circuit may be changed by the variable parameters or parameter data of such circuits. As such, parameter data may be supplied and maintained in each circuit prior to commencement of the desired operation.

In the above-described video camera system, the preprocessing circuit, the processing circuit, the rate converting circuit and the like may each be formed as integrated circuits. Such integrated circuits may be installed on one or more printed circuit boards by various techniques, such as soldering. To ensure that such integrated circuits are properly installed or properly connected, such installations and connections may be inspected or verified. However, at the time of failure detection, such failure point or cause is difficult to determine. That is, it is necessary to inspect each component or integrated circuit (or associated solder joint) along the connections between them. It may be difficult to find a point of failure (or points of failure) because the component or integrated circuit is packaged in high density and the signals are processed in digital form. As a result, the time and expense of finding and repairing a fault may be relatively large.

It is an object of the present invention to provide an apparatus and method for performing self-diagnosing in order to facilitate finding a fault or point of failure (s).

More specifically, the test pattern data is supplied from the first portion or side to the second portion or side, and the discrimination pattern data is generated simultaneously with the test pattern data and compared with the test pattern data of the second portion or side, so that the first and Failure points or failures between the second sides are detected based on the comparison result.

According to one aspect of the invention, an apparatus and method for detecting a failure between a first element and a second element are provided. The apparatus includes a first generating unit located in the first element for generating a first data pattern and supplying the generated first data pattern to the second element, and a second in synchronization with the first data pattern supplied from the first element. Between the second generating unit located in the second element for generating the data pattern, the comparison unit for comparing the first and second data patterns, and the first and second elements based on the comparison result obtained by the comparison unit. It includes a unit for detecting the failure of. The method for detecting a failure between the first and second elements comprises corresponding steps.

The first element may be an integrated circuit or may include a test pattern generation unit for generating predetermined test pattern data and for supplying such test data at the same transmission rate as the transmission data. The second element may be another integrated circuit, and a discrimination pattern generating unit for generating discrimination pattern data in synchronization with the test pattern data, a pattern comparator for comparing the test pattern data and the discrimination pattern data, and a comparison of the pattern comparator It may also include a self-diagnostic unit for detecting a fault or point of failure on the data transmission line between the first and second element or integrated circuit based on the result.

Therefore, in the present invention, the predetermined test pattern data may be supplied at a transmission rate substantially the same as the transmission data from the test pattern generation unit provided on the data transmission side (first side or element). On the data receiving side (second side or element), the discrimination pattern generating unit generates discrimination pattern data which may be synchronized with and may be the same as the test pattern data supplied from the data transmitting side, and the pattern comparator generates the test pattern data and the discriminating pattern data. Compare The failure or point of failure between the transmitting side and the receiving side may be detected based on the result of such a comparison.

Other objects, features and advantages according to the present invention will become apparent from the following detailed description of the described embodiments when understood in conjunction with the accompanying drawings in which corresponding components are identified by the same reference numerals.

Embodiments of the present invention will now be described with reference to the accompanying drawings. In this description, the present embodiment will be applied to a digital video camera system. However, the present invention is not limited thereto and may be applied or used in other systems or applications.

A video camera system incorporating the present invention is shown in FIGS. 1 and 2. As shown, such a video camera system includes a camera block 21 and a connecting member 22 connected to the camera block. The connecting member may be a video tape recorder (VTR) block or the like. The video camera system may further include a shoulder pad 24 mounted to the bottom of the camera block 21. The shoulder pad 24 may have a portion where the VTR block 22 protrudes beyond the rear surface 23 of the camera block 21 arranged thereon.

The VTR block 22 and the camera block 21 may be electrically connected together by a connector or the like. For example, the contact pins 28 of the male connector 27 provided on the front 26 side of the VTR block 22 are female connectors provided on the rear 23 of the camera block 21. Since it can be inserted into the corresponding connection socket or portion (not shown) of 25, the camera block 21 and the VTR block 22 are electrically connected together.

The arrangement of the camera block 21 is shown in FIG. 3A. Such a camera block comprises CCD image sensors 10R, 10G and 10B, a signal selector 15, a preprocessing circuit 20, a processing circuit 30, a first-in first-out (FIFO) unit 52, A rate conversion circuit 60, an encoder 62, and a microcomputer (microcomputer) 76 are included, which are connected as shown in FIG. 3A.

The color image pickup unit or CCD image sensors 10R, 10G and 10B respectively supply the three primary color image detection signals SR, SG and SB to the analog-to-digital (A / D) converter 13 to provide digital image detection data. Fields DAR, DAG, and DAB are sequentially converted and supplied to the signal selector 15. The signal selector 15 collects test pattern data EAR, EAG and EAB from an operation inspection jig 200 (described in more detail below) that is electrically connected to the signal selector 15 during operation of the video camera system. You can also receive more. The signal selector 15 selects the image sensing data DAR, DAG and DAB or the test pattern data EAR, EAG and EAB and supplies it to the preprocessing circuit 20 as the selected data.

As shown in FIG. 4, the selected data PIR, PIG and PIB from the signal selector 15 are passed through the registers 21R, 21G and 21B to the preprocessing signal processor 22 of the preprocessing circuit 20, The pattern comparator 23 and the pulse detector 24 are respectively supplied.

When the selected data PIR, PIG, and PIB are the image sensing data DAR, DAG, and DAB, the preprocessing signal processor 22 performs such processing such that the predetermined processing such as pixel defect compensation, pixel shading compensation, etc. is performed. You may. Such processing (ie defect compensation, shading compensation, etc.) can be performed using the RAM 17 connected to the preprocessing circuit 20 as shown in FIG. 3A. The processed data PIR, PIG and PIB from the preprocessing signal processor 22 are supplied to the signal selectors 25R, 25G and 25B as three primary color image sensing data DBR, DBG and DBB, respectively. In addition, the pulse detector 24 may determine whether there is a pulse for the selected data PIR, PIG and PIB, and may supply the result of this determination to the microcomputer 76 as an output signal RCA.

When the selected data PIR, PIG and PIB are the test pattern data EAR, EAG and EAB, the discrimination pattern generator 26 is in accordance with the control signal CA supplied from the microcomputer 76. Discrimination pattern data FAR, FAG and FAB can be generated at the same time as the EAR, EAG and EAB. The generated discrimination pattern data FAR, FAG and FAB and the selected data PIR, PIG and PIB (which are test pattern data EAR, EAG and EAB) are supplied to the pattern comparator 23. The pattern comparator 23 compares the discrimination pattern data EAR, EAG and EAB with the selected data PIR, PIG and PIB to form a comparison signal RPA for supply to the microcomputer 76.

In addition, the test pattern generator 27 may generate test pattern data EBR, EBG and EBB in accordance with the control signal CA supplied from the microcomputer 76, and may convert them into signal selectors 25R and 25G. And 25B), respectively. In addition, the test pattern generator 27 may generate the selection signal SEA according to the control signal CA, and may supply it to the signal selectors 25R, 25G, and 25B. In response to the selection signal SEA, the signal selectors 25R, 25G and 25B select one of the three primary color image sensing data DBR, DBG and DBB or the test pattern data EBR, EBG and EBB, respectively. Supply the selected data to the processor circuit 30 via the registers 28R, 28G and 28B as selected data POR, POG and POB. In addition, a plurality of such selected data signals are delayed by a predetermined amount and supplied to the processing circuit 30. For example, as shown in FIG. 3A, the selected data POR may be supplied to the processing circuit 30 by a delay by one horizontal retrace period by the delayer 51AR. Such delayed data POR may be delayed by another horizontal retrace period by the delayer 51BR and supplied to the processing circuit 30. Similarly, the selected data POG may be delayed by one horizontal retrace period by the retarder 51AG and supplied to the processing circuit 30, and the delayed data POG may be supplied by another delayer 51BG. It may be delayed by the horizontal retrace period and supplied to the processing circuit 30.

As shown in FIG. 5, the selected data and the delayed data from the preprocessing circuit 20 are supplied to the process signal processor 38 and the pattern comparator 39 of the processing circuit 30 through the registers 31 to 37. do. In particular, the selected data POR is supplied to the processing signal processor 38 and the pattern comparator 39 via the register 31, and the selected and delayed data POAR (delayed by the delay unit 51AR) is stored in the register ( 32 is supplied to the processing signal processor 38 and the pattern comparator 39, and the selected and delayed data POBR is supplied to the processing signal processor 38 and the pattern comparator 39 through the register 33, The selected data POG is supplied to the processing signal processor 38 and the pattern comparator 39 through the register 34, and the selected and delayed data POAG (delayed by the delay unit 51AG) is stored in the register 35. Supplied to the processing signal processor 38 and the pattern comparator 39, and the selected and delayed data POBG (delayed by the delay unit 51BG) is transferred to the processing signal processor 38 and the pattern through the register 36. The selected and delayed data POB supplied to the comparator 39 stores the register 37. It is supplied to the signal processing processor 38 and the pattern comparator 39.

The processing signal processor 38 causes predetermined processing (such as linear matrix processing, gamma correction or control, bending correction, gap correction, etc.) to be performed on the received data (POR, POAR, POBR, POG, POAG, POBG and POB). And brightness or luminance data DY and chrominance signal data DCr and DCb are generated by the YC matrix processing, which is supplied to selectors 40Y, 40r and 40b, respectively. The processing signal processor 38 also generates viewfinder data VFD, and supplies this data to the FIFO unit 52 (FIG. 3A).

The discrimination pattern generator 41 synchronizes the discrimination pattern data FBR, FBAR in synchronization with the data POR, POAR, POBR, POG, POAG, POBG and POB according to the supply control signal CB from the microcomputer 76. , FBBR, FBG, FBAG, FBBG and FBB) can be generated. The generated discrimination pattern data FBR, FBAR, FBBR, FBG, FBAG, FBBG and FBB are supplied to the pattern comparator 39, which also selects the data (POR, POAR, POBR, POG, POAG, POBG and POB). ). The pattern comparator 39 compares the discrimination pattern data FBR, FBAR, FBBR, FBG, FBAG, FBBG and FBB with the selected data (POR, POAR, POBR, POG, POAG, POBG and POB), and compares the comparison signal. (RPB) is formed and supplied to the microcomputer 76.

The test pattern generator 42 can generate the test pattern data EY, ECr and ECb according to the control signal CB supplied from the microcomputer 76, which is then used to generate the signal selectors 40Y, 40r and 40b). In addition, the test pattern generator 42 may generate the selection signal SEB according to the control signal CB, and may supply them to the signal selectors 40Y, 40r, and 40b. In response to the selection signal SEB, the signal selectors 40Y, 40r, and 40b respectively select luminance data DY, color difference signals DCr and DCb, or test pattern data EY, ECr, and ECb, respectively. One is selected to supply the selected data as selected data ROY, ROCr and ROCb to the FIFO unit 52 through the registers 43Y, 43r and 43b.

Returning to FIG. 3A, the FIFO unit 52 receives the viewfinder data VFD and the selected data ROY, ROCr and ROCb from the processing circuit 30, so that the so-called cut-out control is performed. To be done. By way of example, data may be processed or cut out from selected data ROY, ROCr and ROCb, changing the aspect ratio of the displayed image, for example, from 16: 9 to 4: 3. .

The cut-out viewfinder data VFD may be supplied from the FIFO to the digital-to-analog (D / A) converter 54 and may be converted into an analog viewfinder signal SF. The viewfinder signal SF may be supplied to the viewfinder 64, and a photographed image corresponding to the viewfinder signal SF may be displayed.

Cut-out data ROY, ROCr and ROCb may be supplied to a digital-to-analog (D / A) converter 53, such data being analog luminance signal SY and analog chrominance signals SCr and SCb. ) And then supplied to the encoder 62. In accordance with the luminance signal SY and the chrominance signals SCr and SCb, the encoder 62 generates a video signal SV and supplies it therefrom.

As shown in FIGS. 3A and 3B, the cut-out data ROY, ROCr and ROCb may also be supplied to the rate conversion device 400 in the rate conversion circuit 60, and the clock rate of such data. Can be converted to a predetermined rate. For example, the conversion circuit 60 converts the clock rate of the selected data ROY, ROCr and ROCb to the clock rate corresponding to the VTR block 22 and the image clock rate converted data DOY, DOCr and DOCb. ) Is supplied to the VTR block 22 through the selector 402. The rate conversion circuit 60 may also include a discrimination pattern generator 404 and a pattern comparator 406 that operate in a manner similar to that of the preprocessing circuit 20 and the processing circuit 30. That is, the pattern comparator 406 in the rate converting circuit 60 supplies discrimination data generated from the discriminating pattern generator 404 in the rate converting circuit 60 and supplied from the processing circuit 30 through the FIFO unit 52. The test pattern data is received and the received data is compared to form a comparison signal RPC, which is supplied to the microcomputer 76 via the bus. The rate conversion circuit 60 further includes a test pattern generator 408 for generating test pattern data in a manner similar to the test pattern generators 27 and 42 described above. The test pattern data from the test pattern generator 408 of the rate conversion circuit 60 is supplied to the VTR block 22 through the selector 402 along with the image rate converted data DOY, DOCr and DOCb. The operation of the rate conversion circuit 60 can be controlled according to the control signal CC supplied from the microcomputer 76.

The VTR block 22 may include a recorder / player 424 for performing recording and / or reproducing operations. The VTR block 22 may further include a discrimination pattern generator 420 and a pattern comparator 422 that are similar to and operate in a similar manner to the discrimination pattern generators 26 and 41 and the pattern comparators 23 and 39 described above. Can be. The data generated from the discrimination pattern generator 420 of the VTR block 32 may be compared with the test pattern data supplied from the rate conversion circuit 60 and form a comparison signal RPD supplied to the microcomputer 76. do. As a result, it is determined whether a failure has occurred.

The microcomputer 76 may generate control signals CA, CB and CC, each of which supplies these signals to the preprocessing circuit 20, the processing circuit 30 and the rate converting circuit 60 to operate them. To control. In addition, based on the comparison result from the preprocessing circuit 20, the processing circuit 30, the rate conversion circuit 60 and the VTR block 22, and the determination result RCA from the pulse detector 24, The computer 76 can determine whether each circuit and the VTR block are properly connected or if a failure has occurred between them.

The reference signal generator 70 generates a reference signal HF and supplies it to the drive controller 72. The reference signal generator 70 also generates a horizontal synchronizing signal HD, a vertical synchronizing signal VD, and the like, and supplies them to the processing circuit 30 and the rate converting circuit 60 so that signal processing can be performed at a predetermined time. do.

In addition, the shading compensation data calculated by the preprocessing circuit 20 is supplied to a digital-to-analog (D / A) converter 74 and converted into an analog shading compensation signal SH which can be supplied to the drive controller 72. do. Depending on the shading compensation signal SH and the reference signal HF from the reference signal generator 70, the drive controller 72 can generate a drive signal RV, which is then CCD image sensors 10R, 10G and 10B. Supplies). As a result, shading that may be associated with each of the image sensing signals SR, SG, and SB can be reduced. The drive controller 72 may also generate a clock signal CK in synchronization with the reference signal HF, which may supply it to the preprocessing circuit 20, the processing circuit 30, the rate converter 60 and other desired circuits. have. As a result, each such circuit can perform signal processing in synchronization with the clock signal CK.

As described above, the test pattern data EAR, EAG, and EAB may be generated by the operation test jig 200 and supplied to the signal selector 15. This operation test jig 200 is shown in FIG. As shown, the operation test jig 200 includes a trigger generator 201 and a test pattern generator 202, which trigger generator 201 is vertically synchronized with the horizontal sync signal HD from the reference signal generator 70. Receive clock signal CK from signal VD and drive controller 72, and test pattern generator 202 also receives clock signal CK from drive controller 72. The trigger generator 201 may generate the trigger signal TG at a predetermined timing based on the horizontal sync signal HD, the vertical sync signal VD, and the clock signal CK, and supply it to the test pattern generator 202. do. The test pattern generator 202 may generate test pattern data EAR, EAG, and EAB according to the trigger signal TG, and may supply such data to the signal selector 15 based on the clock signal CK. Can be. In addition, the operation test jig 200 is connected to the microcomputer 76 to enable communication therebetween. For example, the microcomputer 76 may control the operation of the operation test jig by supplying a control signal to the operation test jig 200.

The timing arrangement used to output the test pattern data generated in the apparatus is shown in FIG. That is, FIG. 7A shows the vertical sync pulse VD, FIG. 7B shows the horizontal sync pulse HD, FIG. 7C shows the red image sensing data DAR, and FIG. 7D shows the green image sensing data ( DAG), FIG. 7E shows blue image sensing data DAB, and FIGS. 7F-7I respectively show horizontal sync pulse HD and image sensing data DAR, DAG and DAB for the next field. Illustrated. The number given to the horizontal synchronizing pulse HD indicates a horizontal retrace line. The three primary color image sensing data DAR, DAG and DAB represent the horizontal line numbers for the pixels of the CCD image sensors 10R, 10G and 10B, respectively.

The signal selectors 25R, 25G and 25B (FIG. 4) and the signal selectors 40Y, 40r and 40b (FIG. 5) are image sensed data DAR, such as during the 15th and 277th horizontal retrace lines, respectively. The test pattern data EBR, EBG, EBB and EY, ECr, ECb are selected during the period in which the DAG and DAB have the vertical optical black level VOPB, and the selected data is supplied to the next step circuit. (For example, vertical optical black is obtained as the output of an optical sensor that is shielded to prevent incidence of light and output during the vertical retrace period. In this regard, US Pat. No. 4,553,169 is incorporated herein by reference. .) By supplying test pattern data (which can be used to detect faults) during the period when the image sensed data (DAR, DAG and DAB) have an optical black level, the test pattern data adversely affects the displayed image. It can be supplied or transmitted without giving. Similarly, the signal selector 15 may select the test pattern data EAR, EAG and EAB supplied from the test pattern generator 202 of the operation test jig 200 during the 15th and 277th horizontal retrace lines.

An example of a test pattern generator (such as test pattern generator 27 or 42) will now be described.

As shown in FIG. 8, the test pattern generator includes a JK flip-flop 101, OR gates 102 and 104, NAND gate 105, and AND gates 103, 106-1 through 106-12, 109B. , 109R, 109G, and 111, selectors 108G, 108R, and 108B and latches 110G, 110R, 110B, and 107-1 through 107-12.

출력 단자는 NAND 게이트(105)의 다른 입력 단자에 연결되고, NAND 게이트(105)의 출력 단자는 각각의 AND 게이트들(106-1 내지 106-12, 109B, 109R 및 109G)의 입력 단자에 연결된다. 래치, 선택기, 게이트 및 다른 소자들 사이의 나머지 접속은 도 8에 도시된 바와 같다.The trigger signal input terminal 100 is connected to the J input terminal of the JK flip-flop 101 and one input terminal of the respective OR gates 102 and 104. The output terminal of the OR gate 102 is connected to the input terminal of the AND gate 106-1 and the selectors 108B, 108R, and 108G. The K input terminal of the JK flip-flop 101 is connected to the output terminal of the AND gate 111 and the input terminal of the AND gate 103 and the NAND gate 105. The Q output terminal of the JK flip-flop 101 is connected to the other input terminal of the AND gate 103, and the output terminal of the AND gate 103 is connected to the other input terminal of the OR gate 104. The output terminal of the OR gate 104 is connected to the selector 108B. Of JK flip-flop (101)

The output terminal is connected to the other input terminal of the NAND gate 105, and the output terminal of the NAND gate 105 is connected to the input terminal of the respective AND gates 106-1 to 106-12, 109B, 109R, and 109G. do. The remaining connections between latches, selectors, gates, and other elements are as shown in FIG.

The microcomputer at the time t1 shown in FIGS. 9B and 11 during the period in which the triggered signal TR (such as a positive pulse) has image sensed data DAR, DAG and DAB having the optical black level VOPB. When supplied from 76 to trigger signal input terminal 100, output signal LB from OR gate 102 (FIG. 9C) may have a relatively high level H (such as 1). Further, in this initial state, the output signal from the latches 107-1 to 107-12, 110R, 110G and 110B (FIGS. 9E-9S) and the output signal LH from the AND gate 111 are ( It can have a low level (L) (such as 0). The output signal LH from the AND gate 111 (having the low level L) is supplied to the K input terminal of the J-K flip-flop 101 and one input terminal of the NAND gate 105. As a result, the output signal LE (FIG. 9D) from the NAND gate 105 has a high level H, whereby the output signal from the AND gate 106-1 has a high level. Further, when the output signal LB of the OR gate 102 has a high level H, the selector 108B receives the output signal LC (having a high level H) from the OR gate 104. It can be selected and supplied to the input of the AND gate 109B. The other input terminal of AND gate 109B receives the output signal LE from NAND gate 105 (having high level H). As a result, the output signal of the AND gate 109B has a high level (H). In addition, selector 108R can select output signal LG from latch 110B (having low level L), selector 108G output signal LGR (low) from latch 110R. Level L).

Accordingly, the output signal LF1 from the latch 107-1, the output signal LG from the latch 110B and the output signal LA from the output terminal Q of the JK flip-flop 101 are shown in FIG. It has a high level H at time t2 or at the leading edge of the next clock pulse CK as shown in 9E, 9Q and 9T. After that, the output signal LB from the OR gate 102 goes low. As a result, the selector 108B can select the output signal LG from the latch 110B, the selector 108R can select the output signal LGR from the latch 110R, and the selector 108G The output signal LGG from the latch 110G can be selected.

In addition, the respective output signals of the latches 107-1 to 107-12, 110R, 110G and 110B and the output signal LA of the J-K flip-flop 101 are supplied to the pulse generator 120. Such a pulse generator is further shown in FIG. As shown in Fig. 10, the output signal LF1 from the latch 107-1 is supplied to the input terminal of the AND gates 121B-1, 121R-1 and 121G-1, respectively, and the latch 107 The output signal LF2 from -2 is supplied to the input terminal of the AND gates 121B-2, 121R-2, and 121G-2, respectively, and the output from the latches 107-3 to 107-12. The signals LF3 to LF12 are similarly supplied to the input terminals of the corresponding AND gates 121B-3 to 121B-12, 121R-3 to 121R-12, 121G-3 to 121G-12. In addition, the output signal LG from the latch 110B is supplied to the input terminal of the respective AND gates 121B-1 to 121B-12, and the output signal LGR from the latch 110R is the respective AND. Supplied to the input terminals of the gates 121R-1 to 121R-12, and an output signal LGG from the latch 110G is supplied to the input terminals of the respective AND gates 121G-1 to 121G-12. . In addition, the output signal from AND gates 121B-1 through 121B-12, 121R-1 through 121R-12, 121G-1 through 121G-12 are exclusive-OR (XOR) gates 122B-1 through 122B, respectively. -12, 122R-1 to 122R-12, 122G-1 to 122G-12). The signal LA from the Q output terminal of JK flip-flop 101 is different from that of each of the XOR gates 122B-1 through 122B-12, 122R-1 through 122R-12, 122G-1 through 122G-12. It is supplied to the input terminal.

If the output signal LF1 from the latch 107-1 and the output signal LG from the latch 110B have a high level H at time t2 (Figs. 9E and 9Q), then AND gate 121B. The output signal from -1) has a high level H, which is supplied to one input of the XOR gate 122B-1. At this time t2, if the output signal LA from the JK flip-flop 101 has a high level H (Fig. 9T), the output signal B1 from the XOR gate 122B-1 is It has a low level (L) as shown in FIG. Also, at time t2 the output signals LF-2 to LF-12, LGR and LGG are low (FIGS. 9F-9P, 9R and 9S). As a result, the output signals of the AND gates 121B-1 through 121B-12, 121R-1 through 121R-12, 121G-1 through 121G-12 each have a low level, whereby the XOR gates 122B- Output signals B-1 through B-12, R-1 through R-12, G-1 through 1-122B-12, 122R-1 through 122R-12, 122G-1 through 122G-12, respectively G-12) each have a high level H, as shown in FIG.

Further, at time t2, since the output signal LF1 from the latch 107-1 (FIG. 8) and the output signal LE from the NAND gate 105 each have a high level H, AND The output signal from the gate 106-2 goes high. The output signal LB from the OR gate 102 is at a low level, whereby the output signal from the AND gate 106-1 is also at a low level. As a result, at time t3 (or the leading edge of the next clock CK pulse), the output signal LF2 from the latch 107-2 becomes the high level H, and from the latch 107-1 Output signal LF1 becomes low as shown in Figs. 9E and 9F. As a result, at time t3, only the output signal of AND gate 121B-2 (FIG. 10) becomes high level, and only the output signal B2 of XOR gate 122B-2 (FIG. 10) is FIG. Goes low as shown in FIG.

Processing similar to the above is continued. At time t4, output signal LF12 of latch 107-12 is at a high level (as shown in Fig. 9P), and as a result, output signal LB of OR gate 102 is (Fig. High) as shown in 9C. Thereby, the selector 108B can select the output signal LC from the OR gate 104 having a low level, the output signal of the AND gate 109B is at a low level, and the selector 108R is at a high level. The output signal LG from the latch 110B having Fig. 9Q can be selected, and the output signal of the AND gate 109R becomes high. In addition, the output signal LB of the OR gate 102 and the output signal LE of the NAND gate 105 each have a high level H, and the output signal of the AND gate 106-1 becomes high. Thus, at time t5 (or the next rising edge of clock signal CK), only output signal LF1 from latch 107-1 and output signal LGR from latch 110R become high ( 9E and 9R, only the output signal R1 of the XOR gate 122R1 (FIG. 10) becomes low level as shown in FIG.

Processing similar to the above is continued. At time t6, output signal LF12 from latch 107-12 and output signal LGG from latch 110G each have a high level (Figs. 9P, 9S), as a result of which the XOR gate The output signal G12 from 122G-12 goes low and the output signal LH from AND gate 111 goes high. Since the output signal LF12 is high, the output signal LB from the OR gate 102 becomes high level, and as a result, the selector 108B selects the output signal LC from the OR gate 104. Can be. Since the output signal from the AND gate 103 has a high level due to the output signal LA of the JK flip-flop 101 and the output signal LH of the AND gate 111, respectively, having a high level. The output signal LC has a high level. In addition, the output signal LD of the JK flip-flop 101 has a low level, and the output signal LE of the NAND gate 105 has a high level regardless of the output signal LH from the AND gate 111. Has Thereby, since the output signal LE and the output signal LB each have a high level, the output signal of the AND gate 106-1 is high.

At time t7 (or next leading edge of clock signal CK), output signal LA of JK flip-flop 101 goes low (FIG. 9T), and output signal from latch 107-1. Only the output signal LG from the LF1 and the latch 110B becomes the high level H (Figs. 9E and 9Q), respectively. In addition, the output signal LH from the AND gate 111 becomes low. Thereby, even if the output signal LD from the J-K flip-flop 101 becomes high level, the output signal LE of the NAND gate 105 will remain at the high level.

At time t7, only output signal LF1 from latch 107-1 and output signal LG from latch 110B go high (FIGS. 9E and 9Q). As a result, only the output signal from the AND gate 121B-1 (Fig. 10) has a high level. Only the output signal from the AND gate 121B-1 is high and JK (supplied to the XOR gates 122B-1 through 122B-12, 122R-1 through 122R-12, 122G-1 through 122G-12) Since the output signal LA from the flip-flop 101 is low, only the output signal B1 of the XOR gate 122B-1 is high, and the XOR gates 122B-2 to 122B-12 and 122R-1 are high. The other output signals B2 to B12, R1 to R12, and G1 to G12 of the to 122R-12, 122G-1 to 122G-12 become low level at time t7 as shown in FIG.

Thereafter, processing similar to the above is continued. That is, as illustrated in FIG. 11, output signals B2 to B12 and R1 to R12 of the XOR gates 122B-2 to 122B-12, 122R-1 to 122R-12, and 122G-1 to 122G-12. , G1 to G12) are continuously switched to a high level. At time t8, output signal LF12 from latch 107-12 and output signal LGG of latch 110G have a high level (FIGS. 9P 'and 9S'), resulting in an AND gate. The output signal LH of 111 has a high level. (FIGS. 9A 'through 9T' are continuations of FIGS. 9A through 9T along the time axis.) At this time, the output signal LH of the AND gate 111 is high, and the JK flip-flop 101 Since the output signal LD is also high, the output signal LE of the NAND gate 105 goes low (Fig. 9D '). As a result, the output signal from AND gate 106-1 goes low, and at the next rising edge or time t9 of clock signal CK, all output signals from latches 107-1 through 107-12. LF1 to LF12 and output signals LG, LGR, and LGG from latches 110B, 110R, and 110G are at a low level, and XOR gates 122B-1 to 122B-12, 122R-1 to All output signals B1 to B12, R1 to R12, G1 to G12 of 122R-12 and 122G-1 to 122G-12 are low as shown in FIG.

As can be appreciated, such test pattern data can be considered as a series of low (0) and high (1) data pulses. This use of both low and high data pulses reduces the likelihood of error. For example, consider a situation where the test pattern data is a series of only high (1) data pulses. In this situation, assume that a fault has occurred and instead of forming a low (0) data pulse (which would indicate a fault), "1" is formed and transmitted as an error. As a result, such a failure may be determined or not detected. However, by using both low and high data pulses, such a failure will be detected even if such a failure occurs and "1" is formed and transmitted as an error. That is, "1" formed as an error will be detected as a failure by using a low data pulse.

Thus, the test pattern data can be generated as described above. In addition, such test pattern data may be generated by any of the test pattern generators of the apparatus such as, for example, the test pattern generator 202 of the jig 200 (FIG. 6). In this example, the test pattern data EAR, EAG, and EAB generated by the test pattern generator 202 of the jig 200 may be 12-bit parallel data, so that the test pattern data EAB is the XOR gate. Corresponding to the output signals B1 to B12 of the signals 122B-1 to 122B-12, and the test pattern data EAR is output signals R1 to of the XOR gates 122R-1 to 122R-12. Corresponding to R12, the test pattern data EAG corresponds to output signals G1 to G12 of the XOR gates 122G-1 to 122G-12. The generated test pattern data may be supplied to the pattern comparator 23 of the preprocessing circuit 20 through the signal selector 15 in the above-described manner and as shown in FIGS. 3A and 4.

The discrimination pattern generator of the present apparatus, such as the discrimination pattern generator 26 of the preprocessing circuit 20, may be configured similarly to that of the test pattern generator described above shown in Figs. In this situation, the output signals B1 to B12 of the XOR gates 122B-1 to 122B-12 may be discrimination pattern data FAB, and the XOR gates 122R-1 to 122R-12 may be used. The output signals R1 to R12 may be discrimination pattern data FAR, and the output signals G1 to G12 of the XOR gates 122G-1 to 122G-12 may be discrimination pattern data FAG. have. Such discrimination pattern data can be supplied to the pattern comparator 23 (FIG. 4).

The pattern comparator 23 of the preprocessing circuit 20 may be configured as shown in FIG. 12. The pattern comparator 23 stores the test pattern data EAB, EAR, and EAG from the jig 200 (FIG. 6) and the discrimination pattern data FAB, FAR, and FAG from the discrimination pattern generator 26. Can be received and compared to such received data. More specifically, as shown in FIG. 12, the test pattern data EAB, EAR, and EAG are XOR gates 130B-1 to 130B-12, 130R-1 to 130R-12, 130G-1 to 130G. -12). For example, the test pattern data EAB-1 may be supplied to the XOR gate 130B-1, the test pattern data EAR-1 may be supplied to the XOR gate 130R-1, and so on. do. As further shown in FIG. 12, the discrimination pattern data FAB, FAR and FAG are stored in the XOR gates 130B-1 to 130B-12, 130R-1 to 130R-12, 130G-1 to 130G-12. Can be supplied. For example, the discrimination pattern data FAB-1 may be supplied to the XOR gate 130B-1, and the discrimination pattern data FAR-1 may be supplied to the XOR gate 130R-1, and so on. do. Therefore, when the test pattern data EAB, EAR and EAG and the discrimination pattern data FAB, FAR and FAG are properly transmitted in synchronization with the pattern comparator 23, the XOR gates 130B-1 to 130B-12. , All output signals (RPAB-1 to RPAB-12, RPAR-1 to RPAR-12, RPAG-1 to RPAG-12) of 130R-1 to 130R-12 and 130G-1 to 130G-12 are low. do. On the other hand, if a portion of the test pattern data is improperly transmitted to the pattern comparator 23 as may occur when a failure exists, the output of the corresponding XOR gate may be high. As a result, a failure such as a breakdown of a signal line or a short circuit can be easily detected.

As described above, as shown in FIG. 3A, the selected data from the preprocessing circuit 20 can be delayed by one horizontal retrace period by the delayers 51AR and 51AG, and selected by the processing circuit 30. Can be supplied as data POAR and POAG, the selected data POR and POG can be delayed by two horizontal retrace periods by the delayers 51AR, 51BR, 51AG and 51BG, and the processing circuit ( 30 may be supplied as selected data (POBR and POBG). As a result, the test pattern generator 27 of the preprocessing circuit 20 (FIG. 4) allows the image sensed data DAR, DAG, and DAB to display the optical black level VOPB as shown in FIGS. Test pattern data EBB1, EBR1 and EBG1 are obtained from a pulse of the horizontal synchronization signal HD during a horizontal retrace period having a timing sequence corresponding to the selected data delayed, for example, after a predetermined time lapse or delay of the TA. You can print More specifically, the output of the test pattern data EBB1 may be started at time t11 and completed at time t12, and the output of the test pattern data EBR1 may be time t13 after 4 TB of elapse or delay. The output of the test pattern data EBG1 may be started after completion of the test pattern data EBR1 and completed at time t14. (The period between time t11 and time t12 is TB, the period between time t12 and time t13 is 4 TB, and the period between time t13 and time t14 is 4 TB.) Next, the polarity of the pulses for the test pattern data can be reversed, the output of the test pattern data EBB1 can be started at time t14 and completed at time t15, and the test pattern data EBR1 can be reversed. The output can be started at time t16 after the elapse or delay of 4TB, and the output of the test pattern data EBG1 can be started after completion of the test pattern data EBR1 and completed at time t17. (The period between time t14 and time t15 is TB, the period between time t15 and time t16 is 4 TB, and the period between time t16 and time t17 is 2 TB.) As can be appreciated, the timing sequence or arrangement of the test pattern data EBB, EBR and EBG may differ from that described above.

Thus, when the test pattern data EBB1, EBR1 and EBG1 are respectively selected by the signal selectors 25B, 25R and 25G of the preprocessing circuit 20 (FIG. 4), such data can be output therefrom and Delayed in the above manner, the selected data (POB, POR, POG, POAR, POAG, POBR and POBG) supplied to the processing circuit 30 in the timing sequence as shown in FIG. 16 is formed. That is, as shown in FIG. 16, the test pattern data EBB1, EBR1, and EBG1 are selected from the selected data (starting at time t11 after the elapse or time delay of TA when viewed along the horizontal synchronization signal HD ( POB, POR and POG). During the next horizontal retrace period, the test pattern data EBB2, EBR2 and EBG2 may be output after the elapsed or time delay of the TA along the horizontal synchronization signal with a timing sequence as shown in FIGS. 14 and 16. More specifically, the output of the test pattern data EBB2 may be started at time t21 and completed at time t22, and the output of the test pattern data EBR2 may be output at time t23 after a lapse or delay of 2 TB. And the output of the test pattern data EBG2 may be started after completion of the test pattern data EBR2 and completed at time t24. (The period between time t21 and time t22 is TB, the period between time t22 and t23 is 2TB, and the period between time t23 and t24 is 2TB.) Next, the polarity of the pulse for the test pattern data is reversed. And the output of the test pattern data EBB2 may be started at time t25 and complete at time t26 after 2 TB of time or time delay from time t24, and the output of test pattern data EBR2 may be May be initiated at time t27 after 2 TB of elapsed or delay, The output of the data (EBG2) may be initiated after completion of the test pattern data (EBR2) is completed in a time (t28).

Thus, when the test pattern data EBB2, EBR2 and EBG2 are selected by the signal selectors 25B, 25R and 25G of the preprocessing circuit 20 (FIG. 4), such data is shown in FIG. It is supplied from there as selected data (POB, POR and POG) starting at time t21 as shown. Further, the test pattern data EBR1 and EBG1 may be supplied as the selected data POAR and POAG starting at time t24 upon completion of supply of the test pattern data EBG2.

During the next horizontal retrace period, the test pattern data EBB3, EBR3 and EBG3 have a timing sequence as shown in Figs. 15 and 16 and at time t31 after the elapsed or time delay of the TA along the horizontal synchronizing signal. It can be output continuously to start and complete at time t32. After 4 TB of elapse or time delay from time t32 or at time t34, the polarity of the pulses for the test pattern data can be reversed, and the test pattern data EBB3, EBR3 and EBG3 are at time t35. It can be output continuously from the time t34 until the completion of.

Thus, when the test pattern data EBB3, EBR3 and EBG3 are selected by the signal selectors 25B, 25R and 25G of the preprocessing circuit 20 (FIG. 4) respectively, such data is shown in FIG. It is supplied from there as selected data POB, POR and POG starting at time t31 as shown. Further, the test pattern data EBR2 and EBG2 may be supplied as the selected data POAR and POAG starting at time t32 upon completion of the test pattern data EBG3. Also, the test pattern data EBR1 and EBG1 may be supplied as the selected data POBR and POBG starting at time t33 upon completion of the test pattern data EBG2.

Thus, in the above manner, the selected data POB, POR, POG, POAR, POAG, POBR and POBG form a row of continuous pulses supplied to the pattern comparator 39 of the processing circuit 30 (FIG. 5). can do. In addition, the determination pattern generator 41 may generate test pattern data FB substantially the same as the selected data POB, POR, POG, POAR, POAG, POBR, and POBG. The pattern comparator 39 compares the discrimination pattern data FB with the selected data (POB, POR, POG, POAR, POAG, POBR and POBG) in a similar manner to that described above with reference to the pattern generator 23. You can use exclusive OR of. Thereby, when a failure occurs, the corresponding output of the pattern comparator 39 can be made high. As a result, a fault or a point of failure can be easily detected.

The fault or failure point between the processing circuit 30 and the rate converting circuit 60 or between other circuits in the apparatus, such as between the rate converting circuit 60 and the VTR block 22, can be determined in a manner similar to that described above. have. That is, in such a situation, the test pattern data may be generated on the first or transmitting side (circuit), and the data pattern such as test pattern data may be generated on the second or receiving side (circuit), such generation Once the test pattern data and the discrimination pattern data have been supplied to the pattern comparator in a timely or simultaneous manner, such data is compared, and the failure or failure point can be determined according to the result of such comparison.

Therefore, the present invention facilitates the determination as to whether the integrated circuit is properly implemented, whether the connection between the printed circuit boards with the integrated circuit is appropriate, etc., and the point of defect can be easily detected. Also, a decision regarding the state of the connection between circuits or devices in the device (such as a camera device) can be made while such a device is operating. As a result, normal operation of the device can be performed or continued during such a connection state determination.

Thus, according to the present invention, test pattern data having pulses whose timing or sequence arrangement is shifted in the above-described manner is generated on the transmission side or the circuit, and a plurality of signal lines are generated at a transmission rate substantially equivalent to that of other data. And discrimination pattern data having a pattern substantially the same as the test pattern data can be generated in synchronization with the test pattern data on the receiving side or the circuit, and such data is compared to determine the failure or failure point. . In addition, since the test pattern data can be supplied during image retrace data DAR, DAG, and DAB during horizontal retrace or retrace period having an optical black level VOPB, etc. Failures or points of failure that can occur during initial operation can be detected relatively quickly and without adversely affecting such operation. Further, by using the pulse information as the test pattern data, a determination can be made as to whether the image data or the like is properly transmitted or whether the signal line properly transmits the signal.

Although in the above description the invention has been described in terms of determining a fault or failure point between the video processing circuit and the signal processing circuit or connection of the VTR block, the invention is not limited thereto. That is, the present invention can be applied to determining a failure between devices or circuits such as any electrical or processing type apparatus.

Japanese Patent No. 4-258079 and the corresponding Japanese Patent Abstract No. 92-258097, Japanese Patent No. 4-245893 and the corresponding Japanese Patent Abstract No. 92-245893, Japanese Patent No. 4-281691 and the corresponding Japanese Patent Abstract No. 92 -281691, Japanese Patent No. 4-276839 and the corresponding Japanese Patent Abstract No. 92-276839 are incorporated herein by reference.

While the preferred embodiments of the present invention and variations thereof have been described herein, the present invention is not limited to these embodiments and variations, and may be modified without departing from the spirit and scope of the invention as defined by the appended claims. It will be understood that variations and modifications may be made by those skilled in the art.

1 is a perspective view of a video camera system.

2 is a side view of the video camera system of FIG.

3A is a block diagram of a camera block of the video camera system of FIG. 1.

3B is a partial block diagram of the video camera system of FIG. 1.

4 is a block diagram of a preprocessing circuit of the camera block of FIG. 3A.

5 is a block diagram of a processing circuit of the camera block of FIG. 3A.

6 is a block diagram of a jig for generating test pattern data.

7A-7I are timing diagrams for reference in describing the self-diagnosis operation.

8 is a block diagram of a test pattern generator.

9A-9T and 9A'-9T 'are referenced to illustrate the operation of the test pattern generator.

10 is a block diagram of a pulse generator.

11 is a diagram referred to for describing the operation of the test pattern generator.

12 is a block diagram of a pattern comparator.

Fig. 13 is a diagram of test pattern data EBB1, EBR1 and EBG1 supplied by a test pattern generator.

14 is a diagram of test pattern data EBB2, EBR2 and EBG2.

15 is a diagram of test pattern data EBB3, EBR3 and EBG3.

16 is a diagram of selected data POB to POBG.

※ Explanation of code about main part of drawing ※

15: signal selector 20: preprocessing circuit

21: camera block 22: VTR block

23, 39: pattern comparator 26, 41: discrimination pattern generator

27, 42: test pattern generator 30: processing circuit

76: microcomputer

Claims (24)

In a digital signal processing device: A data input unit for receiving digital image data including test pattern data during the vertical retrace period; A discrimination pattern generating unit for generating discrimination pattern data in synchronization with the test pattern data received by the data input unit; A pattern comparator for comparing the test pattern data with the discrimination pattern data; And And a self-diagnosing unit for detecting a faulty spot on a line for transmitting the digital image data, based on a comparison result by the pattern comparator. A signal processing device comprising a first device and a second device detachably connected to the first device, The first device, A test pattern generation unit for generating predetermined test pattern data inserted during a vertical retrace period of digital image data transmitted between the first device and the second device, The second device, A discrimination pattern generating unit for generating discrimination pattern data in synchronization with the test pattern data supplied from the first apparatus; A pattern comparator for comparing the test pattern data with the discrimination pattern data, and And a self-diagnostic unit for detecting a point of failure on a data transmission line between the first and second devices based on a comparison result by the pattern comparator. In the self-diagnosis method: Supplying digital image data including predetermined test pattern data from the first device to the second device during the vertical retrace period; Generating discrimination pattern data in synchronization with the test pattern data in the second device; And Comparing the test pattern data with the discrimination pattern data, and detecting a failure point on a data transmission line between the first device and the second device based on the comparison result. In an integrated circuit, A data input unit for receiving digital image data including test pattern data during the vertical retrace period; A discrimination pattern generating unit for generating discrimination pattern data in synchronization with the test pattern data received by the data input unit; A pattern comparator for comparing the test pattern data with the discrimination pattern data; And And a self-diagnostic unit for detecting a point of failure on a line for transmitting the digital image data based on a comparison result by the pattern comparator. A signal processing apparatus comprising a first integrated circuit and a second integrated circuit connected to the first integrated circuit, The first integrated circuit, A test pattern generation unit for generating predetermined test pattern data inserted during a vertical retrace period of digital image data transmitted between the first integrated circuit and the second integrated circuit; The second integrated circuit, A discrimination pattern generating unit for generating discrimination pattern data in synchronization with the test pattern data supplied from the first integrated circuit; A pattern comparator for comparing the test pattern data with the discrimination pattern data, and And a self-diagnostic unit for detecting a point of failure on the data transmission line between the first and second integrated circuits based on a comparison result by the pattern comparator. In the self-diagnosis method: Supplying digital image data including predetermined test pattern data from the first integrated circuit to the second integrated circuit during the vertical retrace period; Generating discrimination pattern data in synchronization with the test pattern data in the second integrated circuit; And Comparing the test pattern data with the determination pattern data, and detecting a failure point on a data transmission line between the first integrated circuit and the second integrated circuit based on the comparison result. In the apparatus for detecting a failure between a first unit and a second unit: First generating means for generating a first data pattern located in the first unit and inserted during a vertical retrace period of digital image data transmitted between the first unit and the second unit; Second generating means for generating a second data pattern located in the second unit and synchronous with the first data pattern supplied from the first unit; Comparison means for comparing the first and second data patterns; And Means for detecting a failure between the first and second units based on a comparison result by the comparing means. The method of claim 7, wherein And the first data pattern includes a plurality of data signals supplied in parallel to the second unit. The method of claim 8, Wherein each of the data signals of the first data pattern comprises a data pulse having a relatively high value and a data pulse having a relatively low value. The method of claim 8, And means for delaying the plurality of the data signals of the first data pattern. The method of claim 7, wherein And the first data pattern is supplied to the second unit for a predetermined period of time. The method of claim 11, Wherein the predetermined period is a horizontal blanking period. The method of claim 8, And the first and second units are first and second integrated circuits, respectively. The method of claim 8, And the first and second units are detachably connected. The method of claim 14, And the first and second units are included in a digital video camera. A method for detecting a fault between a first unit and a second unit, comprising: Supplying digital image data including a first data pattern from the first unit to the second unit during a vertical retrace period; Generating, in the second unit, a second data pattern in synchronization with the first data pattern supplied from the first unit; Comparing the first and second data patterns; And Detecting a failure between the first and second units based on the comparison result. The method of claim 16, And the first data pattern includes a plurality of data signals, and the plurality of data signals are supplied in parallel to the second unit. The method of claim 17, Wherein each of the data signals of the first data pattern comprises a data pulse having a relatively high value and a data pulse having a relatively low value. The method of claim 16, Delaying a plurality of said data signals of said first data pattern. The method of claim 16, And the first data pattern is supplied to the second unit for a predetermined period of time. The method of claim 20, And the predetermined period is a horizontal retrace period. The method of claim 16, And the first and second units are first and second integrated circuits, respectively. The method of claim 16, And the first and second units are detachably coupled. The method of claim 23, And the first and second units are included in a digital video camera.