JP3343914B2 - Video signal processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal processing apparatus suitable for use in a digital television camera or the like.

[0002]

2. Description of the Related Art As shown in FIG. 3, for example, a conventional television camera mainly comprises an imaging unit 10, a video signal processing unit 20, and a control unit 30. The output of the image pickup device (CCD) 11 of the image pickup unit 10 is converted into three primary color video signals of R, G, and B in the image pickup signal processing circuit 12 and supplied to the video signal processing unit 20.

The pre-processing circuit 2 of the video signal processing unit 20
In 1, the shading correction of the three primary color signals R, G, and B, the adjustment of the clip level, and the like are performed. The mask processing unit 22m of the process circuit 22 performs processes such as gamma correction and skin color adjustment in portrait photography. Is performed, and the image enhancer unit 22i performs signal processing such as contour enhancement. Further, a delay line 23 for contour enhancement or the like is connected between the pre-processing circuit 21 and the processing circuit 22. On the other hand, in the encoding circuit 24, a composite video signal, a so-called composite signal CMS, is converted from the three primary color signals R, G, and B subjected to the above-described process processing by a luminance signal processing unit 24y and a color signal processing unit 24c. Alternatively, the luminance signal Y and the color difference signals RY, B-
A so-called component signal composed of Y is formed.

The control unit 30 includes a control panel represented by a system control circuit 31 and operation keys 32, and a timing signal generation circuit 33 for generating various timing signals Sts and Stc of a synchronous system and a color synchronous system. The timing signals Sts and Stc correspond to the respective circuits 21 to 2 of the video signal processing unit 20.
3 respectively.

[0005]

In the above-described television camera, when a fine adjustment is required for analog signal processing, for example, gamma correction or portrait skin color adjustment, adjustment may be made if necessary. There is a problem that the state tends to vary, and the gradation and color tone of the reproduced image are slightly different for each camera.

In recent years, circuit technology and semiconductor technology have remarkably progressed, and it has become possible to digitize and integrate an image signal processing section as shown in FIG. This allows
By using several large-scale integrated circuits (LSIs) and storing adjustment data for each adjustment item in a memory (RAM) as described above, digital signal processing including adjustment processing becomes possible, and analog signal processing becomes possible. The above-mentioned problem of the variation in the adjustment state caused by the processing is almost eliminated.

Generally, an LSI equipped with each signal processing circuit
Are mounted on a test jig, and only those that pass a predetermined test are mounted on the printed wiring board. For example, a scan path test method is used for testing the LSI alone. In a test mode, input data appropriately set is supplied from the outside, and output data is observed to determine pass / fail.

In the test of the RAM, in a test mode, for example, a microprocessor is used to write appropriately set input data, and whether or not the written data can be read correctly is determined based on whether the RAM is good or bad. Is determined.

However, even when a digital video signal processing circuit as described above is formed by using a printed wiring board on which a tested LSI is mounted, for example, a bridge between wiring patterns by solder (so-called bridge) is used. In addition, a malfunction may occur due to various causes, such as poor contact of the connector, which must be actually operated, and the device may not operate normally. In particular, in the case of a RAM, there is a possibility that predetermined data for each adjustment item may be rewritten due to an operation error or the like while using the television camera.

When a failure occurs, it is necessary to examine the above-described video signal processing circuit one by one in order to find out the cause. However, since the digitization and the implementation of the LSI, the circuit configuration is complicated and minute. In addition, there arises a problem that it becomes more difficult to find a failure point.

In view of the above, an object of the present invention is to provide a memory for storing adjustment data corresponding to a predetermined processing item during the operation of a digitized video signal processing circuit.
It is an object of the present invention to provide a video signal processing device capable of performing a predetermined test and easily inventing a failed portion.

[0012]

The video signal processing apparatus according to the present invention includes a video signal processing section 210 for performing predetermined processing on an input digitized video signal, and a predetermined processing item of the video signal processing section 210. In a video signal processing apparatus having a memory 220 for storing corresponding adjustment data, memory check means 540 and 71 for checking the adjustment data stored in the memory 220 are provided, and during a vertical blanking period of the video signal, The correctness of the adjustment data is checked.

[0013]

According to the present invention, during the actual operation of the video signal processing, the correctness of the adjustment data is checked during the vertical blanking period of the video signal in the memory storing the adjustment data corresponding to the predetermined processing item. The fault location is easily found.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment in which a video signal processing apparatus according to the present invention is applied to a video signal processing section of a television camera will be described below with reference to FIGS. FIG. 2 shows an overall configuration of an embodiment of the present invention, and FIG. 1 shows a configuration of a main part. In FIG. 2, the portions corresponding to FIG. 3 described above are denoted by the same reference numerals, and redundant description will be omitted.

In FIG. 2, 100, 200, 300
Are LSIs, and the pre-processing circuit, the process circuit, and the encoding circuit described above are digitized and mounted. The digital pre-processing circuit 110 is connected to the imaging unit 10 via the AD converter 34.
For example, 10-bit parallel data corresponding to the three primary color signals R, G, and B from FIG. 3 is supplied. On the other hand, from the digital encoding circuit 310, D
Through the A-A converter 35, a composite signal CMS,
The component signals (Y, RY, BY) and the like are output, and the test signal TST is output in a predetermined test mode.
Is output.

A RAM 220 for the digital process circuit 210 is mounted on the LSI 200, and the RAM 1 for the pre-process circuit 110 has a relatively large capacity.
20 is provided outside the LSI 100. Note that control data is derived from the pre-processing circuit 110 to an input / output port (not shown).

The RAM 120 stores three primary color signals R, G, B
The data (table) corresponding to each adjustment item of the pre-processing circuit 110, such as shading correction and clip level adjustment, is stored, and the input / output data length is, for example, 8 bits. The RAM 220 stores data (table) corresponding to each adjustment item of the process circuit 210, such as gamma correction and skin color adjustment, and the input / output data length is, for example, 19 bits.

Reference numerals 400, 500, and 600 denote test circuits, which are a pre-process circuit 110, a process circuit 210,
Each of the LSIs 10 corresponds to the encoding circuit 310.
0, 200, and 300. Reference numeral 71 denotes a microprocessor (MPU) for diagnosis, which is connected to each of the test circuits 400, 500, and 600 via a bus 72.

Each test circuit 400, 500, 600
In cooperation with the diagnostic MPU 71, the pre-processing circuit 11
0, the inside of the process circuit 210, the inside of the encoding circuit 310, the peripheral circuits and between the circuits, and the supply pulse are each tested in the operation state of the predetermined mode.

The test functions of the test circuits 400, 500, and 600 are, for example, as follows. (1) Timing pulse detection (2) Circuit pattern check (EXT mode) (3) Check inside each LSI (SMP mode) (4) Check inside each LSI (INT mode) (5) Check each RAM , EXT mode and INT mode, a scan path test method is used.

Referring to FIG. 1, process circuit 210 and RA
Video data is exchanged with the M220 and the address from the address generator 221 is stored in the RAM 22.
0 is supplied. Reference numeral 540 denotes a checksum circuit for checking the adjustment processing data in the RAM 220, which is composed of a flip-flop 541, an adder 542, and a comparator 543.
It is connected to the output side of 220 and to the microprocessor 71 via the bus 72. From the timing signal generation circuit 33, the start signals Sad and S are sent to the address generator 221 and the checksum circuit 540, respectively.
channel is supplied, and the vertical blanking signal VBLK is
It is supplied to the gate 544 as a control signal.

Next, a RAM check operation according to an embodiment of the present invention will be described. When the television camera is in operation, by the vertical blanking signal VBLK, gate 544 becomes "open" state, that is the vertical blanking signal
During the vertical blanking period where the signal VBLK is present, the flip-flop 541 of the checksum circuit 540 is provided with the generator 221.
The data corresponding to the signal level in the vertical blanking period of the specific adjustment item such as gamma correction is supplied from the RAM 220 controlled to the address of the .gamma correction, and the output of the flip-flop 541 is supplied to the adder 542.

In the adder 542, the start signal S
Under the control of the channel, a cumulative value (checksum) corresponding to the data of the specific adjustment item is generated, and the checksum generated by the adder 542 is supplied to one input terminal of the comparator 543. The other input terminal of the comparator 543 is connected to the bus 7
2 through the adder 54 from the microprocessor 71.
The checksum of the data of the same adjustment item as the checksum generated in step 2 is supplied.

In the comparator 543, both checksums are compared, and the output of the comparator 543 becomes "0" when both checksums match. When the two checksums do not match, the comparator 543 outputs “1”.
Is output (the detection flag is set). This detection flag is supplied to the microprocessor 71 via the bus 72, and it is determined whether or not the data of the specific adjustment item stored in the RAM 220 is correct.

As a result, in this embodiment, during the operation of the digitized television camera, the correctness of the data corresponding to each adjustment item of the process circuit 210 stored in the memory 220 is checked, and the failure location is found. Becomes easier.

The embodiment in which the present invention is applied to the RAM 220 for the process circuit 210 of the television camera has been described above.
120 can be similarly applied.

[0027]

As described in detail above, according to the present invention,
In a video signal processing device comprising a video signal processing unit and a memory for storing adjustment data corresponding to a predetermined processing item, a memory check means for checking the adjustment data stored in the memory is provided, and a vertical blanking of the video signal is provided.
Since the correctness of the adjustment data is checked during the recording period, the self-diagnosis of the memory can be performed during the actual operation of the video signal processing, and the trouble spot can be easily found.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a main part of an embodiment of a video signal processing device according to the present invention.

FIG. 2 is a block diagram showing the overall configuration of an embodiment of the present invention.

FIG. 3 is a block diagram for explaining the present invention;

[Explanation of symbols]

33 Timing Signal Generation Circuit 71 Test Microprocessor 110, 210, 310 Digital Signal Processing Circuit 120, 220 RAM 400, 500, 600 Test Circuit 540 Checksum Circuit 542 Adder 543 Comparator

────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁷ Identification symbol FI H04N 17/00 H04N 17/00 K (56) References JP-A-2-232755 (JP, A) JP-A 1-2222356 ( JP, A) JP-A-1-207862 (JP, A) JP-A-55-45165 (JP, A) JP-A-2-14687 (JP, A) JP-A-61-195091 (JP, A) (58) ) Surveyed field (Int.Cl. ⁷ , DB name) G06F 12/16 330 G01R 31/02 G06F 11/10 310 G06F 11/22 350 H04N 5/232 H04N 17/00

Claims (1)

(57) [Claims] 1. A video signal comprising: a video signal processing unit for performing predetermined processing on an input digitized video signal; and a memory for storing adjustment data corresponding to predetermined processing items of the video signal processing unit. In the processing device, a memory check means for checking the adjustment data stored in the memory is provided, and during a vertical blanking period of the video signal, whether or not the adjustment data is correct is checked. Processing equipment.