JPH04225452A - Optical i/o interface - Google Patents

Abstract

PURPOSE:To omit the waiting time for the idle state of an I/O device and to improve the processing step efficiency by transferring the busy state of the I/O device to a host channel device from a less significant I/O controller by making use of the time of an idle packet on an optical I/O interface while the I/O device designated by the host channel device is kept in a busy state by another host CPU. CONSTITUTION:An optical I/O interface whose transmission line consists of an optical fiber is provided together With a host channel device which is connected to the optical I/O interface and also to a host CPU, a less significant I/O controller which is connected to the host channel device via the optical I/O interface, and at least an I/O device which is connected to the less significant I/O controller. The host channel device always refers to a device state display packet and gives a command to the less significant I/O controller when the display packet is switched to a free state.

Description

[Detailed description of the invention]

0001

[Field of Industrial Application] The present invention relates to an optical I/O interface whose transmission line is an optical fiber, and in particular to an optical I/O interface.
Upper channel device and lower I/O at the interface
It relates to an information transmission protocol for a control device. External interfaces in large computer systems, especially data transfer between external storage devices, are always required to be faster. For this reason, instead of the conventional method that uses electrical signals as a means of information transmission (hereinafter referred to as electrical I/O interface), an interface that uses optical transmission that can transfer high-speed data (optical I/O interface) has become popular. It is starting to be used. On the other hand, in recent years, large computer systems are equipped with multiple CPUs due to performance or reliability considerations.
A multi-configuration is often adopted in which two are connected.

0002

2. Description of the Related Art FIG. 7 is a general configuration diagram of an optical I/O interface system. In the figure, 701-A and 7
01-B is the host CPU, 702-A and 702-
B is an upper channel device connected to each CPU, 703
-A and 703-B are lower I/O control devices, 704
-1 to 704-N are I/O devices, 705-A,
705-B, 706-A, 706-B are optical I/O interfaces, and 707-A, 707-B are I/O device interfaces. Here, 705-A and 705-B are optical I/O interfaces that transmit information from the upper channel device to the lower I/O control device, and 706-A and 706-B are optical I/O interfaces that transmit information from the lower I/O control device to the upper channel device. It is.

FIG. 8 is a schematic diagram of a packet sent out on an optical I/O interface. One packet is, for example, a free packet, a command packet, a data packet, or the like. The arrows indicate the direction of information transmission, indicating that packets are sent out sequentially starting from the left side in time. Light I with such a configuration
/O interface system, the host CPU
When 701-A or 701-B needs to access an I/O device such as an external storage device due to a request from a user program, the upper channel device 702-B
A or 702-B is requested to issue a command. For example, upon receiving a command issuance request from the host CPU, the upper channel device 702-A issues the command and requests write data via the optical I/O interface 705-A. On the other hand, the lower I/O control device 703-A transfers the execution result status and read data to the upper channel device 702-A via the optical I/O interface 706-A. During actual data transmission and reception, the lower I/O control device communicates with any of the I/O devices 704-1 to 704-N via the device interface 707-A.

FIGS. 9 and 10 show packet transitions when a write command is executed on a conventional optical I/O interface. Figure 9 shows the case where the specified I/O device is available (free state), and Figure 10 shows the case where the specified I/O device is available (free state).
This is the case when the /O device is busy. First, in FIG. 9, the upper stage is the optical I/O interface 705-A or 70 from the upper channel device to the lower I/O control device.
5-B The state of the upper packet, the lower row is the lower I/O
The state of the packet on the optical I/O interface 706-A or 706-B from the device to the upper channel device is shown.

When the lower I/O control unit recognizes the write command issued from the upper channel device, it checks the busy state of the specified I/O device and determines if it is available. For example, a status indicating that the device can be used is notified to the upper channel device, and subsequently, when the upper channel device receives this status, it sends data to the lower I/O control. When the data transfer ends normally, the lower I/O control device notifies the upper channel device of a status indicating normal completion, thereby completing a series of processes related to the write command requested by the upper channel device.

Next, as mentioned above, FIG. 9 shows an example of the operation when the target I/O device is available at the time the upper channel device issues the command, but FIG. This is a protocol when the I/O device is in use (busy state) by another host CPU. In FIG. 10, 1 from the upper channel device to the lower I/O control device
When the second write command is issued, the lower I/O control device returns a device busy status to the upper channel device, and the upper channel device releases the I/O device from being used by other host CPUs. At that point, it waits until it receives a device free status from the lower I/O control device, and then issues the write command again.

[0007]

[Problems to be Solved by the Invention] In the conventional optical I/O interface, the I/O
In order for upper channel equipment to know the status of the device, optical I
The use of the /O interface still requires invoking protocols with commands and corresponding statuses similar to traditional electrical I/O interfaces. I/O devices connected to a host CPU via such an optical I/O interface are generally connected to multiple host CPUs via multiple lower I/O control devices, and when a certain host CPU is using an I/O device, commands issued by other host CPUs to use the I/O device will be returned with a busy status (busy status), and other It was necessary to wait until the host CPU finished using it.

That is, as shown in FIG. 10, when an I/O device specified by an upper channel device is in a busy state, the I/O device is released from use by another host CPU and is used for lower I/O control. You must wait until you receive a device-free status from the device and issue the write command again. Therefore, the three processing steps from issuing a command to reporting a busy status and reporting a free status are useless processing steps.

An object of the present invention is to utilize the time of empty packets on the optical I/O interface when an I/O device specified by an upper channel device is in a busy state by another host CPU. The purpose of this method is to transfer the busy state of the /O device from the lower I/O control device to the upper channel device, thereby eliminating the waiting time for waiting for an I/O device to become available and improving the efficiency of processing steps. shall be.

0010

[Means for Solving the Problem] FIG. 1 shows an optical I/O of the present invention.
This is the basic protocol of the interface. The present invention provides an optical I/O interface 70 whose transmission line is an optical fiber.
5,706, an upper channel device 702 connected to the optical I/O interface and connected to the host CPU 701, and a lower I/O control device connected to the upper channel device via the optical I/O interface. device 70
3 and at least one I/O device 704 connected to the lower I/O control device.
In multi-system using O interface,
At the time of an empty packet on the optical I/O interface,
A device status display packet indicating the busy state or free state of the I/O device is sent, and the upper channel device always refers to the device status display packet and when the device switches to the free state, the lower I/O The lower I/O control device is characterized by issuing a command to a control device, and the lower I/O control device is provided with a device state sequential notification means, and the device state sequential notification means includes a general data transmission circuit 201 that transmits normal data. , a device status holding register 202 that holds the status of an I/O device, and a multiplexer 204 that switches these, the multiplexer is switched by a switching signal, and the upper channel device has internal device status sequential detection means, and The device state sequential detection means includes a general data receiving circuit 304 that receives normal data, a device state holding register 306 that holds the state of the I/O device, and a packet decoder circuit 305 that switches these. These are switched by the output of .

[0011]

[Operation] In the present invention, by utilizing the free packet time of the optical I/O interface connected between the upper channel device and the lower I/O control device, the I/O The busy state of the device is notified from the lower I/O control device to the upper channel device.

0012

[Example] FIG. 2 shows lower I/O control devices 703-A, 70
3-B is an I/O device status sequential notification means provided within the device. As shown, general data transmission circuit 201
, an I/O device status holding register 202 , and a multiplexer 204 for switching these. When performing normal status notification, read data transfer, etc., the multiplexer 204 selects the output of the general data transmission circuit 201 using a changeover switch 203 . . Therefore, the data consisting of multiple bits output by the general data transmission circuit 201 is transferred to the parallel/serial converter 20.
5 into serial data, the signal is converted into an optical signal by an electrical-to-optical converter 206, and sent to an optical fiber 207, which is an optical I/O interface. Optical fiber 207 connects to a data receiving port (not shown) of the upper channel device.

Next, the changeover switch 203 is switched to switch the output of the multiplexer 204 to the I/O device status holding register 202 side, and the I/O is connected to the optical fiber.
Sends the contents of the O device status holding register 202. This data is called a device status packet to distinguish it from general packet data. FIG. 3 shows I/O device sequential detection means provided in the upper channel device. The input side is connected to an optical fiber 301, and the optical input signal is converted into an electrical signal by an optical-to-electrical converter 303, and further converted into parallel data by a serial-to-parallel converter 302, and sent to the internal bus as multi-bit data. 3
Output on 08. A general data receiving circuit 304, an I/O device state holding circuit 306, and a packet decoder circuit 305 are connected to the internal bus. When the packet data transmitted from the lower I/O control device is status or read data, the switching signal 307 output from the packet data circuit 305 selects the general data receiving circuit 304, and the received packet is sent to the general data receiving circuit 304. Processed by

On the other hand, when the received packet is a device status packet, the switching signal 307 selects the I/O device status holding register 306, and the contents of the received packet are
/O is held in the device status holding register 306. Figure 4 shows the I/O in the optical I/O interface of the present invention.
FIG. 3 is an explanatory diagram of the state of packets when the device is in a busy state. First, on the optical I/O interface from the lower I/O control device to the upper channel device in the lower stage, in addition to packets for status reporting, the status of the I/O devices under the lower I/O control device is transmitted. A packet indicating a busy or free state is sent out. As mentioned above, these packets are created by the device status sequential notification means in the lower I/O control device (see FIG.
(see Figure 3) and is captured in the device status holding register by the device status sequential detection means in the upper channel device (see Figure 3).
), and can be sequentially referenced by the upper channel device.

As shown in FIG. 4, when an upper channel device receives a command issue instruction from the host CPU, it refers to the device state holding register in its own device and determines the target I/O.
Detects that an /O device is busy without issuing a command, and indicates that the I/O device is busy.
At the same time as switching from status to free status, a write command is issued to perform subsequent data transfer.

FIG. 5 shows busy packets or free packets.
FIG. 3 is a detailed configuration diagram of a device status display packet. The usage status of all I/O devices connected under the lower I/O control device is stored in bits in the packet, and in this example, an I/O device in a busy state is set to "1". , an I/O device in a free state is represented as "0". Therefore, in the diagram, I/O device No. 0 is in a free state, that is, in a usable state, and I/O device No. 1 is in a busy state, that is, in a state in use.
Device No. N is in a free state.

FIG. 6 shows a processing flowchart in the upper channel device. The upper channel device checks whether there is a command issue request from the host CPU (step 1), and if so, recognizes the command (step 2).
). Next, it is checked whether this command has been sent to the lower I/O control device (step 3), and if it has been sent, all subordinate I/O devices are set to "0" indicating a free state. A search is made to find out whether or not (step 4). Furthermore, it is checked whether there is a recognized but unissued command to the target I/O device (step 5), and if there is, the device status flag of the I/O device is checked to see if it is in the busy state. Check it (step 6), and if it is free, issue a command to the lower I/O control device (
Step 7), and increment the I/O device number (Step 8). Furthermore, it is checked whether processing has been performed for all I/O devices N (step 9). If no command has been sent in step 5, the I/O device number is incremented in step 8.

[0018]

[Effects of the Invention] As explained above, according to the present invention,
By storing the usage status of I/O devices in unused empty packets in conventional optical I/O interfaces, commands can be saved without actually issuing commands from the upper channel device to the lower I/O control device. Since the upper channel device can detect the usage status of the target I/O device, the processing that occurs when the relevant I/O device is in use by another host CPU, i.e., command issuance → busy status report →It is now possible to omit the three processing steps of free status reporting, reducing the burden on the upper channel device and lower I/O control device,
It is possible to speed up command processing.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram of a basic protocol of an optical I/O interface of the present invention.

FIG. 2 is a configuration diagram of device status sequential notification means of the present invention.

FIG. 3 is a configuration diagram of device state sequential detection means of the present invention.

FIG. 4 is an example protocol of the optical I/O interface of the present invention.

FIG. 5 is a detailed diagram of a device status indication packet of the present invention.

FIG. 6 is a processing flowchart of the upper channel device of the present invention.

FIG. 7 is a configuration diagram of a multi-system using an optical I/O interface.

FIG. 8 is a schematic diagram of a packet on a general optical I/O interface.

FIG. 9 is an explanatory diagram of an example of a packet on a conventional optical I/O interface.

FIG. 10 is an explanatory diagram of another example of a packet on a conventional optical I/O interface.

[Explanation of symbols]

201...General data transmission circuit 202...Device status holding register 203...Selector switch 204...Multiplexer 304...General data receiving circuit 305...Packet data circuit 306...Device status holding register 701...Host CPU 702...Upper channel device 703...lower I/O control device 704...I/O device

Claims (3)

[Claims] [Claim 1] Optical I/O whose transmission path is an optical fiber.
an upper channel device connected to the optical I/O interface and connected to the host CPU; a lower I/O control device connected to the upper channel device via the optical I/O interface; In a multi-system using an optical I/O interface configured by at least one I/O device connected to the lower I/O control device, when there is an empty packet on the optical I/O interface, A device status display packet indicating the busy state or free state of the I/O device is sent out, and the upper channel device always refers to the device status display packet and controls the lower I/O when the device switches to the free state. An optical I/O interface characterized by issuing commands to devices. 2. Device state sequential notification means is provided in the lower I/O control device, and the device state sequential notification means includes a general data transmission circuit that transmits normal data, and an I/O control device.
2. The optical I/O interface according to claim 1, further comprising a device state holding register for holding the state of the O device and a multiplexer for switching between these registers, the multiplexer being switched by a switching signal. 3. Device state sequential detection means is provided in the upper channel device, and the device state sequential detection means comprises:
A general data receiving circuit that receives normal data and an I/O
2. The optical I/O interface according to claim 1, further comprising a device state holding register for holding the state of the device and a packet decoder circuit for switching between these registers, and switching between these by an output of the packet decoder circuit.