JPH04189087A - High definition television receiver - Google Patents

High definition television receiver

Info

Publication number
JPH04189087A
JPH04189087A JP2318475A JP31847590A JPH04189087A JP H04189087 A JPH04189087 A JP H04189087A JP 2318475 A JP2318475 A JP 2318475A JP 31847590 A JP31847590 A JP 31847590A JP H04189087 A JPH04189087 A JP H04189087A
Authority
JP
Japan
Prior art keywords
circuit
signal
video
synchronizing signal
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2318475A
Other languages
Japanese (ja)
Inventor
Toshihiro Miyoshi
敏博 三好
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP2318475A priority Critical patent/JPH04189087A/en
Publication of JPH04189087A publication Critical patent/JPH04189087A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To display a video signal without disturbance even when no synchronizing signal exists by providing a circuit selecting a synchronizing signal detection circuit and a video signal generating circuit and switching the circuits automatically. CONSTITUTION:A changeover circuit 9 switches the output of a video amplifier circuit 3 or the output of a video signal generating circuit 8 based on the output of a synchronizing signal detection circuit 7 and sends the result to a high definition display device 6. The circuit 7 detects the presence of a synchronizing signal and when no synchronizing signal exists, the synchronizing signal generated from a deflection circuit 5 is inputted to the circuit 8, its output is switched by the circuit 9 and a video image is displayed. In this case, the deflection circuit 5 uses a horizontal synchronizing signal and a vertical synchronizing signal outputted from a synchronization processing circuit 4 to take synchronization for horizontal and vertical deflection and generates a synchronizing signal. Thus, even in the absence of the synchronizing signal, the synchronizing signal generated from the circuit 5 is used to display a video image.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、高品位テレビジボン(ハイビジラン)受信装
置に関するものである。
DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a high-definition television receiver.

従来の技術 高品位テレビ(ハイビジョン)は、きめ細かなテレビ画
像を大画面のワイドスクリーンに表示することにより現
行のテレビ放送では得られない迫力とHp場感などの新
しい魅力を求めようとするもので、近年各国とも関心が
高まってきている。この高品位テレビは、現行標準テレ
ビの方式が走査線525本、アスペクト比4:3である
のに対し、走査11125本、アスペクト比16:9で
ある。しかし、高品位テレビでは、現行標準テレビに急
激にとって変わるものではなく、両方のテレビ方式が共
存していくものと考えられる。このとき、高品位テレビ
ジョン受信袋!でも現行標準テレビの画像を受信・再生
する必要がある。
Conventional technology High-definition television (hi-vision) aims to display detailed television images on a large wide screen to provide new appeal, such as the power and sense of place that cannot be obtained with current television broadcasting. In recent years, interest has been increasing in all countries. This high-definition television has 11,125 scanning lines and an aspect ratio of 16:9, whereas the current standard television system has 525 scanning lines and an aspect ratio of 4:3. However, high-definition television will not suddenly replace the current standard television, and it is thought that both television systems will coexist. At this time, high-definition television reception bag! However, it is necessary to receive and play back images from current standard televisions.

以下、図面を参照しながら上述した従来の高品位テレビ
ジョン受信装置の一例について説明する。
An example of the above-mentioned conventional high-definition television receiving device will be described below with reference to the drawings.

第3図は、従来の高品位テレビジョン受信装置の構成を
示すブロック図である。第3図において、1はハイビジ
ョン映像信号(G、B、RもしくはY、Pb、Pr)を
入力するハイビジョン映像入力端子、2はハイビジョン
同期信号(HD、VD)を入力するハイビジョン同期入
力端子、3は前述のハイビジョン映像信号を増幅する映
像増幅回路、4は同期処理を行う同期回路、5は水平、
垂直の偏向を行う偏向回路、6は前述の映像増幅回路3
の出力を映出するアスペクト比16:9の高品位ディス
プレイである。
FIG. 3 is a block diagram showing the configuration of a conventional high-definition television receiver. In FIG. 3, 1 is a high-definition video input terminal for inputting a high-definition video signal (G, B, R or Y, Pb, Pr), 2 is a high-definition synchronization input terminal for inputting a high-definition synchronization signal (HD, VD), and 3 is a video amplification circuit that amplifies the aforementioned high-definition video signal, 4 is a synchronization circuit that performs synchronization processing, 5 is a horizontal
A deflection circuit that performs vertical deflection; 6 is the aforementioned video amplification circuit 3;
It is a high-quality display with a 16:9 aspect ratio that displays the output of

以−トのように構成された高品位テレビジョン受信装置
について、以下その動作について説明する。
The operation of the high-definition television receiving apparatus configured as described above will be explained below.

ハイビジョン映像入力端子1よりハイビジョン映像信号
(G、B、RもしくはY、Pb、Pr)が入力される。
A high-definition video signal (G, B, R or Y, Pb, Pr) is input from a high-definition video input terminal 1 .

また、ハイビジョン同期入力端子2よりハイビジョン同
期信号(HD、VD)が入力される。同期処理回路4で
は前述の入力端子2より同期信号が、映像増幅回路3よ
り映像信号がおのおの入力されるや同期信号が映像信号
に付加されている場合は映像信号より同期分路を行い、
水平信号(HD)、垂直信号(VD)を映像増幅回路3
、偏向回路5に出力する。映像増幅回路3では、前述の
ハイビジョン映像信号(G、B、R)を水平信号でクラ
ンプをかけ、コントラスト、ブライト調整した後、増幅
し出力する。偏向回路5では、前述同期処理回路4より
出力される水平信号、垂直信号よりそれぞれ水平偏向、
垂直偏向の同期をとり高品位ディスプレイ6に前述の映
像増幅回路3の出力を映出する。
Furthermore, a high-definition synchronization signal (HD, VD) is input from the high-definition synchronization input terminal 2 . The synchronization processing circuit 4 receives a synchronization signal from the input terminal 2 and a video signal from the video amplification circuit 3, and if the synchronization signal is added to the video signal, performs synchronization shunting from the video signal.
The horizontal signal (HD) and vertical signal (VD) are sent to the video amplification circuit 3.
, is output to the deflection circuit 5. The video amplification circuit 3 clamps the aforementioned high-definition video signals (G, B, R) with a horizontal signal, adjusts contrast and brightness, and then amplifies and outputs the signal. The deflection circuit 5 calculates horizontal deflection and vertical deflection from the horizontal and vertical signals output from the synchronization processing circuit 4, respectively.
The vertical deflection is synchronized and the output of the video amplification circuit 3 described above is displayed on a high-quality display 6.

発明が解決しようとする課題 しかしながら、前記のような構成では、映像(3号、同
期信号とも信号がない場合、映像が何も映出されないわ
けであるが、その原因が入力信号がないためか、ハイビ
ジョン受信装置が故障しているためなのかわからない。
Problem to be Solved by the Invention However, with the above configuration, if there is no video signal (No. 3, synchronization signal), no video is displayed. , I don't know if it's because the high-definition receiver is malfunctioning.

また、映像信号は正常だが同期信号がない場合や同期信
号のレベルが不正規の場合は乱れた映像が映出されてし
まうという課題があった。
Further, there is a problem in that, although the video signal is normal, if there is no synchronization signal or the level of the synchronization signal is irregular, a distorted video will be displayed.

本発明は、同期信号がなかった場合でも映像信号を出力
し、映像が何も映出されないことや乱れた映像が映出さ
れてしまうことを防いだものである。
The present invention outputs a video signal even when there is no synchronization signal, and prevents no video from being displayed or a distorted video from being displayed.

課題を解決するための手段 −J二記問題点を解決するため、本発明は、同期信号検
出回路と、特定の映像信号を出力する映像信号発生回路
と、切り換え回路を設け、同期信号がない場合、特定の
映像信号を発生させるという構成を備えたものである。
Means for Solving the Problems - In order to solve the problem described in J.2, the present invention provides a synchronization signal detection circuit, a video signal generation circuit that outputs a specific video signal, and a switching circuit, so that when there is no synchronization signal, In this case, the device is configured to generate a specific video signal.

作用 本発明は、前記した構成により、同期信号検出回路で同
期信号の有無を検出し、同期信号がない場合は、偏向回
路より発生する同期信号を映像信号発生回路に入力し、
映像信号発生回路の出力を切り換え回路で切り換え、映
像を映出する。
Effect of the present invention With the above-described configuration, the synchronization signal detection circuit detects the presence or absence of a synchronization signal, and if there is no synchronization signal, inputs the synchronization signal generated from the deflection circuit to the video signal generation circuit,
A switching circuit switches the output of the video signal generation circuit to display the video.

実施例 以下本発明の一実施例の高品位テレビジョン受信装置に
ついて図面を参照しながら説明する。
Embodiment Hereinafter, a high-definition television receiving apparatus according to an embodiment of the present invention will be described with reference to the drawings.

第1図は、本発明の一実施例における高品位テレビジョ
ン受信装置の構成を示すブロック図、第2図は、同期信
号検出回路の動作説明図である。
FIG. 1 is a block diagram showing the configuration of a high-definition television receiver according to an embodiment of the present invention, and FIG. 2 is an explanatory diagram of the operation of a synchronization signal detection circuit.

第1図において、1はハイビジョン映像信号(G。In FIG. 1, 1 is a high-definition video signal (G.

B、RもしくはY、、Pb、Pr)を入力するハイビジ
ョン映像入力端子、2はハイビジョン同期信号(HD、
VD)を入力するハイビジジン同期入力端子、3は前述
のハイビジョン映像信号を増幅する映像増幅回路、4は
同期処理を行う同期処理回路、5は水平、垂直の偏向を
行う偏向回路、6は前述の映像増幅回路3の出力を映出
するアスベク[比16:9の高品位ディスプレイ、7は
同期信号の有無を検出する同期信号検出回路、8は特定
の映像信号を発生する映像信号発生回路、9は前述の映
像増幅回路3の出力と映像信号発生回路8の出力を同期
信号検出回路7の出力に基いて切り換える切り換え回路
である。
2 is a high-definition video input terminal for inputting B, R or Y, , Pb, Pr), and 2 is a high-definition synchronizing signal (HD,
3 is a video amplification circuit that amplifies the above-mentioned high-definition video signal, 4 is a synchronization processing circuit that performs synchronization processing, 5 is a deflection circuit that performs horizontal and vertical deflection, and 6 is the above-mentioned deflection circuit. 7 is a synchronization signal detection circuit that detects the presence or absence of a synchronization signal; 8 is a video signal generation circuit that generates a specific video signal; 9 is a switching circuit that switches between the output of the video amplification circuit 3 and the output of the video signal generation circuit 8 based on the output of the synchronization signal detection circuit 7.

」二記のように構成された高品位テレビジョン受信装置
について以下、第1図、第2図を用いてその動作につい
て説明する。ハイビジョン映像入力端子1よりハイビジ
ョン映像信号(G、B、RもしくはY、Pb、Pr)が
入力される。また、ハイビジジン同期入力端子2よりハ
イビジョン同期信号(HD、VD)が入力される。同期
処理回路4では前述の入力端子2より同期信号が、吠像
増幅回路3より映像信号が入力される。同期信号が映像
信号に付加されている場合は映像信号より同期分離を行
い、水平信号DAD)、垂直信号(VD)を映像増幅回
路3、偏向回路5、同期信号検出回路7に出力する。映
像増幅回路3では、前述の入力ハイビジョン映像信号(
G、B、R)を水平信号(HD )でクランプをかけ、
コントラスト、ブライト調整した後、増幅し出力する。
The operation of the high-definition television receiving apparatus configured as described in Section 2 will be described below with reference to FIGS. 1 and 2. A high-definition video signal (G, B, R or Y, Pb, Pr) is input from a high-definition video input terminal 1 . Furthermore, a high-definition synchronization signal (HD, VD) is inputted from the high-vision synchronization input terminal 2. In the synchronization processing circuit 4, a synchronization signal is inputted from the input terminal 2 described above, and a video signal is inputted from the image amplification circuit 3. If a synchronization signal is added to the video signal, the synchronization signal is separated from the video signal, and a horizontal signal (DAD) and a vertical signal (VD) are output to the video amplification circuit 3, deflection circuit 5, and synchronization signal detection circuit 7. The video amplification circuit 3 receives the input high-definition video signal (
G, B, R) with a horizontal signal (HD),
After adjusting contrast and brightness, amplify and output.

同期信号検出回路7では、前述の同期処理回路4の出力
である同期信号(たとえば、水平信号)が入力される。
The synchronization signal detection circuit 7 receives a synchronization signal (for example, a horizontal signal) that is the output of the synchronization processing circuit 4 described above.

同期信号検出回路7は、第2図(a)のようにリトリガ
ブルのモノマルチバイブレークで構成される。このモノ
マルチバイブレータに第2図(b)のように前述の同期
処理回路4の出力である同期信号(たとえば、水平信号
)が入力される。リトリガブルのモノマルチバイブレー
クは出力信号であるリトリガブルスの幅がIOH(10
水平期間)になるよう抵抗、コンデンサの値を決めてい
る。したがって、第2図(C)のように入力信号の負パ
ルスの立ち下がりより】ohu間の正パルスを出力し、
入力信号の負パルス(J(D)がIOH期間連続してな
ければ、負パルスを出力する。偏向回路5では、前述同
期処理回路4より出力される水平信号、垂直信号よりそ
れぞれ水平偏向、垂直偏向の同期をとり偏向信号を出力
するが、水平信号もしくは垂直信号あるいは両方ない場
合は、内部の発振回路よりフリーランの水平信号、垂直
信号、偏向信号が出力される。1!ItV像信号発生回
路8では、前述の偏向回路5の出力である水平信号、垂
直信号で同期を取り特定の映像信号を発生する。切り換
え回路9では、前述の同期信号検出回路7の出力である
検出信号がHi(同期信号が有り)の場合、前述の映像
増幅回路3の出力を選択し、検出信号がLow(同期信
号が無し)の場合、前述の映像信号発生回路8の出力を
選択する。高品位ディスプレイ6は前述の切り換え回路
9の出力を映出する。
The synchronization signal detection circuit 7 is constructed of a retriggerable mono-multi-by-break circuit as shown in FIG. 2(a). As shown in FIG. 2(b), a synchronization signal (for example, a horizontal signal) which is the output of the synchronization processing circuit 4 described above is input to this mono-multivibrator. In the retriggerable mono multi-bi break, the width of the output signal, the retriggerable signal, is IOH (10
The values of the resistors and capacitors are determined so that the horizontal period) is achieved. Therefore, as shown in FIG. 2(C), from the falling edge of the negative pulse of the input signal, a positive pulse between ]ohu is output,
If the negative pulse (J(D)) of the input signal is not continuous during the IOH period, a negative pulse is output. The deflection is synchronized and a deflection signal is output, but if there is no horizontal signal, vertical signal, or both, a free-running horizontal signal, vertical signal, and deflection signal are output from the internal oscillation circuit. 1! ItV image signal generation In the circuit 8, a specific video signal is generated by synchronizing with the horizontal signal and vertical signal which are the outputs of the deflection circuit 5 described above.In the switching circuit 9, the detection signal which is the output of the synchronization signal detection circuit 7 described above is set to Hi. If the detection signal is low (there is a synchronization signal), the output of the video amplification circuit 3 described above is selected, and if the detection signal is Low (there is no synchronization signal), the output of the video signal generation circuit 8 described above is selected.High quality display 6 displays the output of the switching circuit 9 mentioned above.

以上のように、本実施例によれば、同期信号検出回路7
と映像信号発生回路8と切り換え回路9を設け、同期信
号がない場合は、前記映像信号発生回路8より出力する
特定の映像信号を映出させ、映像が何も映出されないこ
とや乱れた映像が映出されてしまうことを防ぐ事ができ
る。
As described above, according to this embodiment, the synchronization signal detection circuit 7
A video signal generation circuit 8 and a switching circuit 9 are provided, and when there is no synchronization signal, a specific video signal output from the video signal generation circuit 8 is displayed, so that no video is displayed or a distorted video is displayed. can be prevented from being displayed.

発明の効果 以上のように、本発明によれば、同期信号検出回路と映
像信号発生回路と切り換え回路を設ける事により、同期
信号がない場合でも、自動的に信号を切り換え特定の映
像信号を高品位ディスプレイ6に映出させることができ
る。
Effects of the Invention As described above, according to the present invention, by providing a synchronization signal detection circuit, a video signal generation circuit, and a switching circuit, even when there is no synchronization signal, the signal can be automatically switched and a specific video signal can be increased. It can be displayed on the quality display 6.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例における高品位テレビジョン
受信装置の構成を示すブロック図、第2図(a)、 (
b)、 (C)は周期検出回路の動作説明用の回路図お
よび波形図、第3図は従来の高品位テレビジョン受信装
置の構成を示すブロック図である。 1・・・・・・ハイビジョン映像入力端子、2・・・・
・・ハイビジョン同期入力端子、3・・・・・・映像増
幅回路、4・・・・・・同期処理回路、5・・・・・・
偏向回路、6・・・・・・高品位ディスプレイ、7・・
・・・・同期信号検出回路、8・・・・・・映像信号発
生回路、9・・・・・・切り換え回路。
FIG. 1 is a block diagram showing the configuration of a high-definition television receiver according to an embodiment of the present invention, and FIG.
b) and (C) are a circuit diagram and a waveform diagram for explaining the operation of the period detection circuit, and FIG. 3 is a block diagram showing the configuration of a conventional high-definition television receiver. 1...High-definition video input terminal, 2...
...High-definition synchronization input terminal, 3...Video amplification circuit, 4...Synchronization processing circuit, 5...
Deflection circuit, 6...High quality display, 7...
... Synchronization signal detection circuit, 8 ... Video signal generation circuit, 9 ... Switching circuit.

Claims (1)

【特許請求の範囲】[Claims] 高品位テレビジョン方式の信号を入力し、映像信号を増
幅する映像信号増幅回路と、前記高品位テレビジョン方
式の信号を入力し、同期分離を行う同期処理回路と、同
期信号を入力して偏向信号を発生する偏向回路と、特定
の映像信号を発生する映像信号発生回路と、前記同期処
理回路より出力される同期信号の有無を検出する同期信
号検出回路と、前述の映像信号増幅回路の出力信号と前
述の映像信号発生回路の出力信号を切り換える切り換え
回路とを備え、同期信号検出回路の出力である検出信号
により同期信号が無い場合は特定の映像信号を高品位デ
ィスプレイに映出するようにした高品位テレビジョン受
信装置。
A video signal amplification circuit that inputs a high-definition television system signal and amplifies the video signal; a synchronization processing circuit that inputs the high-definition television system signal and performs synchronous separation; and a synchronization processing circuit that inputs a synchronization signal and performs deflection. A deflection circuit that generates a signal, a video signal generation circuit that generates a specific video signal, a synchronization signal detection circuit that detects the presence or absence of a synchronization signal output from the synchronization processing circuit, and the output of the video signal amplification circuit described above. It is equipped with a switching circuit that switches between the signal and the output signal of the video signal generation circuit described above, and when there is no synchronization signal, a specific video signal is displayed on a high-quality display using the detection signal that is the output of the synchronization signal detection circuit. High-definition television receiver.
JP2318475A 1990-11-22 1990-11-22 High definition television receiver Pending JPH04189087A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2318475A JPH04189087A (en) 1990-11-22 1990-11-22 High definition television receiver

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2318475A JPH04189087A (en) 1990-11-22 1990-11-22 High definition television receiver

Publications (1)

Publication Number Publication Date
JPH04189087A true JPH04189087A (en) 1992-07-07

Family

ID=18099530

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2318475A Pending JPH04189087A (en) 1990-11-22 1990-11-22 High definition television receiver

Country Status (1)

Country Link
JP (1) JPH04189087A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
USRE40396E1 (en) 1996-06-21 2008-06-24 Samsung Electronics Co., Ltd. Method for detecting and separating vertical and horizonal synchronous signals from computer system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
USRE40396E1 (en) 1996-06-21 2008-06-24 Samsung Electronics Co., Ltd. Method for detecting and separating vertical and horizonal synchronous signals from computer system

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