JP3016664B2 - Synchronous signal processing circuit for video display device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit for stably generating a synchronizing signal of a moving image display device for receiving and displaying a moving image radio wave radiated in the air based on the NTSC system while moving. .

[0002]

2. Description of the Related Art Generally, as shown in the configuration of FIG. 6, a video receiving apparatus receives a video radio wave caught by an antenna 61 as an input signal, selects a desired channel of a broadcasting station by a high frequency amplifying section 62, and selects a high frequency signal. The component is amplified, and the frequency conversion unit 63 performs frequency conversion so that the same video intermediate frequency is obtained regardless of which channel of the broadcast station is received.

The output signal converted from the high frequency to the intermediate frequency is amplified with a high gain by a video intermediate frequency amplifying section 64, and a video signal carrier / audio signal carrier / color signal sub-carrier ( (Hereinafter abbreviated as “color sub-carrier”), and the first video amplifier 66 amplifies the composite video signal I.

The composite video signal I thus demodulated and amplified is separated into a synchronization signal by a synchronization signal separation section 67. The synchronization signal is further divided into a horizontal synchronization signal H and a vertical synchronization signal V.
Is separated into

The separated horizontal synchronizing signal H is supplied to a color CRT 80 (hereinafter referred to as “C
RT80], which oscillates a square wave Fh necessary for the scanning line to move left and right in synchronization with the horizontal synchronization signal H.

The square wave Fh which oscillates horizontally is amplified by a horizontal deflection output unit 69 and supplied to a horizontal deflection coil 79. Further, by using a part of the output signal of the horizontal deflection output unit 69, the high voltage
A high voltage of tens of thousands V is efficiently generated and supplied to the anode of the CRT 80.

At the same time, the vertical synchronizing signal V separated by the synchronizing signal separating section 67 is
A square wave Fv, which is necessary for the scanning line of the RT 80 to move up and down and is synchronized with the vertical synchronization signal V, is oscillated. The square wave Fv that oscillates vertically is power-amplified by the vertical deflection output unit 72 and supplied to the vertical deflection coil 79.

On the other hand, the composite video signal I amplified by the first video amplifying section 66 is a three primary color signal (R: red, G: green, B: blue, hereinafter referred to as "RGB") for reproducing and displaying a color image. In order to accurately demodulate the luminance signal and the two color difference signals, it is necessary to demodulate the luminance signal and the two color difference signals.

Generally, the luminance signal Y is supplied to the second video amplifier 73
, And is sent to the color output unit 78 while performing delay correction for adjusting the phase of the two color difference signals.
At the same time, the composite video signal I is separated by the color signal separation unit 74 into a color burst signal Fs and two color difference signals Z. The separated color burst signal Fs is amplified by the color burst amplifying section 75, and the subcarrier oscillating section 76 oscillates the color subcarrier Fsc of the same frequency used on the transmission side, and sends it to the color difference demodulation circuit section 77.

In the color difference demodulation circuit 77, a color signal separation section 74
, The two color difference signals Z separated by
Using the color subcarrier Fsc oscillating at the three primary color signals R and G
Demodulate B accurately.

The three primary color signals thus correctly demodulated are amplified by the color output section 78 with the added luminance signal Y corresponding to the transmitted three primary colors.
Are supplied to the three primary color input terminals RGB.

The audio signal has an audio intermediate frequency in an audio separation unit 81, is amplified in an audio intermediate frequency amplification unit 82, and then demodulates the audio signal FM-modulated by an audio detection unit 83. And is supplied to the speaker 85.

The video display can be viewed in this manner. Here, the NTSC system will be briefly described. N
The National Television System Committee (TSC) has been certified as a unified system for color TV broadcasting in the United States (black and white video is possible), and color TV broadcasting in Japan also adopts the NTSC system.

In the NTSC system, three primary color signals of R, G, and B are converted into a luminance signal Y, two color difference signals Z, and a synchronization signal H.
/ V and the composite video signal I
The composite video signal is transmitted by a residual sideband amplitude modulation using a video signal carrier / audio signal carrier / color subcarrier.

In the NTSC system, the following relationship is strictly defined between the color sub-carrier frequency Fsc and the horizontal synchronizing frequency Fh and the vertical synchronizing frequency Fv constituting the composite video signal. Fsc = 455/2 × Fh = 455/2 × 525/2 × F
v Normally, the frequency of a system clock (hereinafter abbreviated as “system clock”) for controlling various signal processing circuits of a digital circuit system in a color video display device is a color subcarrier F.
Frequently, four times the frequency of sc is used. Therefore, a self-synchronous system that generates a synchronization signal based on the relationship of the system clock 4Fsc = 910 × Fh is a general video display device.

When this self-synchronous video display device catches a TV radio wave from a fixed transmitting station in a fixed direction with a fixed antenna, the video signal can be received stably at a certain electric field intensity, so that a good image is always obtained. Can be played.

[0017]

However, moving vehicles,
For example, in the case of an in-vehicle image display device such as an automobile or a train,
Due to a change in the moving environment, topography, and the like, a sudden change in the electric field intensity occurs, making it impossible to always reproduce good images.

This is due to the attenuation of the electric field strength during the movement. Even in the first video amplifier 66 in FIG. 6, a sufficient amplification gain cannot be obtained, and the composite video signal I decreases. Due to the decrease of the composite video signal I, the synchronization signal H / V detected by the subsequent synchronization signal separation unit 67 and the color signal separation unit 74
This makes it impossible to accurately detect the color subcarrier Fs and the two color difference signals Z, etc., which are detected in step (1).

As a result, the oscillation frequency Fsc of the sub-carrier oscillating section 76 becomes unstable, and the color sub-carrier Fsc = 455/2 × Fh stipulated in the NTSC system is not established. Therefore, the relationship of 4Fsc = 910 × Fh of the system clock oscillation unit 90 generated from the output Fsc of the subcarrier oscillation unit 76 becomes inaccurate, causing a problem that the image display device cannot reproduce a good image.

The present invention has been made in view of such circumstances, and has as its object to stabilize reproduced images on a moving image display device.

[0021]

SUMMARY OF THE INVENTION The present invention relates to a self-synchronous video display device for generating a system clock signal and a synchronizing signal using a composite video signal, and comprising: Means, a color burst detecting means for detecting a color subcarrier using the composite video signal, a system clock generating means for inputting a detection signal of the color burst detecting means, and an input of a generating signal of the system clock generating means. Controlling the validity / invalidity of the detection signal of the color burst detecting means and controlling the composite synchronizing signal generating means by using the composite synchronizing signal generating means and the detection signal of the composite video signal and the video signal decrease detecting means. A synchronizing signal processing circuit of a video display device comprising a synchronizing signal validating / invalidating means. A / D converting means for converting the three primary color signals from an analog signal to a digital signal, the A / D
Memory means for holding the output of the conversion means, calculation means for calculating the difference between the output of the memory means and the output of the A / D conversion means, and comparison calculation means for comparing the output value of the calculation means with a predetermined value Wherein the video signal decrease detection means detects a decrease in the composite video signal based on an output of the comparison operation means.

Further, the present invention is characterized in that control means for controlling the memory means by using an output of the comparison operation means is provided.

Furthermore, the present invention is characterized in that the memory means holds the output of the A / D conversion means in pixel units.

The present invention further comprises address control means for separating the synchronizing signal from the composite video signal and controlling the memory means, and the memory means holds the output of the A / D conversion means in line units. It is characterized by the following.

Further, the present invention comprises frame memory control means for controlling the memory means by separating a synchronizing signal from the composite video signal, and the memory means holds the output of the A / D conversion means on a frame basis. It is characterized by doing.

[0026]

According to the present invention, a system clock and a synchronizing signal having a phase difference corresponding to a color burst immediately before the decrease are detected by detecting a decrease in the A / D conversion output of the luminance signal of the composite video signal or the three primary color signals. It is possible to always see a stable image display without being affected by the electric field strength during movement.

Further, according to the present invention, the amount of change in pixel units,
The decrease in the A / D conversion output can be detected from the change amount of each pixel in line units and the change amount of each pixel in frame units.

[0028]

Next, a specific embodiment of a signal processing circuit of a video display device according to the present invention will be described with reference to FIG. FIG. 1A is a basic configuration diagram, and FIG. 1B shows a composite video signal I, a horizontal synchronizing signal Fh and a color burst signal F.
FIG. 4 is a schematic waveform diagram of a multiplexed signal of sc, a color video signal (one line), and a vertical synchronization signal (V) (not shown). FIG. 3C shows a color burst valid signal Cg generated by the synchronizing signal valid / invalid means 5.

Now, in a normal case where the electric field strength during movement is large and the input of the composite video signal I is sufficient, the video signal decrease detection means 1 does not detect the decrease signal Iz. Therefore, the synchronizing signal valid / invalid means 5 outputs the color burst valid signal Cg.
Is sent.

Therefore, the color burst detecting means 2 detects the color subcarrier Fsc contained in the composite video signal I, and as a system clock generating means 3, a phase locked loop circuit (P
LL: Phase-Locked Loop: hereinafter, abbreviated as "PLL circuit"), generates and outputs a system clock 4Fsc = 910 × Fh that oscillates extremely stably.

The synchronizing signal valid / invalid means 5 is provided with a system clock 4 which the composite synchronizing signal generating means 4 counts.
A reset signal Rs for Fsc is output. As a result, the composite synchronizing signal generating means 4 generates and outputs a composite synchronizing signal such as a horizontal synchronizing signal / return signal / vertical synchronizing signal H / V. Normally, stable video display is performed by such an operation signal.

If the strength of the electric field during movement is weak and the composite video signal I decreases, the video signal decrease detection means 1 sends the decrease signal Iz immediately after the decrease. As a result, the synchronizing signal valid / invalidating means 5 stops sending the valid signal Cg in order to invalidate the color burst valid signal Cg. Also, the transmission of the reset signal Rs for 4Fsc counted by the composite synchronization signal generation means 4 is stopped.

Therefore, P of the system clock generating means 3
The LL circuit can continuously generate and output the system clock 4Fsc having a phase difference corresponding to the color subcarrier Fsc immediately before the decrease.

The continuously generated system clock 4Fsc
The composite synchronizing signal generation means 4 for counting the number of self-generated reset signals, and can continuously generate and output a composite synchronizing signal such as a horizontal synchronizing signal / return signal / vertical synchronizing signal H / V. Therefore, it is possible to use these generated signals, and the moving image display device is not affected by the electric field strength due to its environment and terrain.
A good image can be displayed.

FIG. 2 shows a first method for detecting a decrease in the composite video signal.
Shows an embodiment, built-in video IF-AGC IC
(LA7530N), an internal setting voltage Sv, a comparison operation means 7, and a capacitor C for AC bypass.

Now, when the intensity of the electric field during movement is small and the composite video signal I is reduced, the output terminal pin of the operational amplifier circuit of the IC internal circuit 6 is provided with the gain of the video intermediate frequency amplification for compensating the weak input signal. Voltage Av for improving
Can be taken out.

The compensating voltage Av of this pin and the internal setting voltage Sv are compared and calculated by the comparing and calculating means 7, and when the compensating voltage Av exceeds the internal setting value Sv, a decrease signal indicating that the composite video signal I has decreased. Iz can be detected.

FIG. 3 shows a second method for detecting a decrease in the composite video signal.
FIG. 1 shows an embodiment, in which an A / D conversion unit 8, a pixel memory unit 9, a pixel operation unit 10, a comparison operation unit 11,
It is constituted by the pixel control means 12.

Now, when the intensity of the electric field during movement is small and the composite video signal I decreases, the luminance signal Y or the three primary color signals R and G
B also decreases, and the output after A / D conversion also decreases. The pixel calculation means 10 subtracts the output value of the pixel memory means 9 from the output value of the A / D conversion means 8 and outputs a pixel change amount Gv.

The pixel change amount Gv and the internal set value Sv are compared and calculated by the comparison calculation means 11, and the pixel change amount Gv is calculated.
Is greater than or equal to the internal set value Sv, a decrease signal Iz indicating that the composite video signal I has decreased can be detected. At the same time, the pixel control unit 12 invalidates the system clock 4Fsc at the timing when the decrease signal Iz is detected, so that the pixel memory unit 9 does not hold the next pixel.

FIG. 4 shows a third method for detecting a decrease in the composite video signal.
Embodiment 2 shows an embodiment, which is different from the second embodiment described above.
The point is that a line memory means 14 for holding the data in units of lines and a synchronization separation address control means 15 for controlling the same are provided. The synchronization separation address control means 15 controls the line memory means 14 using a signal ad for specifying an address of the line memory means 14, a read signal R, and a write signal W.

Now, when the electric field strength during movement is weak and the composite video signal I decreases, the luminance signal Y or the three primary color signals R, G,
B also decreases, and the output after A / D conversion also decreases. The line calculation means 16 subtracts the output value of the line memory means 14 from the output value of the A / D conversion means 13 and outputs a pixel change Lv for each line.

The pixel change amount Lv in line units and the internal set value Sv are compared and calculated by the comparison calculation means 17, and when the change amount Lv becomes equal to or larger than the internal set value Sv, a decrease indicating that the composite video signal I has decreased. The signal Iz can be detected. At the same time, the line control means 18 outputs the decrease signal Iz
Is invalidated at the timing when is detected, so that the line memory means 14 does not hold the next pixel in a line unit.

FIG. 5 shows a fourth method for detecting a decrease in the composite video signal.
The present embodiment is different from the above-described embodiments in that a frame memory means 20 for holding a frame unit only when the composite video signal I is a still image, and a sync separation frame memory control means for controlling the same. 21. The sync separation frame memory control means 21 controls the frame memory means 20 using a signal ad designating an address of the frame memory means 20, a read signal R, and a write signal W.

Now, when the electric field strength during movement is weak and the composite video signal I decreases, the luminance signal Y or the three primary color signals R, G,
B also decreases, and the output after A / D conversion also decreases. The frame operation unit 22 subtracts the output value of the frame memory unit 20 from the output value of the A / D conversion unit 19, and outputs a pixel change amount Fv for each frame.

The pixel change amount Fv for each frame and the internal set value Sv are compared and calculated by the comparison calculation means 23.
When the variation Fv becomes equal to or greater than the internal set value Sv, a decrease signal Iz indicating that the composite video signal I has decreased can be detected. At the same time, the frame control means 24 outputs the decrease signal I
At the timing when z is detected, the write signal W is invalidated so that the frame memory unit 20 does not hold the next frame unit pixel.

In this embodiment, the line control means 18 and the Fourem control means 24 shown in FIGS. 4 and 5 make the write signal W of each memory means invalid, but the address designation signal ad or the read signal R May be invalidated.

[0048]

As described above, according to the present invention, by detecting a decrease in a composite video signal, a system clock and a synchronization signal having a phase difference corresponding to a color burst immediately before the decrease can be generated. There is a great advantage that a stable image display can always be seen without being affected by the electric field strength during movement.

[Brief description of the drawings]

FIG. 1 is a basic configuration diagram of a signal processing circuit illustrating a basic principle of the present invention.

FIG. 2 is a configuration diagram showing a first embodiment of a composite video signal decrease detection unit of the present invention.

FIG. 3 is a block diagram showing a second embodiment of the composite video signal decrease detecting means of the present invention.

FIG. 4 is a block diagram showing a third embodiment of the composite video signal decrease detection means of the present invention.

FIG. 5 is a block diagram showing a fourth embodiment of the composite video signal decrease detection means of the present invention.

FIG. 6 is a block diagram showing the entire configuration of a conventional video display device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Video signal decrease detection means 2 Color burst detection means 3 System clock generation means 4 Composite synchronization signal generation means 5 Synchronization signal valid / invalid means 6 IF-AGC circuit 7.1.11.23 Comparison operation means 8.13.19 A / D conversion means 9.14.20 Memory means 10.16.22 Calculation means 12.18.24 Memory control means 15 Address control means 21 Frame memory control means

Claims (5)

(57) [Claims] 1. A self-synchronous video display device that generates a system clock signal and a synchronizing signal using a composite video signal, comprising: a video signal decrease detection unit that detects a decrease in the composite video signal; A color burst detection unit that detects a color subcarrier used, a system clock generation unit that receives a detection signal of the color burst detection unit as an input, a composite synchronization signal generation unit that receives a generation signal of the system clock generation unit as an input, A synchronizing signal validating / invalidating means for controlling the validity / invalidity of the detection signal of the color burst detecting means and controlling the composite synchronizing signal generating means by using the composite video signal and the detection signal of the video signal decrease detecting means; A synchronizing signal processing circuit of a video display device having a A / D conversion means for converting an analog signal to a digital signal; memory means for holding the output of the A / D conversion means; and arithmetic operation for calculating the difference between the output of the memory means and the output of the A / D conversion means. Means, and comparison operation means for comparing an output value of the operation means with a predetermined value, wherein the video signal decrease detection means detects a decrease in the composite video signal based on an output of the comparison operation means. A synchronizing signal processing circuit for a video display device, comprising: 2. The synchronization signal processing circuit according to claim 1, further comprising control means for controlling said memory means using an output of said comparison operation means. Processing circuit. 3. The synchronizing signal processing circuit according to claim 1, wherein said memory means holds an output of said A / D conversion means on a pixel basis. Synchronous signal processing circuit. 4. The synchronizing signal processing circuit of the video display device according to claim 1, further comprising: an address control unit that separates a synchronizing signal from the composite video signal and controls the memory unit. A synchronizing signal processing circuit for a video display device, wherein the output of the A / D conversion means is held for each line. 5. The synchronizing signal processing circuit of a video display device according to claim 1, further comprising: a frame memory control unit that separates a synchronizing signal from the composite video signal and controls the memory unit. Wherein the output of the A / D conversion means is held in frame units.