JPH04183077A - Picture processor - Google Patents

Abstract

PURPOSE:To make a wipe control area coincident with an effective picture area by executing scroll display in the effective picture display area when executing the scroll display of a picture stored in an image memory. CONSTITUTION:When executing superimpose, picture data stored in a memory 38 are read out and impressed through a memory interface 36 to one input of an AND circuit 39. When executing the scroll display of the picture stored in the memory 38, the scroll display is executed in the effective picture display area. Thus, a wipe operation can be executed over all the effective picture area and even when a memory area is smaller than the effective picture area, the wipe operation is smoothly executed from the edge to edge of a screen.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an image processing device, and more specifically to an image processing device in a digital superimposing device.

[Prior Art] Conventionally, for example, in a camera-integrated video tape recorder, the video signal of an image to be superimposed, such as a title picture, is binarized and stored in a memory, and then read out from the memory and converted into a specific image. A digital superimposing device is used that converts the color signal into a color signal and then superimposes it on the video signal to be photographed.

There is a method called wiping as a display method for superimposing, and in this method, images such as the title image are gradually displayed on the screen (hereinafter referred to as wipe-in). When erasing (below,
This is called wipe out. ), or in either case, the area where the display appears and disappears (hereinafter referred to as the wipe control area) corresponds to the memory area (the area indicated by C in Figure 4). was.

[Problems to be Solved by the Invention] However, the conventional example described above has the following drawbacks when the memory area is small compared to the effective screen area (the area indicated by B in FIG. 4). That is, for example, the effective scanning lines of the PAL system are 2875 per field, but the size of a general-purpose memory is preferably a power of 2, and the effective scanning lines of the NTSC system are 242 per field.
Since there are many cases where the NTSC system and the PAL system are compatible in the same system, 256 is allocated as the memory size. As a result, in the case of the PAL system, the effective area of the memory becomes smaller in the vertical direction than the effective screen area.

By the way, there are two display methods for superimposing: a method of superimposing on the black part of the input video signal when storing it in memory (hereinafter referred to as blackout mode), and a method of superimposing on the white part (hereinafter referred to as blackout mode). below,
There is a mode called "outline mode". As mentioned above, if you perform white mode when the memory area is small compared to the effective screen area, the same color as the title image will be superimposed on the insufficient memory area (the area indicated by diagonal lines in Figure 4). I try to do that.

Therefore, if you want to superimpose the same color as the title image even in an area with insufficient memory, and when you perform a wipe-out operation, first all the superimpositions in the area with insufficient memory will be erased, and then the reverse will occur from one direction, up, down, left, and right. The movement was unnatural as it gradually disappeared in the direction of . On the contrary, in the wipe-in operation, first, the same color as the title is superimposed on the memory insufficient area, and then the title gradually appears from one direction to the top, bottom, left, right, and the other direction.

An object of the present invention is to provide an image processing device that eliminates such inconveniences.

[Means for Solving the Problems] An image processing device according to the present invention is a device that processes an image smaller than the storage area of an image memory or an effective image display area, and scrolls the image stored in the image memory. When displayed, scroll display is performed within the effective image display area.

Further, the image processing device according to the second aspect of the present invention provides a suit image processing device that superimposes a binary image stored in the memory means as an image of a predetermined color on an input video signal, in which a count indicating one end of a wipe control area is provided. hold the value,
a counter means for counting a predetermined clock; a coincidence detection means for comparing a count value indicating a display position of a screen area with a count value of the counter means; and display control defined by a coincidence detection result of the coincidence detection means. and key signal generating means for generating a key signal.

[Operation] With the above means, the wipe control area and the effective screen area become coincident. Therefore, the above-mentioned disadvantages are eliminated.

[Example] Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of the configuration of an embodiment of the present invention, FIG. 2 is a block diagram of the configuration of a superimposing device incorporating this embodiment, and FIG. 3 is a block diagram of the title generation circuit of FIG. 2. shows.

First, FIG. 2 will be explained. Reference numeral 10 denotes an input terminal for a luminance signal of a human video signal (a video signal of a title picture or a video signal for superimposing a title picture) supplied from an image pickup circuit (not shown), etc., and 12 a color signal of the input video signal. 14 is an input terminal for the horizontal synchronization signal H5sync, and 16 is an input terminal for the vertical synchronization signal Vsync. 18 is an A/D converter that binarizes the luminance signal input to the input terminal 1o, and 20 is a system control circuit that controls the entire system. Reference numeral 22 denotes a title generation circuit that stores the title image input to the input terminal 10 and generates a title image signal of a predetermined color, and includes an input terminal 22a.

22 b, 22 c, 22 d and output terminal 2
2e, 22f, 22g, and 22h. 24 is a matrix circuit that converts the RGB output from the title generation circuit 22 into a luminance signal Y and color difference signals RY and l3-Y; 26;
is an encoder that converts the color difference signals R-Y and B-Y from the matrix circuit 24 into color signals.

28.30 is a switch that can be switched to the control signal from the output terminal 22h of the title generation circuit 22; the switch 28 selects the luminance signal from the input terminal 10 or the luminance signal output from the matrix circuit 24;
0 selects the color signal of the input terminal 12 or the color signal output from the encoder 26. 32 is an output terminal for a luminance signal superimposed with a title, and 34 is an output terminal for a color signal superimposed on a title.

Briefly explaining the operation in FIG. 2, the luminance signal of the input video signal of the title picture is sent from the input terminal 10 to the A/D converter 1.
8, where it is binarized and input to the title generation circuit 22 from the input terminal 22a. The title generation circuit 22 outputs RGB signals of the title image to be stored from output terminals 22e, 22f, and 22g at the timing and color of the image output position controlled by the system control circuit 20 in accordance with the synchronization signal from the input terminal 14.16. It is output to the matrix circuit 24. The matrix circuit 24 converts the RGB signals into a luminance signal Y
The encoder 26 modulates the color difference signals RY and BY and outputs the color signal.

The system control circuit 20 specifies a title display method to the title generation circuit 22, and the title generation circuit 22 controls the switches 28 and 30 via the output terminal 22h in accordance with the specified display method. By switching the switches 28 and 30, the title picture is superimposed on the video signal input to the input terminal 10 and 12. In this way,
A video signal with a title image superimposed in a desired screen position, color, and display method is output from output terminals 32 and 34.

Details of the title generation circuit 22 will be explained with reference to FIG. Input terminals 22a, 22b, 22c.

22d and output terminals 22e, 22f, 22g, and 22h are the same as in FIG.

The binary image data from the A/D converter 18 is input to the input terminal 2.
2a and is stored in title memory 38 via memory interface 36.

When performing superimposition, the image data stored in the memory 38 is read out and applied to one of the AND circuits 39 via the memory interface 36. At this time, the timing generation circuit 40 generates a timing signal according to the horizontal synchronization signal H5ync inputted from the input terminal 22b, the vertical synchronization signal V5ync inputted to the input terminal 22c, and the clock from the clock generation circuit 42. , memory 38, horizontal position counter 44 and vertical position counter 4
Supply to 6. The horizontal position counter 44 outputs a count value indicating the horizontal position on the screen, and the vertical position counter 46 outputs a count value indicating the vertical position on the screen. The horizontal address generation circuit 48 generates a horizontal address for the title memory 38 according to the count value of the horizontal position counter 44, and the vertical address generation circuit 50 generates a horizontal address for the title memory 38 according to the count value of the vertical position counter 46. Generates vertical address. These addresses control the display position of the title.

The count values of the horizontal position counter 44 and the vertical position counter 46 are also applied to the display control circuit 52. Although the details will be described later, the display control circuit 52 counts the vertical synchronization signal V5sync from the input terminal 22c as a clock, and compares the count value with the count values from the counters 44 and 46 to form a key signal. Then, it is outputted to the other input of the ant circuit 39 from the output terminal 52f. This key signal is a signal that controls the range in which the title picture is displayed.

When the key signal is H, the AND circuit 39 supplies the title image data read from the title memory 38 to the RGB signal generation circuit 54. The mode control circuit 56 controls the display control circuit 52 in accordance with a control signal from the input terminal 22d (system control circuit 20), and controls the title color by the RGB signal generation circuit 54. The RGB signal generation circuit 54 forms an RGB format title image signal of a designated color and outputs it to the output terminals 22e, 22f, and 22g.The output of the AND circuit 39 is also transmitted from the output terminal 22h to the switch 28 as a switching control signal. Applied to .30.

Details of the display control circuit 52 will be explained with reference to FIG. Input terminal 52b from mode control circuit 56.

52c is supplied with a mode control signal instructing whether or not to perform a wipe operation, and these mote control signals are applied to an initial value setting circuit 58.60, which in turn applies the mode control signal to the initial value setting circuit 58.60. Accordingly, initial values are set for the horizontal wipe counter 62 and vertical wipe counter 64, respectively. AND circuit 66.68 is input terminal 5
Under the control of the mode control signals from 2b and 52C, the vertical synchronization signal V5sync at input terminal 52a is applied as a clock signal to horizontal wipe counter 62 and vertical wipe counter 64, respectively. Note that the horizontal wipe counter 62 and the vertical wipe counter 64 are connected to the input terminal 5.
It counts up or down according to the mote control signal from 2c.

In the end detection circuits 70 and 72, the end values of the horizontal wipe counter 62 and the vertical wipe counter 64 are respectively set according to the mode control signal from the input terminal 52c.・Counter 6
When the count value of 2 or the end value matches, the AND circuit 66
When the count value of the vertical wipe counter 64 matches the end value, the end detection circuit 72 puts the AND circuit 68 into a prohibited state.

Horizontal wipe counter 62 and vertical wipe counter 6
The count values of 4 are also supplied to coincidence detection circuits 74 and 76, respectively, and the coincidence detection circuit 74 outputs a coincidence signal when the horizontal position count value from the input terminal 52d and the count value of the horizontal wipe counter 62 match. occurrence, the coincidence detection circuit 76 receives the vertical position count value from the input terminal 52e, and
When the count value of the vertical wipe counter 64 matches, a match signal is generated. The key signal generation circuit 78 generates a key signal according to the output state of the match detection circuits 74 and 76. AND circuit 3 from this key signal or output terminal 52f
9 (FIG. 3), and the output area of the title is determined by the polarity of the key signal.

Next, the behavior when wiping in from above vertically,
In particular, the operation of the display control circuit 52 will be explained in more detail.

Input terminal 5 from mode control circuit 56 to display control circuit 52
2c, a mode control signal is input, and as a result, the initial value setting circuit 60 holds as an initial value the same value as the count value of the vertical position counter 46 indicating point b in FIG. 64 is set to count-up mode. Further, in response to the mode control signal from the input terminal 52c, the end detection circuit 72 is set to the same value as the count value of the vertical position counter 46 indicating the 0 point in FIG. The signal applied from the circuit 72 to the AND circuit 68 becomes "H".

Thereafter, the mode control circuit 56 supplies the input terminal 52b of the display control circuit 52 with a mode control signal instructing the start of the wipe operation. When this mote control signal is "H", it instructs to start wiping, and when it is "L", it instructs to stop wiping. In response to this mote control signal, the initial value setting circuit 60 loads the initial value it holds into the vertical wipe counter 64. Since this initial value is the same as the count value of the vertical position counter 46 indicating point b in FIG. ing. The mode control signal of the input terminal 52b is also applied to the AND circuit 68, and becomes "H" when the wipe is started. As a result, the input terminal 52
The vertical synchronization signal of a is now applied to the vertical wipe counter 72 as a clock.

The vertical wipe counter 72 counts up by 1 for each field, and the count value is detected by the end detection circuit 72.
When the output value matches the end value set in , the end detection circuit 72 sets the output to "L". As a result, the AND circuit 68 becomes disabled and the vertical wave counter 64 stops counting. That is, the count value of the vertical wipe counter 72 changes within the range from the upper end to the lower end of the effective screen area.

- The count value of the vertical wipe counter 72 and the count value of the vertical position counter 46 are supplied to the count output circuit 76. - The count output circuit 76 outputs a pulse signal when both count values match. Occur. Key signal generation circuit 78
In this example, the upper edge of the entire screen area (i.e. a
A key signal is generated which becomes "H" at point ) and "L" by the output pulse signal of the -number output circuit 76. In other words, the key signal is always "H" at the top of the entire screen area for each field, and on the other hand, the key signal is such that the "L" position gradually moves from the top to the bottom of the effective screen for each field. .

The key signal generated by the key signal generation circuit 78 is output from the output terminal 5.
It is applied to the AND circuit 39 via 2f. The output of the AND circuit 39 is applied as a switching control signal to the switch 28.30 via the output terminal 22h. ", the switch 28.30 is connected to the B contact side to output the title, and at other times the switch 28.30 is connected to the A contact side to output the video signal of the input terminal 10.12. Control so that it is output as is.

Through the above operations, the title is displayed from the upper end of the effective screen area, the title image area gradually expands downward, and finally the title is displayed up to the lower end of the effective screen area.

In the above embodiment, the vertical synchronization signal is used as the clock input for the horizontal wipe counter 62 and the vertical wipe counter 64, but a signal obtained by frequency-dividing the vertical synchronization signal may also be used. By controlling the frequency division ratio, the transition time of the wipe operation can be set arbitrarily.

[Effects of the Invention] As can be easily understood from the above description, according to the present invention, a wipe operation can be performed in the entire effective screen area. Even if the memory area is small compared to the effective screen area, the wipe operation is performed smoothly from edge to edge of the screen.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a configuration of an embodiment of the present invention, FIG. 2 is a block diagram of a superimpose device incorporating this embodiment, and FIG. 3 is a detailed circuit configuration of the title generation circuit 22 shown in FIG. The block diagram, FIG. 4, is an explanatory diagram of the screen layout. 10: Luminance signal input terminal 121 Color signal input terminal 14:
Horizontal synchronization signal input terminal 16: Vertical synchronization signal input terminal
18: A/D converter 20 system control circuit 2
2: Title generation circuit 22a.

Claims (2)

[Claims] (1) A device that processes images whose storage area in the image memory is smaller than the effective image display area, and when scrolling and displaying the images stored in the image memory, scroll display is performed within the effective image display area. An image processing device characterized by: (2) In a superimposing device that superimposes a binary image stored in a memory means as an image of a predetermined color onto an input video signal, a counter that holds a count value indicating one end of the wipe control area and counts a predetermined clock. a coincidence detection means for comparing a count value indicating a display position of the screen area with a count value of the counter means; and a key signal for generating a key signal for display control defined by the coincidence detection result of the coincidence detection means. An image processing device comprising: generating means.